| commit | 26c1532583a31650c83a7b502fc06504076157c8 | [log] [tgz] |
|---|---|---|
| author | Girish K S <girish@avatar.(none)> | Tue Nov 06 11:23:07 2012 +0100 |
| committer | John Rigby <john.rigby@linaro.org> | Thu Dec 06 13:51:47 2012 -0700 |
| tree | 5512827beab7de67abc3bdec708ea1ccae5f8a4a | |
| parent | ed3ca71f89bc0216e1bab7df0b9d689eeca0a40d [diff] |
The exynos dwmmc Ip has 2 stage divider. The first divider Register is in the vendor specific region of the dwmmc core (CLK_SEL), and second is part of the dwmmc generic registers (CLK_DIV). The goal of this patch is to maintain a 100MHz clock output before dividing it further by using the CLK_DIV. Depending on the card enumeration, it can be further divided by writing a correct divider in the dwmmc CLK_DIV register. Signed-off-by: Girish K S <ks.giri@samsung.com>