| /* DO NOT EDIT THIS FILE |
| * Automatically generated by generate-def-headers.xsl |
| * DO NOT EDIT THIS FILE |
| */ |
| |
| #ifndef __BFIN_DEF_ADSP_BF504_proc__ |
| #define __BFIN_DEF_ADSP_BF504_proc__ |
| |
| #include "../mach-common/ADSP-EDN-core_def.h" |
| |
| #define PLL_CTL 0xFFC00000 /* PLL Control Register */ |
| #define PLL_DIV 0xFFC00004 /* PLL Divide Register */ |
| #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ |
| #define PLL_STAT 0xFFC0000C /* PLL Status Register */ |
| #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ |
| #define CHIPID 0xFFC00014 |
| #define SWRST 0xFFC00100 /* Software Reset Register */ |
| #define SYSCR 0xFFC00104 /* System Configuration register */ |
| #define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ |
| #define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ |
| #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ |
| #define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ |
| #define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ |
| #define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ |
| #define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ |
| #define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ |
| #define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */ |
| #define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */ |
| #define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */ |
| #define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */ |
| #define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */ |
| #define SIC_ISR1 0xFFC00160 /* Interrupt Status register */ |
| #define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */ |
| #define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ |
| #define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ |
| #define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ |
| #define UART0_DLL 0xFFC00400 /* Divisor Latch Low Byte */ |
| #define UART0_DLH 0xFFC00404 /* Divisor Latch High Byte */ |
| #define UART0_GCTL 0xFFC00408 /* Global Control Register */ |
| #define UART0_LCR 0xFFC0040C /* Line Control Register */ |
| #define UART0_MCR 0xFFC00410 /* Modem Control Register */ |
| #define UART0_LSR 0xFFC00414 /* Line Status Register */ |
| #define UART0_MSR 0xFFC00418 /* Modem Status Register */ |
| #define UART0_SCR 0xFFC0041C /* Scratch Register */ |
| #define UART0_IER_SET 0xFFC00420 /* Interrupt Enable Register Set */ |
| #define UART0_IER_CLEAR 0xFFC00424 /* Interrupt Enable Register Clear */ |
| #define UART0_THR 0xFFC00428 /* Transmit Hold Register */ |
| #define UART0_RBR 0xFFC0042C /* Receive Buffer Register */ |
| #define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */ |
| #define SPI0_FLG 0xFFC00504 /* SPI0 Flag register */ |
| #define SPI0_STAT 0xFFC00508 /* SPI0 Status register */ |
| #define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */ |
| #define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */ |
| #define SPI0_BAUD 0xFFC00514 /* SPI0 Baud rate Register */ |
| #define SPI0_SHADOW 0xFFC00518 /* SPI0_RDBR Shadow Register */ |
| #define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ |
| #define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ |
| #define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ |
| #define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ |
| #define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ |
| #define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ |
| #define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ |
| #define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ |
| #define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ |
| #define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ |
| #define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ |
| #define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ |
| #define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */ |
| #define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */ |
| #define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */ |
| #define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */ |
| #define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */ |
| #define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */ |
| #define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */ |
| #define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */ |
| #define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */ |
| #define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */ |
| #define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */ |
| #define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */ |
| #define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */ |
| #define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */ |
| #define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */ |
| #define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register\n */ |
| #define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */ |
| #define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */ |
| #define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */ |
| #define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ |
| #define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ |
| #define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */ |
| #define TIMER_STATUS 0xFFC00688 /* Timer Status Register */ |
| #define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */ |
| #define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */ |
| #define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */ |
| #define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */ |
| #define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */ |
| #define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */ |
| #define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */ |
| #define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */ |
| #define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */ |
| #define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */ |
| #define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */ |
| #define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */ |
| #define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */ |
| #define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */ |
| #define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */ |
| #define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */ |
| #define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */ |
| #define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ |
| #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ |
| #define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ |
| #define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ |
| #define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ |
| #define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ |
| #define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ |
| #define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ |
| #define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ |
| #define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ |
| #define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ |
| #define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ |
| #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ |
| #define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ |
| #define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ |
| #define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ |
| #define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ |
| #define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ |
| #define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ |
| #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ |
| #define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ |
| #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ |
| #define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ |
| #define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ |
| #define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ |
| #define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ |
| #define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ |
| #define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ |
| #define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ |
| #define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ |
| #define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ |
| #define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ |
| #define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ |
| #define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ |
| #define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ |
| #define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ |
| #define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ |
| #define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ |
| #define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ |
| #define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ |
| #define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ |
| #define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ |
| #define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ |
| #define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ |
| #define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ |
| #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ |
| #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ |
| #define EBIU_MODE 0xFFC00A20 /* Asynchronous Memory Mode Control Register */ |
| #define EBIU_FCTL 0xFFC00A24 /* Asynchronous Memory Parameter Control Register */ |
| #define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ |
| #define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ |
| #define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ |
| #define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ |
| #define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ |
| #define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ |
| #define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ |
| #define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ |
| #define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ |
| #define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ |
| #define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ |
| #define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ |
| #define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ |
| #define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ |
| #define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ |
| #define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ |
| #define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ |
| #define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ |
| #define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ |
| #define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ |
| #define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ |
| #define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ |
| #define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ |
| #define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ |
| #define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ |
| #define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ |
| #define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ |
| #define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ |
| #define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ |
| #define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ |
| #define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ |
| #define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ |
| #define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ |
| #define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ |
| #define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ |
| #define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ |
| #define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ |
| #define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ |
| #define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ |
| #define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ |
| #define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ |
| #define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ |
| #define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ |
| #define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ |
| #define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ |
| #define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ |
| #define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ |
| #define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ |
| #define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ |
| #define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ |
| #define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ |
| #define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ |
| #define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ |
| #define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ |
| #define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ |
| #define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ |
| #define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ |
| #define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ |
| #define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ |
| #define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ |
| #define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ |
| #define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ |
| #define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ |
| #define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ |
| #define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ |
| #define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ |
| #define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ |
| #define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ |
| #define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ |
| #define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ |
| #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ |
| #define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ |
| #define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ |
| #define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ |
| #define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ |
| #define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ |
| #define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ |
| #define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ |
| #define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ |
| #define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ |
| #define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ |
| #define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ |
| #define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ |
| #define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ |
| #define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ |
| #define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ |
| #define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ |
| #define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ |
| #define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ |
| #define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ |
| #define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ |
| #define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ |
| #define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ |
| #define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ |
| #define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ |
| #define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ |
| #define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ |
| #define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ |
| #define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ |
| #define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ |
| #define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ |
| #define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ |
| #define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ |
| #define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ |
| #define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ |
| #define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ |
| #define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ |
| #define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ |
| #define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ |
| #define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ |
| #define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ |
| #define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ |
| #define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ |
| #define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ |
| #define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ |
| #define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ |
| #define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ |
| #define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ |
| #define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ |
| #define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ |
| #define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ |
| #define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ |
| #define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ |
| #define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ |
| #define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ |
| #define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ |
| #define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ |
| #define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ |
| #define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ |
| #define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ |
| #define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ |
| #define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ |
| #define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ |
| #define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ |
| #define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ |
| #define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ |
| #define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ |
| #define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ |
| #define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ |
| #define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ |
| #define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ |
| #define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ |
| #define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ |
| #define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ |
| #define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ |
| #define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ |
| #define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ |
| #define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ |
| #define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ |
| #define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ |
| #define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ |
| #define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ |
| #define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ |
| #define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ |
| #define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ |
| #define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ |
| #define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ |
| #define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */ |
| #define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */ |
| #define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */ |
| #define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */ |
| #define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */ |
| #define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */ |
| #define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ |
| #define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */ |
| #define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */ |
| #define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */ |
| #define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */ |
| #define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */ |
| #define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ |
| #define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */ |
| #define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */ |
| #define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */ |
| #define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */ |
| #define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */ |
| #define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */ |
| #define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ |
| #define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */ |
| #define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ |
| #define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */ |
| #define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */ |
| #define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */ |
| #define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ |
| #define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */ |
| #define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */ |
| #define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */ |
| #define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */ |
| #define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */ |
| #define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */ |
| #define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ |
| #define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */ |
| #define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ |
| #define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */ |
| #define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */ |
| #define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */ |
| #define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ |
| #define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */ |
| #define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */ |
| #define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */ |
| #define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */ |
| #define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */ |
| #define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */ |
| #define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ |
| #define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */ |
| #define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ |
| #define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */ |
| #define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */ |
| #define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */ |
| #define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ |
| #define PPI_STATUS 0xFFC01004 /* PPI Status Register */ |
| #define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ |
| #define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ |
| #define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ |
| #define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ |
| #define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ |
| #define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ |
| #define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ |
| #define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ |
| #define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ |
| #define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ |
| #define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ |
| #define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ |
| #define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ |
| #define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ |
| #define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ |
| #define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ |
| #define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ |
| #define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ |
| #define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ |
| #define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ |
| #define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */ |
| #define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */ |
| #define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */ |
| #define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */ |
| #define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */ |
| #define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */ |
| #define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */ |
| #define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */ |
| #define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */ |
| #define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */ |
| #define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */ |
| #define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */ |
| #define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */ |
| #define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */ |
| #define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */ |
| #define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */ |
| #define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */ |
| #define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */ |
| #define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */ |
| #define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */ |
| #define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */ |
| #define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */ |
| #define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */ |
| #define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */ |
| #define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */ |
| #define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */ |
| #define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */ |
| #define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */ |
| #define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */ |
| #define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */ |
| #define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */ |
| #define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */ |
| #define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */ |
| #define UART1_DLL 0xFFC02000 /* Divisor Latch Low Byte */ |
| #define UART1_DLH 0xFFC02004 /* Divisor Latch High Byte */ |
| #define UART1_GCTL 0xFFC02008 /* Global Control Register */ |
| #define UART1_LCR 0xFFC0200C /* Line Control Register */ |
| #define UART1_MCR 0xFFC02010 /* Modem Control Register */ |
| #define UART1_LSR 0xFFC02014 /* Line Status Register */ |
| #define UART1_MSR 0xFFC02018 /* Modem Status Register */ |
| #define UART1_SCR 0xFFC0201C /* Scratch Register */ |
| #define UART1_IER_SET 0xFFC02020 /* Interrupt Enable Register Set */ |
| #define UART1_IER_CLEAR 0xFFC02024 /* Interrupt Enable Register Clear */ |
| #define UART1_THR 0xFFC02028 /* Transmit Hold Register */ |
| #define UART1_RBR 0xFFC0202C /* Receive Buffer Register */ |
| #define CAN_MC1 0xFFC02A00 /* CAN Controller 0 Mailbox Configuration Register 1 */ |
| #define CAN_MD1 0xFFC02A04 /* CAN Controller 0 Mailbox Direction Register 1 */ |
| #define CAN_TRS1 0xFFC02A08 /* CAN Controller 0 Transmit Request Set Register 1 */ |
| #define CAN_TRR1 0xFFC02A0C /* CAN Controller 0 Transmit Request Reset Register 1 */ |
| #define CAN_TA1 0xFFC02A10 /* CAN Controller 0 Transmit Acknowledge Register 1 */ |
| #define CAN_AA1 0xFFC02A14 /* CAN Controller 0 Abort Acknowledge Register 1 */ |
| #define CAN_RMP1 0xFFC02A18 /* CAN Controller 0 Receive Message Pending Register 1 */ |
| #define CAN_RML1 0xFFC02A1C /* CAN Controller 0 Receive Message Lost Register 1 */ |
| #define CAN_MBTIF1 0xFFC02A20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */ |
| #define CAN_MBRIF1 0xFFC02A24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */ |
| #define CAN_MBIM1 0xFFC02A28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */ |
| #define CAN_RFH1 0xFFC02A2C /* CAN Controller 0 Remote Frame Handling Enable Register 1 */ |
| #define CAN_OPSS1 0xFFC02A30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */ |
| #define CAN_MC2 0xFFC02A40 /* CAN Controller 0 Mailbox Configuration Register 2 */ |
| #define CAN_MD2 0xFFC02A44 /* CAN Controller 0 Mailbox Direction Register 2 */ |
| #define CAN_TRS2 0xFFC02A48 /* CAN Controller 0 Transmit Request Set Register 2 */ |
| #define CAN_TRR2 0xFFC02A4C /* CAN Controller 0 Transmit Request Reset Register 2 */ |
| #define CAN_TA2 0xFFC02A50 /* CAN Controller 0 Transmit Acknowledge Register 2 */ |
| #define CAN_AA2 0xFFC02A54 /* CAN Controller 0 Abort Acknowledge Register 2 */ |
| #define CAN_RMP2 0xFFC02A58 /* CAN Controller 0 Receive Message Pending Register 2 */ |
| #define CAN_RML2 0xFFC02A5C /* CAN Controller 0 Receive Message Lost Register 2 */ |
| #define CAN_MBTIF2 0xFFC02A60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */ |
| #define CAN_MBRIF2 0xFFC02A64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */ |
| #define CAN_MBIM2 0xFFC02A68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */ |
| #define CAN_RFH2 0xFFC02A6C /* CAN Controller 0 Remote Frame Handling Enable Register 2 */ |
| #define CAN_OPSS2 0xFFC02A70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */ |
| #define CAN_CLOCK 0xFFC02A80 /* CAN Controller 0 Clock Register */ |
| #define CAN_TIMING 0xFFC02A84 /* CAN Controller 0 Timing Register */ |
| #define CAN_DEBUG 0xFFC02A88 /* CAN Controller 0 Debug Register */ |
| #define CAN_STATUS 0xFFC02A8C /* CAN Controller 0 Global Status Register */ |
| #define CAN_CEC 0xFFC02A90 /* CAN Controller 0 Error Counter Register */ |
| #define CAN_GIS 0xFFC02A94 /* CAN Controller 0 Global Interrupt Status Register */ |
| #define CAN_GIM 0xFFC02A98 /* CAN Controller 0 Global Interrupt Mask Register */ |
| #define CAN_GIF 0xFFC02A9C /* CAN Controller 0 Global Interrupt Flag Register */ |
| #define CAN_CONTROL 0xFFC02AA0 /* CAN Controller 0 Master Control Register */ |
| #define CAN_INTR 0xFFC02AA4 /* CAN Controller 0 Interrupt Pending Register */ |
| #define CAN_MBTD 0xFFC02AAC /* CAN Controller 0 Mailbox Temporary Disable Register */ |
| #define CAN_EWR 0xFFC02AB0 /* CAN Controller 0 Programmable Warning Level Register */ |
| #define CAN_ESR 0xFFC02AB4 /* CAN Controller 0 Error Status Register */ |
| #define CAN_UCCNT 0xFFC02AC4 /* CAN Controller 0 Universal Counter Register */ |
| #define CAN_UCRC 0xFFC02AC8 /* CAN Controller 0 Universal Counter Force Reload Register */ |
| #define CAN_UCCNF 0xFFC02ACC /* CAN Controller 0 Universal Counter Configuration Register */ |
| #define CAN_AM00L 0xFFC02B00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */ |
| #define CAN_AM00H 0xFFC02B04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */ |
| #define CAN_AM01L 0xFFC02B08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */ |
| #define CAN_AM01H 0xFFC02B0C /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */ |
| #define CAN_AM02L 0xFFC02B10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */ |
| #define CAN_AM02H 0xFFC02B14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */ |
| #define CAN_AM03L 0xFFC02B18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */ |
| #define CAN_AM03H 0xFFC02B1C /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */ |
| #define CAN_AM04L 0xFFC02B20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */ |
| #define CAN_AM04H 0xFFC02B24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */ |
| #define CAN_AM05L 0xFFC02B28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */ |
| #define CAN_AM05H 0xFFC02B2C /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */ |
| #define CAN_AM06L 0xFFC02B30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */ |
| #define CAN_AM06H 0xFFC02B34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */ |
| #define CAN_AM07L 0xFFC02B38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */ |
| #define CAN_AM07H 0xFFC02B3C /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */ |
| #define CAN_AM08L 0xFFC02B40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */ |
| #define CAN_AM08H 0xFFC02B44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */ |
| #define CAN_AM09L 0xFFC02B48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */ |
| #define CAN_AM09H 0xFFC02B4C /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */ |
| #define CAN_AM10L 0xFFC02B50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */ |
| #define CAN_AM10H 0xFFC02B54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */ |
| #define CAN_AM11L 0xFFC02B58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */ |
| #define CAN_AM11H 0xFFC02B5C /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */ |
| #define CAN_AM12L 0xFFC02B60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */ |
| #define CAN_AM12H 0xFFC02B64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */ |
| #define CAN_AM13L 0xFFC02B68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */ |
| #define CAN_AM13H 0xFFC02B6C /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */ |
| #define CAN_AM14L 0xFFC02B70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */ |
| #define CAN_AM14H 0xFFC02B74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */ |
| #define CAN_AM15L 0xFFC02B78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */ |
| #define CAN_AM15H 0xFFC02B7C /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */ |
| #define CAN_AM16L 0xFFC02B80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */ |
| #define CAN_AM16H 0xFFC02B84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */ |
| #define CAN_AM17L 0xFFC02B88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */ |
| #define CAN_AM17H 0xFFC02B8C /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */ |
| #define CAN_AM18L 0xFFC02B90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */ |
| #define CAN_AM18H 0xFFC02B94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */ |
| #define CAN_AM19L 0xFFC02B98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */ |
| #define CAN_AM19H 0xFFC02B9C /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */ |
| #define CAN_AM20L 0xFFC02BA0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */ |
| #define CAN_AM20H 0xFFC02BA4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */ |
| #define CAN_AM21L 0xFFC02BA8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */ |
| #define CAN_AM21H 0xFFC02BAC /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */ |
| #define CAN_AM22L 0xFFC02BB0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */ |
| #define CAN_AM22H 0xFFC02BB4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */ |
| #define CAN_AM23L 0xFFC02BB8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */ |
| #define CAN_AM23H 0xFFC02BBC /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */ |
| #define CAN_AM24L 0xFFC02BC0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */ |
| #define CAN_AM24H 0xFFC02BC4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */ |
| #define CAN_AM25L 0xFFC02BC8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */ |
| #define CAN_AM25H 0xFFC02BCC /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */ |
| #define CAN_AM26L 0xFFC02BD0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */ |
| #define CAN_AM26H 0xFFC02BD4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */ |
| #define CAN_AM27L 0xFFC02BD8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */ |
| #define CAN_AM27H 0xFFC02BDC /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */ |
| #define CAN_AM28L 0xFFC02BE0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */ |
| #define CAN_AM28H 0xFFC02BE4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */ |
| #define CAN_AM29L 0xFFC02BE8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */ |
| #define CAN_AM29H 0xFFC02BEC /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */ |
| #define CAN_AM30L 0xFFC02BF0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */ |
| #define CAN_AM30H 0xFFC02BF4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */ |
| #define CAN_AM31L 0xFFC02BF8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */ |
| #define CAN_AM31H 0xFFC02BFC /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */ |
| #define CAN_MB00_DATA0 0xFFC02C00 /* CAN Controller 0 Mailbox 0 Data 0 Register */ |
| #define CAN_MB00_DATA1 0xFFC02C04 /* CAN Controller 0 Mailbox 0 Data 1 Register */ |
| #define CAN_MB00_DATA2 0xFFC02C08 /* CAN Controller 0 Mailbox 0 Data 2 Register */ |
| #define CAN_MB00_DATA3 0xFFC02C0C /* CAN Controller 0 Mailbox 0 Data 3 Register */ |
| #define CAN_MB00_LENGTH 0xFFC02C10 /* CAN Controller 0 Mailbox 0 Length Register */ |
| #define CAN_MB00_TIMESTAMP 0xFFC02C14 /* CAN Controller 0 Mailbox 0 Timestamp Register */ |
| #define CAN_MB00_ID0 0xFFC02C18 /* CAN Controller 0 Mailbox 0 ID0 Register */ |
| #define CAN_MB00_ID1 0xFFC02C1C /* CAN Controller 0 Mailbox 0 ID1 Register */ |
| #define CAN_MB01_DATA0 0xFFC02C20 /* CAN Controller 0 Mailbox 1 Data 0 Register */ |
| #define CAN_MB01_DATA1 0xFFC02C24 /* CAN Controller 0 Mailbox 1 Data 1 Register */ |
| #define CAN_MB01_DATA2 0xFFC02C28 /* CAN Controller 0 Mailbox 1 Data 2 Register */ |
| #define CAN_MB01_DATA3 0xFFC02C2C /* CAN Controller 0 Mailbox 1 Data 3 Register */ |
| #define CAN_MB01_LENGTH 0xFFC02C30 /* CAN Controller 0 Mailbox 1 Length Register */ |
| #define CAN_MB01_TIMESTAMP 0xFFC02C34 /* CAN Controller 0 Mailbox 1 Timestamp Register */ |
| #define CAN_MB01_ID0 0xFFC02C38 /* CAN Controller 0 Mailbox 1 ID0 Register */ |
| #define CAN_MB01_ID1 0xFFC02C3C /* CAN Controller 0 Mailbox 1 ID1 Register */ |
| #define CAN_MB02_DATA0 0xFFC02C40 /* CAN Controller 0 Mailbox 2 Data 0 Register */ |
| #define CAN_MB02_DATA1 0xFFC02C44 /* CAN Controller 0 Mailbox 2 Data 1 Register */ |
| #define CAN_MB02_DATA2 0xFFC02C48 /* CAN Controller 0 Mailbox 2 Data 2 Register */ |
| #define CAN_MB02_DATA3 0xFFC02C4C /* CAN Controller 0 Mailbox 2 Data 3 Register */ |
| #define CAN_MB02_LENGTH 0xFFC02C50 /* CAN Controller 0 Mailbox 2 Length Register */ |
| #define CAN_MB02_TIMESTAMP 0xFFC02C54 /* CAN Controller 0 Mailbox 2 Timestamp Register */ |
| #define CAN_MB02_ID0 0xFFC02C58 /* CAN Controller 0 Mailbox 2 ID0 Register */ |
| #define CAN_MB02_ID1 0xFFC02C5C /* CAN Controller 0 Mailbox 2 ID1 Register */ |
| #define CAN_MB03_DATA0 0xFFC02C60 /* CAN Controller 0 Mailbox 3 Data 0 Register */ |
| #define CAN_MB03_DATA1 0xFFC02C64 /* CAN Controller 0 Mailbox 3 Data 1 Register */ |
| #define CAN_MB03_DATA2 0xFFC02C68 /* CAN Controller 0 Mailbox 3 Data 2 Register */ |
| #define CAN_MB03_DATA3 0xFFC02C6C /* CAN Controller 0 Mailbox 3 Data 3 Register */ |
| #define CAN_MB03_LENGTH 0xFFC02C70 /* CAN Controller 0 Mailbox 3 Length Register */ |
| #define CAN_MB03_TIMESTAMP 0xFFC02C74 /* CAN Controller 0 Mailbox 3 Timestamp Register */ |
| #define CAN_MB03_ID0 0xFFC02C78 /* CAN Controller 0 Mailbox 3 ID0 Register */ |
| #define CAN_MB03_ID1 0xFFC02C7C /* CAN Controller 0 Mailbox 3 ID1 Register */ |
| #define CAN_MB04_DATA0 0xFFC02C80 /* CAN Controller 0 Mailbox 4 Data 0 Register */ |
| #define CAN_MB04_DATA1 0xFFC02C84 /* CAN Controller 0 Mailbox 4 Data 1 Register */ |
| #define CAN_MB04_DATA2 0xFFC02C88 /* CAN Controller 0 Mailbox 4 Data 2 Register */ |
| #define CAN_MB04_DATA3 0xFFC02C8C /* CAN Controller 0 Mailbox 4 Data 3 Register */ |
| #define CAN_MB04_LENGTH 0xFFC02C90 /* CAN Controller 0 Mailbox 4 Length Register */ |
| #define CAN_MB04_TIMESTAMP 0xFFC02C94 /* CAN Controller 0 Mailbox 4 Timestamp Register */ |
| #define CAN_MB04_ID0 0xFFC02C98 /* CAN Controller 0 Mailbox 4 ID0 Register */ |
| #define CAN_MB04_ID1 0xFFC02C9C /* CAN Controller 0 Mailbox 4 ID1 Register */ |
| #define CAN_MB05_DATA0 0xFFC02CA0 /* CAN Controller 0 Mailbox 5 Data 0 Register */ |
| #define CAN_MB05_DATA1 0xFFC02CA4 /* CAN Controller 0 Mailbox 5 Data 1 Register */ |
| #define CAN_MB05_DATA2 0xFFC02CA8 /* CAN Controller 0 Mailbox 5 Data 2 Register */ |
| #define CAN_MB05_DATA3 0xFFC02CAC /* CAN Controller 0 Mailbox 5 Data 3 Register */ |
| #define CAN_MB05_LENGTH 0xFFC02CB0 /* CAN Controller 0 Mailbox 5 Length Register */ |
| #define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* CAN Controller 0 Mailbox 5 Timestamp Register */ |
| #define CAN_MB05_ID0 0xFFC02CB8 /* CAN Controller 0 Mailbox 5 ID0 Register */ |
| #define CAN_MB05_ID1 0xFFC02CBC /* CAN Controller 0 Mailbox 5 ID1 Register */ |
| #define CAN_MB06_DATA0 0xFFC02CC0 /* CAN Controller 0 Mailbox 6 Data 0 Register */ |
| #define CAN_MB06_DATA1 0xFFC02CC4 /* CAN Controller 0 Mailbox 6 Data 1 Register */ |
| #define CAN_MB06_DATA2 0xFFC02CC8 /* CAN Controller 0 Mailbox 6 Data 2 Register */ |
| #define CAN_MB06_DATA3 0xFFC02CCC /* CAN Controller 0 Mailbox 6 Data 3 Register */ |
| #define CAN_MB06_LENGTH 0xFFC02CD0 /* CAN Controller 0 Mailbox 6 Length Register */ |
| #define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* CAN Controller 0 Mailbox 6 Timestamp Register */ |
| #define CAN_MB06_ID0 0xFFC02CD8 /* CAN Controller 0 Mailbox 6 ID0 Register */ |
| #define CAN_MB06_ID1 0xFFC02CDC /* CAN Controller 0 Mailbox 6 ID1 Register */ |
| #define CAN_MB07_DATA0 0xFFC02CE0 /* CAN Controller 0 Mailbox 7 Data 0 Register */ |
| #define CAN_MB07_DATA1 0xFFC02CE4 /* CAN Controller 0 Mailbox 7 Data 1 Register */ |
| #define CAN_MB07_DATA2 0xFFC02CE8 /* CAN Controller 0 Mailbox 7 Data 2 Register */ |
| #define CAN_MB07_DATA3 0xFFC02CEC /* CAN Controller 0 Mailbox 7 Data 3 Register */ |
| #define CAN_MB07_LENGTH 0xFFC02CF0 /* CAN Controller 0 Mailbox 7 Length Register */ |
| #define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* CAN Controller 0 Mailbox 7 Timestamp Register */ |
| #define CAN_MB07_ID0 0xFFC02CF8 /* CAN Controller 0 Mailbox 7 ID0 Register */ |
| #define CAN_MB07_ID1 0xFFC02CFC /* CAN Controller 0 Mailbox 7 ID1 Register */ |
| #define CAN_MB08_DATA0 0xFFC02D00 /* CAN Controller 0 Mailbox 8 Data 0 Register */ |
| #define CAN_MB08_DATA1 0xFFC02D04 /* CAN Controller 0 Mailbox 8 Data 1 Register */ |
| #define CAN_MB08_DATA2 0xFFC02D08 /* CAN Controller 0 Mailbox 8 Data 2 Register */ |
| #define CAN_MB08_DATA3 0xFFC02D0C /* CAN Controller 0 Mailbox 8 Data 3 Register */ |
| #define CAN_MB08_LENGTH 0xFFC02D10 /* CAN Controller 0 Mailbox 8 Length Register */ |
| #define CAN_MB08_TIMESTAMP 0xFFC02D14 /* CAN Controller 0 Mailbox 8 Timestamp Register */ |
| #define CAN_MB08_ID0 0xFFC02D18 /* CAN Controller 0 Mailbox 8 ID0 Register */ |
| #define CAN_MB08_ID1 0xFFC02D1C /* CAN Controller 0 Mailbox 8 ID1 Register */ |
| #define CAN_MB09_DATA0 0xFFC02D20 /* CAN Controller 0 Mailbox 9 Data 0 Register */ |
| #define CAN_MB09_DATA1 0xFFC02D24 /* CAN Controller 0 Mailbox 9 Data 1 Register */ |
| #define CAN_MB09_DATA2 0xFFC02D28 /* CAN Controller 0 Mailbox 9 Data 2 Register */ |
| #define CAN_MB09_DATA3 0xFFC02D2C /* CAN Controller 0 Mailbox 9 Data 3 Register */ |
| #define CAN_MB09_LENGTH 0xFFC02D30 /* CAN Controller 0 Mailbox 9 Length Register */ |
| #define CAN_MB09_TIMESTAMP 0xFFC02D34 /* CAN Controller 0 Mailbox 9 Timestamp Register */ |
| #define CAN_MB09_ID0 0xFFC02D38 /* CAN Controller 0 Mailbox 9 ID0 Register */ |
| #define CAN_MB09_ID1 0xFFC02D3C /* CAN Controller 0 Mailbox 9 ID1 Register */ |
| #define CAN_MB10_DATA0 0xFFC02D40 /* CAN Controller 0 Mailbox 10 Data 0 Register */ |
| #define CAN_MB10_DATA1 0xFFC02D44 /* CAN Controller 0 Mailbox 10 Data 1 Register */ |
| #define CAN_MB10_DATA2 0xFFC02D48 /* CAN Controller 0 Mailbox 10 Data 2 Register */ |
| #define CAN_MB10_DATA3 0xFFC02D4C /* CAN Controller 0 Mailbox 10 Data 3 Register */ |
| #define CAN_MB10_LENGTH 0xFFC02D50 /* CAN Controller 0 Mailbox 10 Length Register */ |
| #define CAN_MB10_TIMESTAMP 0xFFC02D54 /* CAN Controller 0 Mailbox 10 Timestamp Register */ |
| #define CAN_MB10_ID0 0xFFC02D58 /* CAN Controller 0 Mailbox 10 ID0 Register */ |
| #define CAN_MB10_ID1 0xFFC02D5C /* CAN Controller 0 Mailbox 10 ID1 Register */ |
| #define CAN_MB11_DATA0 0xFFC02D60 /* CAN Controller 0 Mailbox 11 Data 0 Register */ |
| #define CAN_MB11_DATA1 0xFFC02D64 /* CAN Controller 0 Mailbox 11 Data 1 Register */ |
| #define CAN_MB11_DATA2 0xFFC02D68 /* CAN Controller 0 Mailbox 11 Data 2 Register */ |
| #define CAN_MB11_DATA3 0xFFC02D6C /* CAN Controller 0 Mailbox 11 Data 3 Register */ |
| #define CAN_MB11_LENGTH 0xFFC02D70 /* CAN Controller 0 Mailbox 11 Length Register */ |
| #define CAN_MB11_TIMESTAMP 0xFFC02D74 /* CAN Controller 0 Mailbox 11 Timestamp Register */ |
| #define CAN_MB11_ID0 0xFFC02D78 /* CAN Controller 0 Mailbox 11 ID0 Register */ |
| #define CAN_MB11_ID1 0xFFC02D7C /* CAN Controller 0 Mailbox 11 ID1 Register */ |
| #define CAN_MB12_DATA0 0xFFC02D80 /* CAN Controller 0 Mailbox 12 Data 0 Register */ |
| #define CAN_MB12_DATA1 0xFFC02D84 /* CAN Controller 0 Mailbox 12 Data 1 Register */ |
| #define CAN_MB12_DATA2 0xFFC02D88 /* CAN Controller 0 Mailbox 12 Data 2 Register */ |
| #define CAN_MB12_DATA3 0xFFC02D8C /* CAN Controller 0 Mailbox 12 Data 3 Register */ |
| #define CAN_MB12_LENGTH 0xFFC02D90 /* CAN Controller 0 Mailbox 12 Length Register */ |
| #define CAN_MB12_TIMESTAMP 0xFFC02D94 /* CAN Controller 0 Mailbox 12 Timestamp Register */ |
| #define CAN_MB12_ID0 0xFFC02D98 /* CAN Controller 0 Mailbox 12 ID0 Register */ |
| #define CAN_MB12_ID1 0xFFC02D9C /* CAN Controller 0 Mailbox 12 ID1 Register */ |
| #define CAN_MB13_DATA0 0xFFC02DA0 /* CAN Controller 0 Mailbox 13 Data 0 Register */ |
| #define CAN_MB13_DATA1 0xFFC02DA4 /* CAN Controller 0 Mailbox 13 Data 1 Register */ |
| #define CAN_MB13_DATA2 0xFFC02DA8 /* CAN Controller 0 Mailbox 13 Data 2 Register */ |
| #define CAN_MB13_DATA3 0xFFC02DAC /* CAN Controller 0 Mailbox 13 Data 3 Register */ |
| #define CAN_MB13_LENGTH 0xFFC02DB0 /* CAN Controller 0 Mailbox 13 Length Register */ |
| #define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* CAN Controller 0 Mailbox 13 Timestamp Register */ |
| #define CAN_MB13_ID0 0xFFC02DB8 /* CAN Controller 0 Mailbox 13 ID0 Register */ |
| #define CAN_MB13_ID1 0xFFC02DBC /* CAN Controller 0 Mailbox 13 ID1 Register */ |
| #define CAN_MB14_DATA0 0xFFC02DC0 /* CAN Controller 0 Mailbox 14 Data 0 Register */ |
| #define CAN_MB14_DATA1 0xFFC02DC4 /* CAN Controller 0 Mailbox 14 Data 1 Register */ |
| #define CAN_MB14_DATA2 0xFFC02DC8 /* CAN Controller 0 Mailbox 14 Data 2 Register */ |
| #define CAN_MB14_DATA3 0xFFC02DCC /* CAN Controller 0 Mailbox 14 Data 3 Register */ |
| #define CAN_MB14_LENGTH 0xFFC02DD0 /* CAN Controller 0 Mailbox 14 Length Register */ |
| #define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* CAN Controller 0 Mailbox 14 Timestamp Register */ |
| #define CAN_MB14_ID0 0xFFC02DD8 /* CAN Controller 0 Mailbox 14 ID0 Register */ |
| #define CAN_MB14_ID1 0xFFC02DDC /* CAN Controller 0 Mailbox 14 ID1 Register */ |
| #define CAN_MB15_DATA0 0xFFC02DE0 /* CAN Controller 0 Mailbox 15 Data 0 Register */ |
| #define CAN_MB15_DATA1 0xFFC02DE4 /* CAN Controller 0 Mailbox 15 Data 1 Register */ |
| #define CAN_MB15_DATA2 0xFFC02DE8 /* CAN Controller 0 Mailbox 15 Data 2 Register */ |
| #define CAN_MB15_DATA3 0xFFC02DEC /* CAN Controller 0 Mailbox 15 Data 3 Register */ |
| #define CAN_MB15_LENGTH 0xFFC02DF0 /* CAN Controller 0 Mailbox 15 Length Register */ |
| #define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* CAN Controller 0 Mailbox 15 Timestamp Register */ |
| #define CAN_MB15_ID0 0xFFC02DF8 /* CAN Controller 0 Mailbox 15 ID0 Register */ |
| #define CAN_MB15_ID1 0xFFC02DFC /* CAN Controller 0 Mailbox 15 ID1 Register */ |
| #define CAN_MB16_DATA0 0xFFC02E00 /* CAN Controller 0 Mailbox 16 Data 0 Register */ |
| #define CAN_MB16_DATA1 0xFFC02E04 /* CAN Controller 0 Mailbox 16 Data 1 Register */ |
| #define CAN_MB16_DATA2 0xFFC02E08 /* CAN Controller 0 Mailbox 16 Data 2 Register */ |
| #define CAN_MB16_DATA3 0xFFC02E0C /* CAN Controller 0 Mailbox 16 Data 3 Register */ |
| #define CAN_MB16_LENGTH 0xFFC02E10 /* CAN Controller 0 Mailbox 16 Length Register */ |
| #define CAN_MB16_TIMESTAMP 0xFFC02E14 /* CAN Controller 0 Mailbox 16 Timestamp Register */ |
| #define CAN_MB16_ID0 0xFFC02E18 /* CAN Controller 0 Mailbox 16 ID0 Register */ |
| #define CAN_MB16_ID1 0xFFC02E1C /* CAN Controller 0 Mailbox 16 ID1 Register */ |
| #define CAN_MB17_DATA0 0xFFC02E20 /* CAN Controller 0 Mailbox 17 Data 0 Register */ |
| #define CAN_MB17_DATA1 0xFFC02E24 /* CAN Controller 0 Mailbox 17 Data 1 Register */ |
| #define CAN_MB17_DATA2 0xFFC02E28 /* CAN Controller 0 Mailbox 17 Data 2 Register */ |
| #define CAN_MB17_DATA3 0xFFC02E2C /* CAN Controller 0 Mailbox 17 Data 3 Register */ |
| #define CAN_MB17_LENGTH 0xFFC02E30 /* CAN Controller 0 Mailbox 17 Length Register */ |
| #define CAN_MB17_TIMESTAMP 0xFFC02E34 /* CAN Controller 0 Mailbox 17 Timestamp Register */ |
| #define CAN_MB17_ID0 0xFFC02E38 /* CAN Controller 0 Mailbox 17 ID0 Register */ |
| #define CAN_MB17_ID1 0xFFC02E3C /* CAN Controller 0 Mailbox 17 ID1 Register */ |
| #define CAN_MB18_DATA0 0xFFC02E40 /* CAN Controller 0 Mailbox 18 Data 0 Register */ |
| #define CAN_MB18_DATA1 0xFFC02E44 /* CAN Controller 0 Mailbox 18 Data 1 Register */ |
| #define CAN_MB18_DATA2 0xFFC02E48 /* CAN Controller 0 Mailbox 18 Data 2 Register */ |
| #define CAN_MB18_DATA3 0xFFC02E4C /* CAN Controller 0 Mailbox 18 Data 3 Register */ |
| #define CAN_MB18_LENGTH 0xFFC02E50 /* CAN Controller 0 Mailbox 18 Length Register */ |
| #define CAN_MB18_TIMESTAMP 0xFFC02E54 /* CAN Controller 0 Mailbox 18 Timestamp Register */ |
| #define CAN_MB18_ID0 0xFFC02E58 /* CAN Controller 0 Mailbox 18 ID0 Register */ |
| #define CAN_MB18_ID1 0xFFC02E5C /* CAN Controller 0 Mailbox 18 ID1 Register */ |
| #define CAN_MB19_DATA0 0xFFC02E60 /* CAN Controller 0 Mailbox 19 Data 0 Register */ |
| #define CAN_MB19_DATA1 0xFFC02E64 /* CAN Controller 0 Mailbox 19 Data 1 Register */ |
| #define CAN_MB19_DATA2 0xFFC02E68 /* CAN Controller 0 Mailbox 19 Data 2 Register */ |
| #define CAN_MB19_DATA3 0xFFC02E6C /* CAN Controller 0 Mailbox 19 Data 3 Register */ |
| #define CAN_MB19_LENGTH 0xFFC02E70 /* CAN Controller 0 Mailbox 19 Length Register */ |
| #define CAN_MB19_TIMESTAMP 0xFFC02E74 /* CAN Controller 0 Mailbox 19 Timestamp Register */ |
| #define CAN_MB19_ID0 0xFFC02E78 /* CAN Controller 0 Mailbox 19 ID0 Register */ |
| #define CAN_MB19_ID1 0xFFC02E7C /* CAN Controller 0 Mailbox 19 ID1 Register */ |
| #define CAN_MB20_DATA0 0xFFC02E80 /* CAN Controller 0 Mailbox 20 Data 0 Register */ |
| #define CAN_MB20_DATA1 0xFFC02E84 /* CAN Controller 0 Mailbox 20 Data 1 Register */ |
| #define CAN_MB20_DATA2 0xFFC02E88 /* CAN Controller 0 Mailbox 20 Data 2 Register */ |
| #define CAN_MB20_DATA3 0xFFC02E8C /* CAN Controller 0 Mailbox 20 Data 3 Register */ |
| #define CAN_MB20_LENGTH 0xFFC02E90 /* CAN Controller 0 Mailbox 20 Length Register */ |
| #define CAN_MB20_TIMESTAMP 0xFFC02E94 /* CAN Controller 0 Mailbox 20 Timestamp Register */ |
| #define CAN_MB20_ID0 0xFFC02E98 /* CAN Controller 0 Mailbox 20 ID0 Register */ |
| #define CAN_MB20_ID1 0xFFC02E9C /* CAN Controller 0 Mailbox 20 ID1 Register */ |
| #define CAN_MB21_DATA0 0xFFC02EA0 /* CAN Controller 0 Mailbox 21 Data 0 Register */ |
| #define CAN_MB21_DATA1 0xFFC02EA4 /* CAN Controller 0 Mailbox 21 Data 1 Register */ |
| #define CAN_MB21_DATA2 0xFFC02EA8 /* CAN Controller 0 Mailbox 21 Data 2 Register */ |
| #define CAN_MB21_DATA3 0xFFC02EAC /* CAN Controller 0 Mailbox 21 Data 3 Register */ |
| #define CAN_MB21_LENGTH 0xFFC02EB0 /* CAN Controller 0 Mailbox 21 Length Register */ |
| #define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* CAN Controller 0 Mailbox 21 Timestamp Register */ |
| #define CAN_MB21_ID0 0xFFC02EB8 /* CAN Controller 0 Mailbox 21 ID0 Register */ |
| #define CAN_MB21_ID1 0xFFC02EBC /* CAN Controller 0 Mailbox 21 ID1 Register */ |
| #define CAN_MB22_DATA0 0xFFC02EC0 /* CAN Controller 0 Mailbox 22 Data 0 Register */ |
| #define CAN_MB22_DATA1 0xFFC02EC4 /* CAN Controller 0 Mailbox 22 Data 1 Register */ |
| #define CAN_MB22_DATA2 0xFFC02EC8 /* CAN Controller 0 Mailbox 22 Data 2 Register */ |
| #define CAN_MB22_DATA3 0xFFC02ECC /* CAN Controller 0 Mailbox 22 Data 3 Register */ |
| #define CAN_MB22_LENGTH 0xFFC02ED0 /* CAN Controller 0 Mailbox 22 Length Register */ |
| #define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* CAN Controller 0 Mailbox 22 Timestamp Register */ |
| #define CAN_MB22_ID0 0xFFC02ED8 /* CAN Controller 0 Mailbox 22 ID0 Register */ |
| #define CAN_MB22_ID1 0xFFC02EDC /* CAN Controller 0 Mailbox 22 ID1 Register */ |
| #define CAN_MB23_DATA0 0xFFC02EE0 /* CAN Controller 0 Mailbox 23 Data 0 Register */ |
| #define CAN_MB23_DATA1 0xFFC02EE4 /* CAN Controller 0 Mailbox 23 Data 1 Register */ |
| #define CAN_MB23_DATA2 0xFFC02EE8 /* CAN Controller 0 Mailbox 23 Data 2 Register */ |
| #define CAN_MB23_DATA3 0xFFC02EEC /* CAN Controller 0 Mailbox 23 Data 3 Register */ |
| #define CAN_MB23_LENGTH 0xFFC02EF0 /* CAN Controller 0 Mailbox 23 Length Register */ |
| #define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* CAN Controller 0 Mailbox 23 Timestamp Register */ |
| #define CAN_MB23_ID0 0xFFC02EF8 /* CAN Controller 0 Mailbox 23 ID0 Register */ |
| #define CAN_MB23_ID1 0xFFC02EFC /* CAN Controller 0 Mailbox 23 ID1 Register */ |
| #define CAN_MB24_DATA0 0xFFC02F00 /* CAN Controller 0 Mailbox 24 Data 0 Register */ |
| #define CAN_MB24_DATA1 0xFFC02F04 /* CAN Controller 0 Mailbox 24 Data 1 Register */ |
| #define CAN_MB24_DATA2 0xFFC02F08 /* CAN Controller 0 Mailbox 24 Data 2 Register */ |
| #define CAN_MB24_DATA3 0xFFC02F0C /* CAN Controller 0 Mailbox 24 Data 3 Register */ |
| #define CAN_MB24_LENGTH 0xFFC02F10 /* CAN Controller 0 Mailbox 24 Length Register */ |
| #define CAN_MB24_TIMESTAMP 0xFFC02F14 /* CAN Controller 0 Mailbox 24 Timestamp Register */ |
| #define CAN_MB24_ID0 0xFFC02F18 /* CAN Controller 0 Mailbox 24 ID0 Register */ |
| #define CAN_MB24_ID1 0xFFC02F1C /* CAN Controller 0 Mailbox 24 ID1 Register */ |
| #define CAN_MB25_DATA0 0xFFC02F20 /* CAN Controller 0 Mailbox 25 Data 0 Register */ |
| #define CAN_MB25_DATA1 0xFFC02F24 /* CAN Controller 0 Mailbox 25 Data 1 Register */ |
| #define CAN_MB25_DATA2 0xFFC02F28 /* CAN Controller 0 Mailbox 25 Data 2 Register */ |
| #define CAN_MB25_DATA3 0xFFC02F2C /* CAN Controller 0 Mailbox 25 Data 3 Register */ |
| #define CAN_MB25_LENGTH 0xFFC02F30 /* CAN Controller 0 Mailbox 25 Length Register */ |
| #define CAN_MB25_TIMESTAMP 0xFFC02F34 /* CAN Controller 0 Mailbox 25 Timestamp Register */ |
| #define CAN_MB25_ID0 0xFFC02F38 /* CAN Controller 0 Mailbox 25 ID0 Register */ |
| #define CAN_MB25_ID1 0xFFC02F3C /* CAN Controller 0 Mailbox 25 ID1 Register */ |
| #define CAN_MB26_DATA0 0xFFC02F40 /* CAN Controller 0 Mailbox 26 Data 0 Register */ |
| #define CAN_MB26_DATA1 0xFFC02F44 /* CAN Controller 0 Mailbox 26 Data 1 Register */ |
| #define CAN_MB26_DATA2 0xFFC02F48 /* CAN Controller 0 Mailbox 26 Data 2 Register */ |
| #define CAN_MB26_DATA3 0xFFC02F4C /* CAN Controller 0 Mailbox 26 Data 3 Register */ |
| #define CAN_MB26_LENGTH 0xFFC02F50 /* CAN Controller 0 Mailbox 26 Length Register */ |
| #define CAN_MB26_TIMESTAMP 0xFFC02F54 /* CAN Controller 0 Mailbox 26 Timestamp Register */ |
| #define CAN_MB26_ID0 0xFFC02F58 /* CAN Controller 0 Mailbox 26 ID0 Register */ |
| #define CAN_MB26_ID1 0xFFC02F5C /* CAN Controller 0 Mailbox 26 ID1 Register */ |
| #define CAN_MB27_DATA0 0xFFC02F60 /* CAN Controller 0 Mailbox 27 Data 0 Register */ |
| #define CAN_MB27_DATA1 0xFFC02F64 /* CAN Controller 0 Mailbox 27 Data 1 Register */ |
| #define CAN_MB27_DATA2 0xFFC02F68 /* CAN Controller 0 Mailbox 27 Data 2 Register */ |
| #define CAN_MB27_DATA3 0xFFC02F6C /* CAN Controller 0 Mailbox 27 Data 3 Register */ |
| #define CAN_MB27_LENGTH 0xFFC02F70 /* CAN Controller 0 Mailbox 27 Length Register */ |
| #define CAN_MB27_TIMESTAMP 0xFFC02F74 /* CAN Controller 0 Mailbox 27 Timestamp Register */ |
| #define CAN_MB27_ID0 0xFFC02F78 /* CAN Controller 0 Mailbox 27 ID0 Register */ |
| #define CAN_MB27_ID1 0xFFC02F7C /* CAN Controller 0 Mailbox 27 ID1 Register */ |
| #define CAN_MB28_DATA0 0xFFC02F80 /* CAN Controller 0 Mailbox 28 Data 0 Register */ |
| #define CAN_MB28_DATA1 0xFFC02F84 /* CAN Controller 0 Mailbox 28 Data 1 Register */ |
| #define CAN_MB28_DATA2 0xFFC02F88 /* CAN Controller 0 Mailbox 28 Data 2 Register */ |
| #define CAN_MB28_DATA3 0xFFC02F8C /* CAN Controller 0 Mailbox 28 Data 3 Register */ |
| #define CAN_MB28_LENGTH 0xFFC02F90 /* CAN Controller 0 Mailbox 28 Length Register */ |
| #define CAN_MB28_TIMESTAMP 0xFFC02F94 /* CAN Controller 0 Mailbox 28 Timestamp Register */ |
| #define CAN_MB28_ID0 0xFFC02F98 /* CAN Controller 0 Mailbox 28 ID0 Register */ |
| #define CAN_MB28_ID1 0xFFC02F9C /* CAN Controller 0 Mailbox 28 ID1 Register */ |
| #define CAN_MB29_DATA0 0xFFC02FA0 /* CAN Controller 0 Mailbox 29 Data 0 Register */ |
| #define CAN_MB29_DATA1 0xFFC02FA4 /* CAN Controller 0 Mailbox 29 Data 1 Register */ |
| #define CAN_MB29_DATA2 0xFFC02FA8 /* CAN Controller 0 Mailbox 29 Data 2 Register */ |
| #define CAN_MB29_DATA3 0xFFC02FAC /* CAN Controller 0 Mailbox 29 Data 3 Register */ |
| #define CAN_MB29_LENGTH 0xFFC02FB0 /* CAN Controller 0 Mailbox 29 Length Register */ |
| #define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* CAN Controller 0 Mailbox 29 Timestamp Register */ |
| #define CAN_MB29_ID0 0xFFC02FB8 /* CAN Controller 0 Mailbox 29 ID0 Register */ |
| #define CAN_MB29_ID1 0xFFC02FBC /* CAN Controller 0 Mailbox 29 ID1 Register */ |
| #define CAN_MB30_DATA0 0xFFC02FC0 /* CAN Controller 0 Mailbox 30 Data 0 Register */ |
| #define CAN_MB30_DATA1 0xFFC02FC4 /* CAN Controller 0 Mailbox 30 Data 1 Register */ |
| #define CAN_MB30_DATA2 0xFFC02FC8 /* CAN Controller 0 Mailbox 30 Data 2 Register */ |
| #define CAN_MB30_DATA3 0xFFC02FCC /* CAN Controller 0 Mailbox 30 Data 3 Register */ |
| #define CAN_MB30_LENGTH 0xFFC02FD0 /* CAN Controller 0 Mailbox 30 Length Register */ |
| #define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* CAN Controller 0 Mailbox 30 Timestamp Register */ |
| #define CAN_MB30_ID0 0xFFC02FD8 /* CAN Controller 0 Mailbox 30 ID0 Register */ |
| #define CAN_MB30_ID1 0xFFC02FDC /* CAN Controller 0 Mailbox 30 ID1 Register */ |
| #define CAN_MB31_DATA0 0xFFC02FE0 /* CAN Controller 0 Mailbox 31 Data 0 Register */ |
| #define CAN_MB31_DATA1 0xFFC02FE4 /* CAN Controller 0 Mailbox 31 Data 1 Register */ |
| #define CAN_MB31_DATA2 0xFFC02FE8 /* CAN Controller 0 Mailbox 31 Data 2 Register */ |
| #define CAN_MB31_DATA3 0xFFC02FEC /* CAN Controller 0 Mailbox 31 Data 3 Register */ |
| #define CAN_MB31_LENGTH 0xFFC02FF0 /* CAN Controller 0 Mailbox 31 Length Register */ |
| #define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* CAN Controller 0 Mailbox 31 Timestamp Register */ |
| #define CAN_MB31_ID0 0xFFC02FF8 /* CAN Controller 0 Mailbox 31 ID0 Register */ |
| #define CAN_MB31_ID1 0xFFC02FFC /* CAN Controller 0 Mailbox 31 ID1 Register */ |
| #define PWM1_CTRL 0xFFC03000 /* PWM1 Control Register */ |
| #define PWM1_STAT 0xFFC03004 /* PWM1 Status Register */ |
| #define PWM1_TM 0xFFC03008 /* PWM1 Period Register */ |
| #define PWM1_DT 0xFFC0300C /* PWM1 Dead Time Register */ |
| #define PWM1_GATE 0xFFC03010 /* PWM1 Chopping Control */ |
| #define PWM1_CHA 0xFFC03014 /* PWM1 Channel A Duty Control */ |
| #define PWM1_CHB 0xFFC03018 /* PWM1 Channel B Duty Control */ |
| #define PWM1_CHC 0xFFC0301C /* PWM1 Channel C Duty Control */ |
| #define PWM1_SEG 0xFFC03020 /* PWM1 Crossover and Output Enable */ |
| #define PWM1_SYNCWT 0xFFC03024 /* PWM1 Sync pulse width control */ |
| #define PWM1_CHAL 0xFFC03028 /* PWM1 Channel AL Duty Control (SR mode only) */ |
| #define PWM1_CHBL 0xFFC0302C /* PWM1 Channel BL Duty Control (SR mode only) */ |
| #define PWM1_CHCL 0xFFC03030 /* PWM1 Channel CL Duty Control (SR mode only) */ |
| #define PWM1_LSI 0xFFC03034 /* Low Side Invert (SR mode only) */ |
| #define PWM1_STAT2 0xFFC03038 /* PWM1 Status Register */ |
| #define ACM_CTL 0xFFC03100 /* ACM Control Register */ |
| #define ACM_TC0 0xFFC03104 /* ACM Timing Configuration 0 Register */ |
| #define ACM_TC1 0xFFC03108 /* ACM Timing Configuration 1 Register */ |
| #define ACM_STAT 0xFFC0310C /* ACM Status Register */ |
| #define ACM_ES 0xFFC03110 /* ACM Event Status Register */ |
| #define ACM_IMSK 0xFFC03114 /* ACM Interrupt Mask Register */ |
| #define ACM_MS 0xFFC03118 /* ACM Missed Event Status Register */ |
| #define ACM_EMSK 0xFFC0311C /* ACM Missed Event Interrupt Mask Register */ |
| #define ACM_ER0 0xFFC03120 /* ACM Event 0 Control Register */ |
| #define ACM_ER1 0xFFC03124 /* ACM Event 1 Control Register */ |
| #define ACM_ER2 0xFFC03128 /* ACM Event 2 Control Register */ |
| #define ACM_ER3 0xFFC0312C /* ACM Event 3 Control Register */ |
| #define ACM_ER4 0xFFC03130 /* ACM Event 4 Control Register */ |
| #define ACM_ER5 0xFFC03134 /* ACM Event 5 Control Register */ |
| #define ACM_ER6 0xFFC03138 /* ACM Event 6 Control Register */ |
| #define ACM_ER7 0xFFC0313C /* ACM Event 7 Control Register */ |
| #define ACM_ER8 0xFFC03140 /* ACM Event 8 Control Register */ |
| #define ACM_ER9 0xFFC03144 /* ACM Event 9 Control Register */ |
| #define ACM_ER10 0xFFC03148 /* ACM Event 10 Control Register */ |
| #define ACM_ER11 0xFFC0314C /* ACM Event 11 Control Register */ |
| #define ACM_ER12 0xFFC03150 /* ACM Event 12 Control Register */ |
| #define ACM_ER13 0xFFC03154 /* ACM Event 13 Control Register */ |
| #define ACM_ER14 0xFFC03158 /* ACM Event 14 Control Register */ |
| #define ACM_ER15 0xFFC0315C /* ACM Event 15 Control Register */ |
| #define ACM_ET0 0xFFC03180 /* ACM Event 0 Time Register */ |
| #define ACM_ET1 0xFFC03184 /* ACM Event 1 Time Register */ |
| #define ACM_ET2 0xFFC03188 /* ACM Event 2 Time Register */ |
| #define ACM_ET3 0xFFC0318C /* ACM Event 3 Time Register */ |
| #define ACM_ET4 0xFFC03190 /* ACM Event 4 Time Register */ |
| #define ACM_ET5 0xFFC03194 /* ACM Event 5 Time Register */ |
| #define ACM_ET6 0xFFC03198 /* ACM Event 6 Time Register */ |
| #define ACM_ET7 0xFFC0319C /* ACM Event 7 Time Register */ |
| #define ACM_ET8 0xFFC031A0 /* ACM Event 8 Time Register */ |
| #define ACM_ET9 0xFFC031A4 /* ACM Event 9 Time Register */ |
| #define ACM_ET10 0xFFC031A8 /* ACM Event 10 Time Register */ |
| #define ACM_ET11 0xFFC031AC /* ACM Event 11 Time Register */ |
| #define ACM_ET12 0xFFC031B0 /* ACM Event 12 Time Register */ |
| #define ACM_ET13 0xFFC031B4 /* ACM Event 13 Time Register */ |
| #define ACM_ET14 0xFFC031B8 /* ACM Event 14 Time Register */ |
| #define ACM_ET15 0xFFC031BC /* ACM Event 15 Time Register */ |
| #define ACM_TMR0 0xFFC031C0 /* ACM Timer 0 Registers */ |
| #define ACM_TMR1 0xFFC031C4 /* ACM Timer 1 Registers */ |
| #define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */ |
| #define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */ |
| #define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */ |
| #define PORTF_MUX 0xFFC03210 /* Port F mux control */ |
| #define PORTG_MUX 0xFFC03214 /* Port G mux control */ |
| #define PORTH_MUX 0xFFC03218 /* Port H mux control */ |
| #define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */ |
| #define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */ |
| #define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */ |
| #define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */ |
| #define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */ |
| #define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */ |
| #define NONGPIO_DRIVE 0xFFC03280 /* Non-GPIO Port drive strength control */ |
| #define NONGPIO_HYSTERESIS 0xFFC03288 /* Non-GPIO Port Schmitt trigger control */ |
| #define FLASH_CONTROL 0xFFC0328C /* Stacked flash control register */ |
| #define FLASH_CONTROL_SET 0xFFC03290 /* Stacked flash control set register */ |
| #define FLASH_CONTROL_CLEAR 0xFFC03294 /* Stacked flash control clear register */ |
| #define CNT1_CONFIG 0xFFC03300 /* Counter 1 Configuration Register */ |
| #define CNT1_IMASK 0xFFC03304 /* Counter 1 Interrupt Mask Register */ |
| #define CNT1_STATUS 0xFFC03308 /* Counter 1 Status Register */ |
| #define CNT1_COMMAND 0xFFC0330C /* Counter 1 Command Register */ |
| #define CNT1_DEBOUNCE 0xFFC03310 /* Counter 1 Debounce Register */ |
| #define CNT1_COUNTER 0xFFC03314 /* Counter 1 Counter Register */ |
| #define CNT1_MAX 0xFFC03318 /* Counter 1 Boundry Value Register - max count */ |
| #define CNT1_MIN 0xFFC0331C /* Counter 1 Boundry Value Register - min count */ |
| #define SPI1_CTL 0xFFC03400 /* SPI1 Control */ |
| #define SPI1_FLG 0xFFC03404 /* SPI1 Flag Register */ |
| #define SPI1_STAT 0xFFC03408 /* SPI1 Status Register */ |
| #define SPI1_TDBR 0xFFC0340C /* SPI1 Transmit Data Buffer */ |
| #define SPI1_RDBR 0xFFC03410 /* SPI1 Receive Data Buffer */ |
| #define SPI1_BAUD 0xFFC03414 /* SPI1 Baud Rate */ |
| #define SPI1_SHADOW 0xFFC03418 /* SPI1_RDBR Shadow Register */ |
| #define CNT0_CONFIG 0xFFC03500 /* Configuration/Control Register */ |
| #define CNT0_IMASK 0xFFC03504 /* Interrupt Mask Register */ |
| #define CNT0_STATUS 0xFFC03508 /* Status Register */ |
| #define CNT0_COMMAND 0xFFC0350C /* Command Register */ |
| #define CNT0_DEBOUNCE 0xFFC03510 /* Debounce Prescaler Register */ |
| #define CNT0_COUNTER 0xFFC03514 /* Counter Register */ |
| #define CNT0_MAX 0xFFC03518 /* Maximal Count Boundary Value Register */ |
| #define CNT0_MIN 0xFFC0351C /* Minimal Count Boundary Value Register */ |
| #define PWM0_CTRL 0xFFC03700 /* PWM Control Register */ |
| #define PWM0_STAT 0xFFC03704 /* PWM Status Register */ |
| #define PWM0_TM 0xFFC03708 /* PWM Period Register */ |
| #define PWM0_DT 0xFFC0370C /* PWM Dead Time Register */ |
| #define PWM0_GATE 0xFFC03710 /* PWM Chopping Control */ |
| #define PWM0_CHA 0xFFC03714 /* PWM Channel A Duty Control */ |
| #define PWM0_CHB 0xFFC03718 /* PWM Channel B Duty Control */ |
| #define PWM0_CHC 0xFFC0371C /* PWM Channel C Duty Control */ |
| #define PWM0_SEG 0xFFC03720 /* PWM Crossover and Output Enable */ |
| #define PWM0_SYNCWT 0xFFC03724 /* PWM Sync pulse width control */ |
| #define PWM0_CHAL 0xFFC03728 /* PWM Channel AL Duty Control (SR mode only) */ |
| #define PWM0_CHBL 0xFFC0372C /* PWM Channel BL Duty Control (SR mode only) */ |
| #define PWM0_CHCL 0xFFC03730 /* PWM Channel CL Duty Control (SR mode only) */ |
| #define PWM0_LSI 0xFFC03734 /* Low Side Invert (SR mode only) */ |
| #define PWM0_STAT2 0xFFC03738 /* PWM Status Register */ |
| #define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */ |
| #define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */ |
| #define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */ |
| #define RSI_COMMAND 0xFFC0380C /* RSI Command Register */ |
| #define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */ |
| #define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */ |
| #define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */ |
| #define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */ |
| #define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */ |
| #define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */ |
| #define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */ |
| #define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */ |
| #define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */ |
| #define RSI_STATUS 0xFFC03834 /* RSI Status Register */ |
| #define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */ |
| #define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */ |
| #define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */ |
| #define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */ |
| #define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */ |
| #define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */ |
| #define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */ |
| #define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */ |
| #define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */ |
| #define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */ |
| #define RSI_PID0 0xFFC038D0 /* RSI Peripheral ID Register 0 */ |
| #define RSI_PID1 0xFFC038D4 /* RSI Peripheral ID Register 1 */ |
| #define RSI_PID2 0xFFC038D8 /* RSI Peripheral ID Register 2 */ |
| #define RSI_PID3 0xFFC038DC /* RSI Peripheral ID Register 3 */ |
| #define DMA_TC_CNT 0xFFC00B0C |
| #define DMA_TC_PER 0xFFC00B10 |
| |
| #define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ |
| #define L1_DATA_A_SRAM_SIZE 0x8000 |
| #define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) |
| #define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ |
| #define L1_INST_SRAM_SIZE 0x8000 |
| #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) |
| |
| #endif /* __BFIN_DEF_ADSP_BF504_proc__ */ |
