driver: dwmmc: Add the clock divider code for exynos dwmmc
The exynos dwmmc Ip has 2 stage divider. The first divider
Register is in the vendor specific region of the dwmmc core
(CLK_SEL), and second is part of the dwmmc generic registers
(CLK_DIV).
The goal of this patch is to maintain a 100MHz clock output
before dividing it further by using the CLK_DIV.
Depending on the card enumeration, it can be further divided
by writing a correct divider in the dwmmc CLK_DIV register.
Signed-off-by: Girish K S <ks.giri@samsung.com>
1 file changed
