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Stefan Roese36d830c2007-02-20 10:35:42 +01001/*
Stefan Roesea47a12b2010-04-15 16:07:28 +02002 * arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c
Stefan Roese36d830c2007-02-20 10:35:42 +01003 * This SPD SDRAM detection code supports IBM/AMCC PPC44x cpu with a
4 * SDRAM controller. Those are all current 405 PPC's.
5 *
6 * (C) Copyright 2001
7 * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
8 *
9 * Based on code by:
10 *
11 * Kenneth Johansson ,Ericsson AB.
12 * kenneth.johansson@etx.ericsson.se
13 *
14 * hacked up by bill hunter. fixed so we could run before
15 * serial_init and console_init. previous version avoided this by
16 * running out of cache memory during serial/console init, then running
17 * this code later.
18 *
19 * (C) Copyright 2002
20 * Jun Gu, Artesyn Technology, jung@artesyncp.com
21 * Support for AMCC 440 based on OpenBIOS draminit.c from IBM.
22 *
23 * (C) Copyright 2005
24 * Stefan Roese, DENX Software Engineering, sr@denx.de.
25 *
26 * See file CREDITS for list of people who contributed to this
27 * project.
28 *
29 * This program is free software; you can redistribute it and/or
30 * modify it under the terms of the GNU General Public License as
31 * published by the Free Software Foundation; either version 2 of
32 * the License, or (at your option) any later version.
33 *
34 * This program is distributed in the hope that it will be useful,
35 * but WITHOUT ANY WARRANTY; without even the implied warranty of
36 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
37 * GNU General Public License for more details.
38 *
39 * You should have received a copy of the GNU General Public License
40 * along with this program; if not, write to the Free Software
41 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
42 * MA 02111-1307 USA
43 */
44
45#include <common.h>
46#include <asm/processor.h>
47#include <i2c.h>
Stefan Roeseb36df562010-09-09 19:18:00 +020048#include <asm/ppc4xx.h>
Stefan Roese36d830c2007-02-20 10:35:42 +010049
50#if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_440)
51
52/*
53 * Set default values
54 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055#ifndef CONFIG_SYS_I2C_SPEED
56#define CONFIG_SYS_I2C_SPEED 50000
Stefan Roese36d830c2007-02-20 10:35:42 +010057#endif
58
Stefan Roese36d830c2007-02-20 10:35:42 +010059#define ONE_BILLION 1000000000
60
61#define SDRAM0_CFG_DCE 0x80000000
62#define SDRAM0_CFG_SRE 0x40000000
63#define SDRAM0_CFG_PME 0x20000000
64#define SDRAM0_CFG_MEMCHK 0x10000000
65#define SDRAM0_CFG_REGEN 0x08000000
66#define SDRAM0_CFG_ECCDD 0x00400000
67#define SDRAM0_CFG_EMDULR 0x00200000
68#define SDRAM0_CFG_DRW_SHIFT (31-6)
69#define SDRAM0_CFG_BRPF_SHIFT (31-8)
70
71#define SDRAM0_TR_CASL_SHIFT (31-8)
72#define SDRAM0_TR_PTA_SHIFT (31-13)
73#define SDRAM0_TR_CTP_SHIFT (31-15)
74#define SDRAM0_TR_LDF_SHIFT (31-17)
75#define SDRAM0_TR_RFTA_SHIFT (31-29)
76#define SDRAM0_TR_RCD_SHIFT (31-31)
77
78#define SDRAM0_RTR_SHIFT (31-15)
79#define SDRAM0_ECCCFG_SHIFT (31-11)
80
81/* SDRAM0_CFG enable macro */
82#define SDRAM0_CFG_BRPF(x) ( ( x & 0x3)<< SDRAM0_CFG_BRPF_SHIFT )
83
84#define SDRAM0_BXCR_SZ_MASK 0x000e0000
85#define SDRAM0_BXCR_AM_MASK 0x0000e000
86
87#define SDRAM0_BXCR_SZ_SHIFT (31-14)
88#define SDRAM0_BXCR_AM_SHIFT (31-18)
89
90#define SDRAM0_BXCR_SZ(x) ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) )
91#define SDRAM0_BXCR_AM(x) ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) )
92
93#ifdef CONFIG_SPDDRAM_SILENT
94# define SPD_ERR(x) do { return 0; } while (0)
95#else
96# define SPD_ERR(x) do { printf(x); return(0); } while (0)
97#endif
98
99#define sdram_HZ_to_ns(hertz) (1000000000/(hertz))
100
101/* function prototypes */
102int spd_read(uint addr);
103
104
105/*
106 * This function is reading data from the DIMM module EEPROM over the SPD bus
107 * and uses that to program the sdram controller.
108 *
109 * This works on boards that has the same schematics that the AMCC walnut has.
110 *
111 * Input: null for default I2C spd functions or a pointer to a custom function
112 * returning spd_data.
113 */
114
115long int spd_sdram(int(read_spd)(uint addr))
116{
117 int tmp,row,col;
118 int total_size,bank_size,bank_code;
Stefan Roese36d830c2007-02-20 10:35:42 +0100119 int mode;
120 int bank_cnt;
121
122 int sdram0_pmit=0x07c00000;
Stefan Roese4a127262011-11-15 08:02:37 +0000123 int sdram0_b0cr;
124 int sdram0_b1cr = 0;
Stefan Roese36d830c2007-02-20 10:35:42 +0100125#ifndef CONFIG_405EP /* not on PPC405EP */
Stefan Roese4a127262011-11-15 08:02:37 +0000126 int sdram0_b2cr = 0;
127 int sdram0_b3cr = 0;
Wolfgang Denkd0ff51b2008-07-14 15:19:07 +0200128 int sdram0_besr0 = -1;
129 int sdram0_besr1 = -1;
130 int sdram0_eccesr = -1;
Stefan Roese36d830c2007-02-20 10:35:42 +0100131 int sdram0_ecccfg;
Stefan Roese4a127262011-11-15 08:02:37 +0000132 int ecc_on;
133#endif
Stefan Roese36d830c2007-02-20 10:35:42 +0100134
135 int sdram0_rtr=0;
136 int sdram0_tr=0;
137
Stefan Roese36d830c2007-02-20 10:35:42 +0100138 int sdram0_cfg=0;
139
140 int t_rp;
141 int t_rcd;
142 int t_ras;
143 int t_rc;
144 int min_cas;
145
Stefan Roese087dfdb2007-10-21 08:12:41 +0200146 PPC4xx_SYS_INFO sys_info;
Stefan Roese36d830c2007-02-20 10:35:42 +0100147 unsigned long bus_period_x_10;
148
149 /*
150 * get the board info
151 */
152 get_sys_info(&sys_info);
153 bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
154
155 if (read_spd == 0){
156 read_spd=spd_read;
157 /*
158 * Make sure I2C controller is initialized
159 * before continuing.
160 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
Stefan Roese36d830c2007-02-20 10:35:42 +0100162 }
163
164 /* Make shure we are using SDRAM */
165 if (read_spd(2) != 0x04) {
166 SPD_ERR("SDRAM - non SDRAM memory module found\n");
167 }
168
169 /* ------------------------------------------------------------------
170 * configure memory timing register
171 *
172 * data from DIMM:
173 * 27 IN Row Precharge Time ( t RP)
174 * 29 MIN RAS to CAS Delay ( t RCD)
175 * 127 Component and Clock Detail ,clk0-clk3, junction temp, CAS
176 * -------------------------------------------------------------------*/
177
178 /*
179 * first figure out which cas latency mode to use
180 * use the min supported mode
181 */
182
183 tmp = read_spd(127) & 0x6;
184 if (tmp == 0x02) { /* only cas = 2 supported */
185 min_cas = 2;
186/* t_ck = read_spd(9); */
187/* t_ac = read_spd(10); */
188 } else if (tmp == 0x04) { /* only cas = 3 supported */
189 min_cas = 3;
190/* t_ck = read_spd(9); */
191/* t_ac = read_spd(10); */
192 } else if (tmp == 0x06) { /* 2,3 supported, so use 2 */
193 min_cas = 2;
194/* t_ck = read_spd(23); */
195/* t_ac = read_spd(24); */
196 } else {
197 SPD_ERR("SDRAM - unsupported CAS latency \n");
198 }
199
200 /* get some timing values, t_rp,t_rcd,t_ras,t_rc
201 */
202 t_rp = read_spd(27);
203 t_rcd = read_spd(29);
204 t_ras = read_spd(30);
205 t_rc = t_ras + t_rp;
206
207 /* The following timing calcs subtract 1 before deviding.
208 * this has effect of using ceiling instead of floor rounding,
209 * and also subtracting 1 to convert number to reg value
210 */
211 /* set up CASL */
212 sdram0_tr = (min_cas - 1) << SDRAM0_TR_CASL_SHIFT;
213 /* set up PTA */
214 sdram0_tr |= ((((t_rp - 1) * 10)/bus_period_x_10) & 0x3) << SDRAM0_TR_PTA_SHIFT;
215 /* set up CTP */
216 tmp = (((t_rc - t_rcd - t_rp -1) * 10) / bus_period_x_10) & 0x3;
217 if (tmp < 1)
218 tmp = 1;
219 sdram0_tr |= tmp << SDRAM0_TR_CTP_SHIFT;
220 /* set LDF = 2 cycles, reg value = 1 */
221 sdram0_tr |= 1 << SDRAM0_TR_LDF_SHIFT;
222 /* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */
223 tmp = (((t_rc - 1) * 10) / bus_period_x_10) - 3;
224 if (tmp < 0)
225 tmp = 0;
226 if (tmp > 6)
227 tmp = 6;
228 sdram0_tr |= tmp << SDRAM0_TR_RFTA_SHIFT;
229 /* set RCD = t_rcd/bus_period*/
230 sdram0_tr |= ((((t_rcd - 1) * 10) / bus_period_x_10) &0x3) << SDRAM0_TR_RCD_SHIFT ;
231
232
233 /*------------------------------------------------------------------
234 * configure RTR register
235 * -------------------------------------------------------------------*/
236 row = read_spd(3);
237 col = read_spd(4);
238 tmp = read_spd(12) & 0x7f ; /* refresh type less self refresh bit */
239 switch (tmp) {
240 case 0x00:
241 tmp = 15625;
242 break;
243 case 0x01:
244 tmp = 15625 / 4;
245 break;
246 case 0x02:
247 tmp = 15625 / 2;
248 break;
249 case 0x03:
250 tmp = 15625 * 2;
251 break;
252 case 0x04:
253 tmp = 15625 * 4;
254 break;
255 case 0x05:
256 tmp = 15625 * 8;
257 break;
258 default:
259 SPD_ERR("SDRAM - Bad refresh period \n");
260 }
261 /* convert from nsec to bus cycles */
262 tmp = (tmp * 10) / bus_period_x_10;
263 sdram0_rtr = (tmp & 0x3ff8) << SDRAM0_RTR_SHIFT;
264
265 /*------------------------------------------------------------------
266 * determine the number of banks used
267 * -------------------------------------------------------------------*/
268 /* byte 7:6 is module data width */
269 if (read_spd(7) != 0)
270 SPD_ERR("SDRAM - unsupported module width\n");
271 tmp = read_spd(6);
272 if (tmp < 32)
273 SPD_ERR("SDRAM - unsupported module width\n");
274 else if (tmp < 64)
275 bank_cnt = 1; /* one bank per sdram side */
276 else if (tmp < 73)
277 bank_cnt = 2; /* need two banks per side */
278 else if (tmp < 161)
279 bank_cnt = 4; /* need four banks per side */
280 else
281 SPD_ERR("SDRAM - unsupported module width\n");
282
283 /* byte 5 is the module row count (refered to as dimm "sides") */
284 tmp = read_spd(5);
285 if (tmp == 1)
286 ;
287 else if (tmp==2)
288 bank_cnt *= 2;
289 else if (tmp==4)
290 bank_cnt *= 4;
291 else
292 bank_cnt = 8; /* 8 is an error code */
293
294 if (bank_cnt > 4) /* we only have 4 banks to work with */
295 SPD_ERR("SDRAM - unsupported module rows for this width\n");
296
Stefan Roese4a127262011-11-15 08:02:37 +0000297#ifndef CONFIG_405EP /* not on PPC405EP */
Stefan Roese36d830c2007-02-20 10:35:42 +0100298 /* now check for ECC ability of module. We only support ECC
299 * on 32 bit wide devices with 8 bit ECC.
300 */
301 if ((read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8)) {
302 sdram0_ecccfg = 0xf << SDRAM0_ECCCFG_SHIFT;
303 ecc_on = 1;
304 } else {
305 sdram0_ecccfg = 0;
306 ecc_on = 0;
307 }
Stefan Roese4a127262011-11-15 08:02:37 +0000308#endif
Stefan Roese36d830c2007-02-20 10:35:42 +0100309
310 /*------------------------------------------------------------------
311 * calculate total size
312 * -------------------------------------------------------------------*/
313 /* calculate total size and do sanity check */
314 tmp = read_spd(31);
315 total_size = 1 << 22; /* total_size = 4MB */
316 /* now multiply 4M by the smallest device row density */
317 /* note that we don't support asymetric rows */
318 while (((tmp & 0x0001) == 0) && (tmp != 0)) {
319 total_size = total_size << 1;
320 tmp = tmp >> 1;
321 }
322 total_size *= read_spd(5); /* mult by module rows (dimm sides) */
323
324 /*------------------------------------------------------------------
325 * map rows * cols * banks to a mode
326 * -------------------------------------------------------------------*/
327
328 switch (row) {
329 case 11:
330 switch (col) {
331 case 8:
332 mode=4; /* mode 5 */
333 break;
334 case 9:
335 case 10:
336 mode=0; /* mode 1 */
337 break;
338 default:
339 SPD_ERR("SDRAM - unsupported mode\n");
340 }
341 break;
342 case 12:
343 switch (col) {
344 case 8:
345 mode=3; /* mode 4 */
346 break;
347 case 9:
348 case 10:
349 mode=1; /* mode 2 */
350 break;
351 default:
352 SPD_ERR("SDRAM - unsupported mode\n");
353 }
354 break;
355 case 13:
356 switch (col) {
357 case 8:
358 mode=5; /* mode 6 */
359 break;
360 case 9:
361 case 10:
362 if (read_spd(17) == 2)
363 mode = 6; /* mode 7 */
364 else
365 mode = 2; /* mode 3 */
366 break;
367 case 11:
368 mode = 2; /* mode 3 */
369 break;
370 default:
371 SPD_ERR("SDRAM - unsupported mode\n");
372 }
373 break;
374 default:
375 SPD_ERR("SDRAM - unsupported mode\n");
376 }
377
378 /*------------------------------------------------------------------
379 * using the calculated values, compute the bank
380 * config register values.
381 * -------------------------------------------------------------------*/
Stefan Roese36d830c2007-02-20 10:35:42 +0100382
383 /* compute the size of each bank */
384 bank_size = total_size / bank_cnt;
385 /* convert bank size to bank size code for ppc4xx
386 by takeing log2(bank_size) - 22 */
387 tmp = bank_size; /* start with tmp = bank_size */
388 bank_code = 0; /* and bank_code = 0 */
389 while (tmp > 1) { /* this takes log2 of tmp */
390 bank_code++; /* and stores result in bank_code */
391 tmp = tmp >> 1;
392 } /* bank_code is now log2(bank_size) */
393 bank_code -= 22; /* subtract 22 to get the code */
394
395 tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1;
396 sdram0_b0cr = (bank_size * 0) | tmp;
397#ifndef CONFIG_405EP /* not on PPC405EP */
398 if (bank_cnt > 1)
399 sdram0_b2cr = (bank_size * 1) | tmp;
400 if (bank_cnt > 2)
401 sdram0_b1cr = (bank_size * 2) | tmp;
402 if (bank_cnt > 3)
403 sdram0_b3cr = (bank_size * 3) | tmp;
404#else
405 /* PPC405EP chip only supports two SDRAM banks */
406 if (bank_cnt > 1)
407 sdram0_b1cr = (bank_size * 1) | tmp;
408 if (bank_cnt > 2)
409 total_size = 2 * bank_size;
410#endif
411
412 /*
413 * enable sdram controller DCE=1
414 * enable burst read prefetch to 32 bytes BRPF=2
415 * leave other functions off
416 */
417
418 /*------------------------------------------------------------------
419 * now that we've done our calculations, we are ready to
420 * program all the registers.
421 * -------------------------------------------------------------------*/
422
Stefan Roese36d830c2007-02-20 10:35:42 +0100423 /* disable memcontroller so updates work */
Stefan Roeseb306db22009-09-24 14:10:30 +0200424 mtsdram(SDRAM0_CFG, 0);
Stefan Roese36d830c2007-02-20 10:35:42 +0100425
426#ifndef CONFIG_405EP /* not on PPC405EP */
Stefan Roeseb306db22009-09-24 14:10:30 +0200427 mtsdram(SDRAM0_BESR0, sdram0_besr0);
428 mtsdram(SDRAM0_BESR1, sdram0_besr1);
429 mtsdram(SDRAM0_ECCCFG, sdram0_ecccfg);
430 mtsdram(SDRAM0_ECCESR, sdram0_eccesr);
Stefan Roese36d830c2007-02-20 10:35:42 +0100431#endif
Stefan Roeseb306db22009-09-24 14:10:30 +0200432 mtsdram(SDRAM0_RTR, sdram0_rtr);
433 mtsdram(SDRAM0_PMIT, sdram0_pmit);
434 mtsdram(SDRAM0_B0CR, sdram0_b0cr);
435 mtsdram(SDRAM0_B1CR, sdram0_b1cr);
Stefan Roese36d830c2007-02-20 10:35:42 +0100436#ifndef CONFIG_405EP /* not on PPC405EP */
Stefan Roeseb306db22009-09-24 14:10:30 +0200437 mtsdram(SDRAM0_B2CR, sdram0_b2cr);
438 mtsdram(SDRAM0_B3CR, sdram0_b3cr);
Stefan Roese36d830c2007-02-20 10:35:42 +0100439#endif
Stefan Roeseb306db22009-09-24 14:10:30 +0200440 mtsdram(SDRAM0_TR, sdram0_tr);
Stefan Roese36d830c2007-02-20 10:35:42 +0100441
442 /* SDRAM have a power on delay, 500 micro should do */
443 udelay(500);
444 sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR;
Stefan Roese4a127262011-11-15 08:02:37 +0000445#ifndef CONFIG_405EP /* not on PPC405EP */
Stefan Roese36d830c2007-02-20 10:35:42 +0100446 if (ecc_on)
447 sdram0_cfg |= SDRAM0_CFG_MEMCHK;
Stefan Roese4a127262011-11-15 08:02:37 +0000448#endif
Stefan Roeseb306db22009-09-24 14:10:30 +0200449 mtsdram(SDRAM0_CFG, sdram0_cfg);
Stefan Roese36d830c2007-02-20 10:35:42 +0100450
451 return (total_size);
452}
453
454int spd_read(uint addr)
455{
456 uchar data[2];
457
458 if (i2c_read(SPD_EEPROM_ADDRESS, addr, 1, data, 1) == 0)
459 return (int)data[0];
460 else
461 return 0;
462}
463
464#endif /* CONFIG_SPD_EEPROM */