| commit | aef81b62a24c04687ee1abc92ffae7ac02331ae8 | [log] [tgz] |
|---|---|---|
| author | Charles M. Hannum <root@ihack.net> | Mon Feb 24 16:41:34 2014 -0500 |
| committer | Charles M. Hannum <root@ihack.net> | Fri May 09 19:19:10 2014 +0200 |
| tree | a28e68341437a3b7feb6e1c19b4365faeedff26c | |
| parent | fc3a8b5e4ffb29f4b8d57b07b231926b34619cc6 [diff] |
Wire GPIO 43 to control SDIO power. Overload SYS_BOOT5 to decide whether to use the FPC connector or the FPGA for DSI. The only effect here is to jumble the lanes for the FPGA. This also swaps the UART vs. MMC boot order, but we don't care.