commit fc3a8b5e4ffb29f4b8d57b07b231926b34619cc6
author Charles M. Hannum <root@ihack.net> Thu Feb 20 17:48:37 2014 -0500
committer Charles M. Hannum <root@ihack.net> Fri May 09 19:19:10 2014 +0200
tree 4c02adb8d0f32040fbf7e90e47592796780f35db
parent 0f25c8ed611d78204092884992781a1ed19cf9ab

Calculate the clock divider using the correct FCLK.

drivers/mmc/host/omap_hsmmc.c

diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index b151052..9e74ea6 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -124,7 +124,6 @@
 
 #define MMC_AUTOSUSPEND_DELAY	100
 #define MMC_TIMEOUT_MS		20
-#define OMAP_MMC_MASTER_CLOCK	96000000
 #define OMAP_MMC_MIN_CLOCK	400000
 #define OMAP_MMC_MAX_CLOCK	52000000
 #define DRIVER_NAME		"omap_hsmmc"
@@ -615,12 +614,14 @@
 }
 
 /* Calculate divisor for the given clock frequency */
-static u16 calc_divisor(struct mmc_ios *ios)
+static u16 calc_divisor(struct omap_hsmmc_host *host)
 {
+	struct mmc_ios *ios = &host->mmc->ios;
+	unsigned int fclk = clk_get_rate(host->fclk);
 	u16 dsor = 0;
 
 	if (ios->clock) {
-		dsor = DIV_ROUND_UP(OMAP_MMC_MASTER_CLOCK, ios->clock);
+		dsor = DIV_ROUND_UP(fclk, ios->clock);
 		if (dsor > 250)
 			dsor = 250;
 	}
@@ -640,7 +641,7 @@
 
 	regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 	regval = regval & ~(CLKD_MASK | DTO_MASK);
-	regval = regval | (calc_divisor(ios) << 6) | (DTO << 16);
+	regval = regval | (calc_divisor(host) << 6) | (DTO << 16);
 	OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 	OMAP_HSMMC_WRITE(host->base, SYSCTL,
 		OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);