Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 1 | /* |
| 2 | * drivers/mtd/ndfc.c |
| 3 | * |
| 4 | * Overview: |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 5 | * Platform independent driver for NDFC (NanD Flash Controller) |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 6 | * integrated into EP440 cores |
| 7 | * |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 8 | * Ported to an OF platform driver by Sean MacLennan |
| 9 | * |
| 10 | * The NDFC supports multiple chips, but this driver only supports a |
| 11 | * single chip since I do not have access to any boards with |
| 12 | * multiple chips. |
| 13 | * |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 14 | * Author: Thomas Gleixner |
| 15 | * |
| 16 | * Copyright 2006 IBM |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 17 | * Copyright 2008 PIKA Technologies |
| 18 | * Sean MacLennan <smaclennan@pikatech.com> |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 19 | * |
| 20 | * This program is free software; you can redistribute it and/or modify it |
| 21 | * under the terms of the GNU General Public License as published by the |
| 22 | * Free Software Foundation; either version 2 of the License, or (at your |
| 23 | * option) any later version. |
| 24 | * |
| 25 | */ |
| 26 | #include <linux/module.h> |
| 27 | #include <linux/mtd/nand.h> |
| 28 | #include <linux/mtd/nand_ecc.h> |
| 29 | #include <linux/mtd/partitions.h> |
| 30 | #include <linux/mtd/ndfc.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 31 | #include <linux/slab.h> |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 32 | #include <linux/mtd/mtd.h> |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 33 | #include <linux/of_platform.h> |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 34 | #include <asm/io.h> |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 35 | |
Felix Radensky | 410fe2f | 2011-04-26 12:36:46 +0300 | [diff] [blame] | 36 | #define NDFC_MAX_CS 4 |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 37 | |
| 38 | struct ndfc_controller { |
Grant Likely | 2dc1158 | 2010-08-06 09:25:50 -0600 | [diff] [blame] | 39 | struct platform_device *ofdev; |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 40 | void __iomem *ndfcbase; |
| 41 | struct mtd_info mtd; |
| 42 | struct nand_chip chip; |
| 43 | int chip_select; |
| 44 | struct nand_hw_control ndfc_control; |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 45 | struct mtd_partition *parts; |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 46 | }; |
| 47 | |
Felix Radensky | 410fe2f | 2011-04-26 12:36:46 +0300 | [diff] [blame] | 48 | static struct ndfc_controller ndfc_ctrl[NDFC_MAX_CS]; |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 49 | |
| 50 | static void ndfc_select_chip(struct mtd_info *mtd, int chip) |
| 51 | { |
| 52 | uint32_t ccr; |
Felix Radensky | 410fe2f | 2011-04-26 12:36:46 +0300 | [diff] [blame] | 53 | struct nand_chip *nchip = mtd->priv; |
| 54 | struct ndfc_controller *ndfc = nchip->priv; |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 55 | |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 56 | ccr = in_be32(ndfc->ndfcbase + NDFC_CCR); |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 57 | if (chip >= 0) { |
| 58 | ccr &= ~NDFC_CCR_BS_MASK; |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 59 | ccr |= NDFC_CCR_BS(chip + ndfc->chip_select); |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 60 | } else |
| 61 | ccr |= NDFC_CCR_RESET_CE; |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 62 | out_be32(ndfc->ndfcbase + NDFC_CCR, ccr); |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 63 | } |
| 64 | |
Thomas Gleixner | 7abd3ef | 2006-05-23 23:25:53 +0200 | [diff] [blame] | 65 | static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 66 | { |
Felix Radensky | 410fe2f | 2011-04-26 12:36:46 +0300 | [diff] [blame] | 67 | struct nand_chip *chip = mtd->priv; |
| 68 | struct ndfc_controller *ndfc = chip->priv; |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 69 | |
Thomas Gleixner | 7abd3ef | 2006-05-23 23:25:53 +0200 | [diff] [blame] | 70 | if (cmd == NAND_CMD_NONE) |
| 71 | return; |
| 72 | |
| 73 | if (ctrl & NAND_CLE) |
Thomas Gleixner | 1794c13 | 2006-06-22 13:06:43 +0200 | [diff] [blame] | 74 | writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_CMD); |
Thomas Gleixner | 7abd3ef | 2006-05-23 23:25:53 +0200 | [diff] [blame] | 75 | else |
Thomas Gleixner | 1794c13 | 2006-06-22 13:06:43 +0200 | [diff] [blame] | 76 | writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_ALE); |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 77 | } |
| 78 | |
| 79 | static int ndfc_ready(struct mtd_info *mtd) |
| 80 | { |
Felix Radensky | 410fe2f | 2011-04-26 12:36:46 +0300 | [diff] [blame] | 81 | struct nand_chip *chip = mtd->priv; |
| 82 | struct ndfc_controller *ndfc = chip->priv; |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 83 | |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 84 | return in_be32(ndfc->ndfcbase + NDFC_STAT) & NDFC_STAT_IS_READY; |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 85 | } |
| 86 | |
| 87 | static void ndfc_enable_hwecc(struct mtd_info *mtd, int mode) |
| 88 | { |
| 89 | uint32_t ccr; |
Felix Radensky | 410fe2f | 2011-04-26 12:36:46 +0300 | [diff] [blame] | 90 | struct nand_chip *chip = mtd->priv; |
| 91 | struct ndfc_controller *ndfc = chip->priv; |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 92 | |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 93 | ccr = in_be32(ndfc->ndfcbase + NDFC_CCR); |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 94 | ccr |= NDFC_CCR_RESET_ECC; |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 95 | out_be32(ndfc->ndfcbase + NDFC_CCR, ccr); |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 96 | wmb(); |
| 97 | } |
| 98 | |
| 99 | static int ndfc_calculate_ecc(struct mtd_info *mtd, |
| 100 | const u_char *dat, u_char *ecc_code) |
| 101 | { |
Felix Radensky | 410fe2f | 2011-04-26 12:36:46 +0300 | [diff] [blame] | 102 | struct nand_chip *chip = mtd->priv; |
| 103 | struct ndfc_controller *ndfc = chip->priv; |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 104 | uint32_t ecc; |
| 105 | uint8_t *p = (uint8_t *)&ecc; |
| 106 | |
| 107 | wmb(); |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 108 | ecc = in_be32(ndfc->ndfcbase + NDFC_ECC); |
| 109 | /* The NDFC uses Smart Media (SMC) bytes order */ |
Feng Kan | 76c23c3 | 2009-08-25 11:27:20 -0700 | [diff] [blame] | 110 | ecc_code[0] = p[1]; |
| 111 | ecc_code[1] = p[2]; |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 112 | ecc_code[2] = p[3]; |
| 113 | |
| 114 | return 0; |
| 115 | } |
| 116 | |
| 117 | /* |
| 118 | * Speedups for buffer read/write/verify |
| 119 | * |
| 120 | * NDFC allows 32bit read/write of data. So we can speed up the buffer |
| 121 | * functions. No further checking, as nand_base will always read/write |
| 122 | * page aligned. |
| 123 | */ |
| 124 | static void ndfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
| 125 | { |
Felix Radensky | 410fe2f | 2011-04-26 12:36:46 +0300 | [diff] [blame] | 126 | struct nand_chip *chip = mtd->priv; |
| 127 | struct ndfc_controller *ndfc = chip->priv; |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 128 | uint32_t *p = (uint32_t *) buf; |
| 129 | |
| 130 | for(;len > 0; len -= 4) |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 131 | *p++ = in_be32(ndfc->ndfcbase + NDFC_DATA); |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 132 | } |
| 133 | |
| 134 | static void ndfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
| 135 | { |
Felix Radensky | 410fe2f | 2011-04-26 12:36:46 +0300 | [diff] [blame] | 136 | struct nand_chip *chip = mtd->priv; |
| 137 | struct ndfc_controller *ndfc = chip->priv; |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 138 | uint32_t *p = (uint32_t *) buf; |
| 139 | |
| 140 | for(;len > 0; len -= 4) |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 141 | out_be32(ndfc->ndfcbase + NDFC_DATA, *p++); |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 142 | } |
| 143 | |
| 144 | static int ndfc_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
| 145 | { |
Felix Radensky | 410fe2f | 2011-04-26 12:36:46 +0300 | [diff] [blame] | 146 | struct nand_chip *chip = mtd->priv; |
| 147 | struct ndfc_controller *ndfc = chip->priv; |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 148 | uint32_t *p = (uint32_t *) buf; |
| 149 | |
| 150 | for(;len > 0; len -= 4) |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 151 | if (*p++ != in_be32(ndfc->ndfcbase + NDFC_DATA)) |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 152 | return -EFAULT; |
| 153 | return 0; |
| 154 | } |
| 155 | |
| 156 | /* |
| 157 | * Initialize chip structure |
| 158 | */ |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 159 | static int ndfc_chip_init(struct ndfc_controller *ndfc, |
| 160 | struct device_node *node) |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 161 | { |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 162 | #ifdef CONFIG_MTD_CMDLINE_PARTS |
| 163 | static const char *part_types[] = { "cmdlinepart", NULL }; |
| 164 | #else |
| 165 | static const char *part_types[] = { NULL }; |
| 166 | #endif |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 167 | struct device_node *flash_np; |
| 168 | struct nand_chip *chip = &ndfc->chip; |
| 169 | int ret; |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 170 | |
| 171 | chip->IO_ADDR_R = ndfc->ndfcbase + NDFC_DATA; |
| 172 | chip->IO_ADDR_W = ndfc->ndfcbase + NDFC_DATA; |
Thomas Gleixner | 7abd3ef | 2006-05-23 23:25:53 +0200 | [diff] [blame] | 173 | chip->cmd_ctrl = ndfc_hwcontrol; |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 174 | chip->dev_ready = ndfc_ready; |
| 175 | chip->select_chip = ndfc_select_chip; |
| 176 | chip->chip_delay = 50; |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 177 | chip->controller = &ndfc->ndfc_control; |
| 178 | chip->read_buf = ndfc_read_buf; |
| 179 | chip->write_buf = ndfc_write_buf; |
| 180 | chip->verify_buf = ndfc_verify_buf; |
Thomas Gleixner | 6dfc6d2 | 2006-05-23 12:00:46 +0200 | [diff] [blame] | 181 | chip->ecc.correct = nand_correct_data; |
| 182 | chip->ecc.hwctl = ndfc_enable_hwecc; |
| 183 | chip->ecc.calculate = ndfc_calculate_ecc; |
| 184 | chip->ecc.mode = NAND_ECC_HW; |
| 185 | chip->ecc.size = 256; |
| 186 | chip->ecc.bytes = 3; |
Felix Radensky | 410fe2f | 2011-04-26 12:36:46 +0300 | [diff] [blame] | 187 | chip->priv = ndfc; |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 188 | |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 189 | ndfc->mtd.priv = chip; |
| 190 | ndfc->mtd.owner = THIS_MODULE; |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 191 | |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 192 | flash_np = of_get_next_child(node, NULL); |
| 193 | if (!flash_np) |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 194 | return -ENODEV; |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 195 | |
| 196 | ndfc->mtd.name = kasprintf(GFP_KERNEL, "%s.%s", |
Kay Sievers | c36f1e3 | 2009-03-24 16:38:21 -0700 | [diff] [blame] | 197 | dev_name(&ndfc->ofdev->dev), flash_np->name); |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 198 | if (!ndfc->mtd.name) { |
| 199 | ret = -ENOMEM; |
| 200 | goto err; |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 201 | } |
| 202 | |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 203 | ret = nand_scan(&ndfc->mtd, 1); |
| 204 | if (ret) |
| 205 | goto err; |
| 206 | |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 207 | ret = parse_mtd_partitions(&ndfc->mtd, part_types, &ndfc->parts, 0); |
| 208 | if (ret < 0) |
| 209 | goto err; |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 210 | |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 211 | if (ret == 0) { |
| 212 | ret = of_mtd_parse_partitions(&ndfc->ofdev->dev, flash_np, |
| 213 | &ndfc->parts); |
| 214 | if (ret < 0) |
| 215 | goto err; |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 216 | } |
| 217 | |
Jamie Iles | 1f3a7c6 | 2011-05-23 10:23:28 +0100 | [diff] [blame] | 218 | ret = mtd_device_register(&ndfc->mtd, ndfc->parts, ret); |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 219 | |
| 220 | err: |
| 221 | of_node_put(flash_np); |
| 222 | if (ret) |
| 223 | kfree(ndfc->mtd.name); |
| 224 | return ret; |
| 225 | } |
| 226 | |
Grant Likely | 1c48a5c | 2011-02-17 02:43:24 -0700 | [diff] [blame] | 227 | static int __devinit ndfc_probe(struct platform_device *ofdev) |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 228 | { |
Felix Radensky | 410fe2f | 2011-04-26 12:36:46 +0300 | [diff] [blame] | 229 | struct ndfc_controller *ndfc; |
Ian Munsie | 766f271 | 2010-10-01 17:06:08 +1000 | [diff] [blame] | 230 | const __be32 *reg; |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 231 | u32 ccr; |
Felix Radensky | 410fe2f | 2011-04-26 12:36:46 +0300 | [diff] [blame] | 232 | int err, len, cs; |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 233 | |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 234 | /* Read the reg property to get the chip select */ |
Grant Likely | 61c7a08 | 2010-04-13 16:12:29 -0700 | [diff] [blame] | 235 | reg = of_get_property(ofdev->dev.of_node, "reg", &len); |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 236 | if (reg == NULL || len != 12) { |
| 237 | dev_err(&ofdev->dev, "unable read reg property (%d)\n", len); |
| 238 | return -ENOENT; |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 239 | } |
Felix Radensky | 410fe2f | 2011-04-26 12:36:46 +0300 | [diff] [blame] | 240 | |
| 241 | cs = be32_to_cpu(reg[0]); |
| 242 | if (cs >= NDFC_MAX_CS) { |
| 243 | dev_err(&ofdev->dev, "invalid CS number (%d)\n", cs); |
| 244 | return -EINVAL; |
| 245 | } |
| 246 | |
| 247 | ndfc = &ndfc_ctrl[cs]; |
| 248 | ndfc->chip_select = cs; |
| 249 | |
| 250 | spin_lock_init(&ndfc->ndfc_control.lock); |
| 251 | init_waitqueue_head(&ndfc->ndfc_control.wq); |
| 252 | ndfc->ofdev = ofdev; |
| 253 | dev_set_drvdata(&ofdev->dev, ndfc); |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 254 | |
Grant Likely | 61c7a08 | 2010-04-13 16:12:29 -0700 | [diff] [blame] | 255 | ndfc->ndfcbase = of_iomap(ofdev->dev.of_node, 0); |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 256 | if (!ndfc->ndfcbase) { |
| 257 | dev_err(&ofdev->dev, "failed to get memory\n"); |
| 258 | return -EIO; |
| 259 | } |
| 260 | |
| 261 | ccr = NDFC_CCR_BS(ndfc->chip_select); |
| 262 | |
| 263 | /* It is ok if ccr does not exist - just default to 0 */ |
Grant Likely | 61c7a08 | 2010-04-13 16:12:29 -0700 | [diff] [blame] | 264 | reg = of_get_property(ofdev->dev.of_node, "ccr", NULL); |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 265 | if (reg) |
Ian Munsie | 766f271 | 2010-10-01 17:06:08 +1000 | [diff] [blame] | 266 | ccr |= be32_to_cpup(reg); |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 267 | |
| 268 | out_be32(ndfc->ndfcbase + NDFC_CCR, ccr); |
| 269 | |
| 270 | /* Set the bank settings if given */ |
Grant Likely | 61c7a08 | 2010-04-13 16:12:29 -0700 | [diff] [blame] | 271 | reg = of_get_property(ofdev->dev.of_node, "bank-settings", NULL); |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 272 | if (reg) { |
| 273 | int offset = NDFC_BCFG0 + (ndfc->chip_select << 2); |
Ian Munsie | 766f271 | 2010-10-01 17:06:08 +1000 | [diff] [blame] | 274 | out_be32(ndfc->ndfcbase + offset, be32_to_cpup(reg)); |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 275 | } |
| 276 | |
Grant Likely | 61c7a08 | 2010-04-13 16:12:29 -0700 | [diff] [blame] | 277 | err = ndfc_chip_init(ndfc, ofdev->dev.of_node); |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 278 | if (err) { |
| 279 | iounmap(ndfc->ndfcbase); |
| 280 | return err; |
| 281 | } |
| 282 | |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 283 | return 0; |
| 284 | } |
| 285 | |
Grant Likely | 2dc1158 | 2010-08-06 09:25:50 -0600 | [diff] [blame] | 286 | static int __devexit ndfc_remove(struct platform_device *ofdev) |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 287 | { |
| 288 | struct ndfc_controller *ndfc = dev_get_drvdata(&ofdev->dev); |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 289 | |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 290 | nand_release(&ndfc->mtd); |
| 291 | |
| 292 | return 0; |
| 293 | } |
| 294 | |
| 295 | static const struct of_device_id ndfc_match[] = { |
| 296 | { .compatible = "ibm,ndfc", }, |
| 297 | {} |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 298 | }; |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 299 | MODULE_DEVICE_TABLE(of, ndfc_match); |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 300 | |
Grant Likely | 1c48a5c | 2011-02-17 02:43:24 -0700 | [diff] [blame] | 301 | static struct platform_driver ndfc_driver = { |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 302 | .driver = { |
Grant Likely | 4018294 | 2010-04-13 16:13:02 -0700 | [diff] [blame] | 303 | .name = "ndfc", |
| 304 | .owner = THIS_MODULE, |
| 305 | .of_match_table = ndfc_match, |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 306 | }, |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 307 | .probe = ndfc_probe, |
| 308 | .remove = __devexit_p(ndfc_remove), |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 309 | }; |
| 310 | |
| 311 | static int __init ndfc_nand_init(void) |
| 312 | { |
Grant Likely | 1c48a5c | 2011-02-17 02:43:24 -0700 | [diff] [blame] | 313 | return platform_driver_register(&ndfc_driver); |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 314 | } |
| 315 | |
| 316 | static void __exit ndfc_nand_exit(void) |
| 317 | { |
Grant Likely | 1c48a5c | 2011-02-17 02:43:24 -0700 | [diff] [blame] | 318 | platform_driver_unregister(&ndfc_driver); |
Thomas Gleixner | ce4c61f | 2006-05-23 11:43:28 +0200 | [diff] [blame] | 319 | } |
| 320 | |
| 321 | module_init(ndfc_nand_init); |
| 322 | module_exit(ndfc_nand_exit); |
| 323 | |
| 324 | MODULE_LICENSE("GPL"); |
| 325 | MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>"); |
Sean MacLennan | a808ad3 | 2008-12-10 13:16:34 +0000 | [diff] [blame] | 326 | MODULE_DESCRIPTION("OF Platform driver for NDFC"); |