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Thomas Gleixnerce4c61f2006-05-23 11:43:28 +02001/*
2 * drivers/mtd/ndfc.c
3 *
4 * Overview:
Sean MacLennana808ad32008-12-10 13:16:34 +00005 * Platform independent driver for NDFC (NanD Flash Controller)
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +02006 * integrated into EP440 cores
7 *
Sean MacLennana808ad32008-12-10 13:16:34 +00008 * Ported to an OF platform driver by Sean MacLennan
9 *
10 * The NDFC supports multiple chips, but this driver only supports a
11 * single chip since I do not have access to any boards with
12 * multiple chips.
13 *
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020014 * Author: Thomas Gleixner
15 *
16 * Copyright 2006 IBM
Sean MacLennana808ad32008-12-10 13:16:34 +000017 * Copyright 2008 PIKA Technologies
18 * Sean MacLennan <smaclennan@pikatech.com>
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020019 *
20 * This program is free software; you can redistribute it and/or modify it
21 * under the terms of the GNU General Public License as published by the
22 * Free Software Foundation; either version 2 of the License, or (at your
23 * option) any later version.
24 *
25 */
26#include <linux/module.h>
27#include <linux/mtd/nand.h>
28#include <linux/mtd/nand_ecc.h>
29#include <linux/mtd/partitions.h>
30#include <linux/mtd/ndfc.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090031#include <linux/slab.h>
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020032#include <linux/mtd/mtd.h>
Sean MacLennana808ad32008-12-10 13:16:34 +000033#include <linux/of_platform.h>
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020034#include <asm/io.h>
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020035
Felix Radensky410fe2f2011-04-26 12:36:46 +030036#define NDFC_MAX_CS 4
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020037
38struct ndfc_controller {
Grant Likely2dc11582010-08-06 09:25:50 -060039 struct platform_device *ofdev;
Sean MacLennana808ad32008-12-10 13:16:34 +000040 void __iomem *ndfcbase;
41 struct mtd_info mtd;
42 struct nand_chip chip;
43 int chip_select;
44 struct nand_hw_control ndfc_control;
Sean MacLennana808ad32008-12-10 13:16:34 +000045 struct mtd_partition *parts;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020046};
47
Felix Radensky410fe2f2011-04-26 12:36:46 +030048static struct ndfc_controller ndfc_ctrl[NDFC_MAX_CS];
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020049
50static void ndfc_select_chip(struct mtd_info *mtd, int chip)
51{
52 uint32_t ccr;
Felix Radensky410fe2f2011-04-26 12:36:46 +030053 struct nand_chip *nchip = mtd->priv;
54 struct ndfc_controller *ndfc = nchip->priv;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020055
Sean MacLennana808ad32008-12-10 13:16:34 +000056 ccr = in_be32(ndfc->ndfcbase + NDFC_CCR);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020057 if (chip >= 0) {
58 ccr &= ~NDFC_CCR_BS_MASK;
Sean MacLennana808ad32008-12-10 13:16:34 +000059 ccr |= NDFC_CCR_BS(chip + ndfc->chip_select);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020060 } else
61 ccr |= NDFC_CCR_RESET_CE;
Sean MacLennana808ad32008-12-10 13:16:34 +000062 out_be32(ndfc->ndfcbase + NDFC_CCR, ccr);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020063}
64
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +020065static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020066{
Felix Radensky410fe2f2011-04-26 12:36:46 +030067 struct nand_chip *chip = mtd->priv;
68 struct ndfc_controller *ndfc = chip->priv;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020069
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +020070 if (cmd == NAND_CMD_NONE)
71 return;
72
73 if (ctrl & NAND_CLE)
Thomas Gleixner1794c132006-06-22 13:06:43 +020074 writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_CMD);
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +020075 else
Thomas Gleixner1794c132006-06-22 13:06:43 +020076 writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_ALE);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020077}
78
79static int ndfc_ready(struct mtd_info *mtd)
80{
Felix Radensky410fe2f2011-04-26 12:36:46 +030081 struct nand_chip *chip = mtd->priv;
82 struct ndfc_controller *ndfc = chip->priv;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020083
Sean MacLennana808ad32008-12-10 13:16:34 +000084 return in_be32(ndfc->ndfcbase + NDFC_STAT) & NDFC_STAT_IS_READY;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020085}
86
87static void ndfc_enable_hwecc(struct mtd_info *mtd, int mode)
88{
89 uint32_t ccr;
Felix Radensky410fe2f2011-04-26 12:36:46 +030090 struct nand_chip *chip = mtd->priv;
91 struct ndfc_controller *ndfc = chip->priv;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020092
Sean MacLennana808ad32008-12-10 13:16:34 +000093 ccr = in_be32(ndfc->ndfcbase + NDFC_CCR);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020094 ccr |= NDFC_CCR_RESET_ECC;
Sean MacLennana808ad32008-12-10 13:16:34 +000095 out_be32(ndfc->ndfcbase + NDFC_CCR, ccr);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020096 wmb();
97}
98
99static int ndfc_calculate_ecc(struct mtd_info *mtd,
100 const u_char *dat, u_char *ecc_code)
101{
Felix Radensky410fe2f2011-04-26 12:36:46 +0300102 struct nand_chip *chip = mtd->priv;
103 struct ndfc_controller *ndfc = chip->priv;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200104 uint32_t ecc;
105 uint8_t *p = (uint8_t *)&ecc;
106
107 wmb();
Sean MacLennana808ad32008-12-10 13:16:34 +0000108 ecc = in_be32(ndfc->ndfcbase + NDFC_ECC);
109 /* The NDFC uses Smart Media (SMC) bytes order */
Feng Kan76c23c32009-08-25 11:27:20 -0700110 ecc_code[0] = p[1];
111 ecc_code[1] = p[2];
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200112 ecc_code[2] = p[3];
113
114 return 0;
115}
116
117/*
118 * Speedups for buffer read/write/verify
119 *
120 * NDFC allows 32bit read/write of data. So we can speed up the buffer
121 * functions. No further checking, as nand_base will always read/write
122 * page aligned.
123 */
124static void ndfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
125{
Felix Radensky410fe2f2011-04-26 12:36:46 +0300126 struct nand_chip *chip = mtd->priv;
127 struct ndfc_controller *ndfc = chip->priv;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200128 uint32_t *p = (uint32_t *) buf;
129
130 for(;len > 0; len -= 4)
Sean MacLennana808ad32008-12-10 13:16:34 +0000131 *p++ = in_be32(ndfc->ndfcbase + NDFC_DATA);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200132}
133
134static void ndfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
135{
Felix Radensky410fe2f2011-04-26 12:36:46 +0300136 struct nand_chip *chip = mtd->priv;
137 struct ndfc_controller *ndfc = chip->priv;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200138 uint32_t *p = (uint32_t *) buf;
139
140 for(;len > 0; len -= 4)
Sean MacLennana808ad32008-12-10 13:16:34 +0000141 out_be32(ndfc->ndfcbase + NDFC_DATA, *p++);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200142}
143
144static int ndfc_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
145{
Felix Radensky410fe2f2011-04-26 12:36:46 +0300146 struct nand_chip *chip = mtd->priv;
147 struct ndfc_controller *ndfc = chip->priv;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200148 uint32_t *p = (uint32_t *) buf;
149
150 for(;len > 0; len -= 4)
Sean MacLennana808ad32008-12-10 13:16:34 +0000151 if (*p++ != in_be32(ndfc->ndfcbase + NDFC_DATA))
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200152 return -EFAULT;
153 return 0;
154}
155
156/*
157 * Initialize chip structure
158 */
Sean MacLennana808ad32008-12-10 13:16:34 +0000159static int ndfc_chip_init(struct ndfc_controller *ndfc,
160 struct device_node *node)
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200161{
Sean MacLennana808ad32008-12-10 13:16:34 +0000162#ifdef CONFIG_MTD_CMDLINE_PARTS
163 static const char *part_types[] = { "cmdlinepart", NULL };
164#else
165 static const char *part_types[] = { NULL };
166#endif
Sean MacLennana808ad32008-12-10 13:16:34 +0000167 struct device_node *flash_np;
168 struct nand_chip *chip = &ndfc->chip;
169 int ret;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200170
171 chip->IO_ADDR_R = ndfc->ndfcbase + NDFC_DATA;
172 chip->IO_ADDR_W = ndfc->ndfcbase + NDFC_DATA;
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200173 chip->cmd_ctrl = ndfc_hwcontrol;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200174 chip->dev_ready = ndfc_ready;
175 chip->select_chip = ndfc_select_chip;
176 chip->chip_delay = 50;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200177 chip->controller = &ndfc->ndfc_control;
178 chip->read_buf = ndfc_read_buf;
179 chip->write_buf = ndfc_write_buf;
180 chip->verify_buf = ndfc_verify_buf;
Thomas Gleixner6dfc6d22006-05-23 12:00:46 +0200181 chip->ecc.correct = nand_correct_data;
182 chip->ecc.hwctl = ndfc_enable_hwecc;
183 chip->ecc.calculate = ndfc_calculate_ecc;
184 chip->ecc.mode = NAND_ECC_HW;
185 chip->ecc.size = 256;
186 chip->ecc.bytes = 3;
Felix Radensky410fe2f2011-04-26 12:36:46 +0300187 chip->priv = ndfc;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200188
Sean MacLennana808ad32008-12-10 13:16:34 +0000189 ndfc->mtd.priv = chip;
190 ndfc->mtd.owner = THIS_MODULE;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200191
Sean MacLennana808ad32008-12-10 13:16:34 +0000192 flash_np = of_get_next_child(node, NULL);
193 if (!flash_np)
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200194 return -ENODEV;
Sean MacLennana808ad32008-12-10 13:16:34 +0000195
196 ndfc->mtd.name = kasprintf(GFP_KERNEL, "%s.%s",
Kay Sieversc36f1e32009-03-24 16:38:21 -0700197 dev_name(&ndfc->ofdev->dev), flash_np->name);
Sean MacLennana808ad32008-12-10 13:16:34 +0000198 if (!ndfc->mtd.name) {
199 ret = -ENOMEM;
200 goto err;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200201 }
202
Sean MacLennana808ad32008-12-10 13:16:34 +0000203 ret = nand_scan(&ndfc->mtd, 1);
204 if (ret)
205 goto err;
206
Sean MacLennana808ad32008-12-10 13:16:34 +0000207 ret = parse_mtd_partitions(&ndfc->mtd, part_types, &ndfc->parts, 0);
208 if (ret < 0)
209 goto err;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200210
Sean MacLennana808ad32008-12-10 13:16:34 +0000211 if (ret == 0) {
212 ret = of_mtd_parse_partitions(&ndfc->ofdev->dev, flash_np,
213 &ndfc->parts);
214 if (ret < 0)
215 goto err;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200216 }
217
Jamie Iles1f3a7c62011-05-23 10:23:28 +0100218 ret = mtd_device_register(&ndfc->mtd, ndfc->parts, ret);
Sean MacLennana808ad32008-12-10 13:16:34 +0000219
220err:
221 of_node_put(flash_np);
222 if (ret)
223 kfree(ndfc->mtd.name);
224 return ret;
225}
226
Grant Likely1c48a5c2011-02-17 02:43:24 -0700227static int __devinit ndfc_probe(struct platform_device *ofdev)
Sean MacLennana808ad32008-12-10 13:16:34 +0000228{
Felix Radensky410fe2f2011-04-26 12:36:46 +0300229 struct ndfc_controller *ndfc;
Ian Munsie766f2712010-10-01 17:06:08 +1000230 const __be32 *reg;
Sean MacLennana808ad32008-12-10 13:16:34 +0000231 u32 ccr;
Felix Radensky410fe2f2011-04-26 12:36:46 +0300232 int err, len, cs;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200233
Sean MacLennana808ad32008-12-10 13:16:34 +0000234 /* Read the reg property to get the chip select */
Grant Likely61c7a082010-04-13 16:12:29 -0700235 reg = of_get_property(ofdev->dev.of_node, "reg", &len);
Sean MacLennana808ad32008-12-10 13:16:34 +0000236 if (reg == NULL || len != 12) {
237 dev_err(&ofdev->dev, "unable read reg property (%d)\n", len);
238 return -ENOENT;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200239 }
Felix Radensky410fe2f2011-04-26 12:36:46 +0300240
241 cs = be32_to_cpu(reg[0]);
242 if (cs >= NDFC_MAX_CS) {
243 dev_err(&ofdev->dev, "invalid CS number (%d)\n", cs);
244 return -EINVAL;
245 }
246
247 ndfc = &ndfc_ctrl[cs];
248 ndfc->chip_select = cs;
249
250 spin_lock_init(&ndfc->ndfc_control.lock);
251 init_waitqueue_head(&ndfc->ndfc_control.wq);
252 ndfc->ofdev = ofdev;
253 dev_set_drvdata(&ofdev->dev, ndfc);
Sean MacLennana808ad32008-12-10 13:16:34 +0000254
Grant Likely61c7a082010-04-13 16:12:29 -0700255 ndfc->ndfcbase = of_iomap(ofdev->dev.of_node, 0);
Sean MacLennana808ad32008-12-10 13:16:34 +0000256 if (!ndfc->ndfcbase) {
257 dev_err(&ofdev->dev, "failed to get memory\n");
258 return -EIO;
259 }
260
261 ccr = NDFC_CCR_BS(ndfc->chip_select);
262
263 /* It is ok if ccr does not exist - just default to 0 */
Grant Likely61c7a082010-04-13 16:12:29 -0700264 reg = of_get_property(ofdev->dev.of_node, "ccr", NULL);
Sean MacLennana808ad32008-12-10 13:16:34 +0000265 if (reg)
Ian Munsie766f2712010-10-01 17:06:08 +1000266 ccr |= be32_to_cpup(reg);
Sean MacLennana808ad32008-12-10 13:16:34 +0000267
268 out_be32(ndfc->ndfcbase + NDFC_CCR, ccr);
269
270 /* Set the bank settings if given */
Grant Likely61c7a082010-04-13 16:12:29 -0700271 reg = of_get_property(ofdev->dev.of_node, "bank-settings", NULL);
Sean MacLennana808ad32008-12-10 13:16:34 +0000272 if (reg) {
273 int offset = NDFC_BCFG0 + (ndfc->chip_select << 2);
Ian Munsie766f2712010-10-01 17:06:08 +1000274 out_be32(ndfc->ndfcbase + offset, be32_to_cpup(reg));
Sean MacLennana808ad32008-12-10 13:16:34 +0000275 }
276
Grant Likely61c7a082010-04-13 16:12:29 -0700277 err = ndfc_chip_init(ndfc, ofdev->dev.of_node);
Sean MacLennana808ad32008-12-10 13:16:34 +0000278 if (err) {
279 iounmap(ndfc->ndfcbase);
280 return err;
281 }
282
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200283 return 0;
284}
285
Grant Likely2dc11582010-08-06 09:25:50 -0600286static int __devexit ndfc_remove(struct platform_device *ofdev)
Sean MacLennana808ad32008-12-10 13:16:34 +0000287{
288 struct ndfc_controller *ndfc = dev_get_drvdata(&ofdev->dev);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200289
Sean MacLennana808ad32008-12-10 13:16:34 +0000290 nand_release(&ndfc->mtd);
291
292 return 0;
293}
294
295static const struct of_device_id ndfc_match[] = {
296 { .compatible = "ibm,ndfc", },
297 {}
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200298};
Sean MacLennana808ad32008-12-10 13:16:34 +0000299MODULE_DEVICE_TABLE(of, ndfc_match);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200300
Grant Likely1c48a5c2011-02-17 02:43:24 -0700301static struct platform_driver ndfc_driver = {
Sean MacLennana808ad32008-12-10 13:16:34 +0000302 .driver = {
Grant Likely40182942010-04-13 16:13:02 -0700303 .name = "ndfc",
304 .owner = THIS_MODULE,
305 .of_match_table = ndfc_match,
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200306 },
Sean MacLennana808ad32008-12-10 13:16:34 +0000307 .probe = ndfc_probe,
308 .remove = __devexit_p(ndfc_remove),
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200309};
310
311static int __init ndfc_nand_init(void)
312{
Grant Likely1c48a5c2011-02-17 02:43:24 -0700313 return platform_driver_register(&ndfc_driver);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200314}
315
316static void __exit ndfc_nand_exit(void)
317{
Grant Likely1c48a5c2011-02-17 02:43:24 -0700318 platform_driver_unregister(&ndfc_driver);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200319}
320
321module_init(ndfc_nand_init);
322module_exit(ndfc_nand_exit);
323
324MODULE_LICENSE("GPL");
325MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
Sean MacLennana808ad32008-12-10 13:16:34 +0000326MODULE_DESCRIPTION("OF Platform driver for NDFC");