am 6bb5bf61: Merge "Add watchdog.h"
* commit '6bb5bf6108c36cf17f18d2d7b1c01ad5f8e9be42':
Add watchdog.h
diff --git a/original/asm-generic/fcntl.h b/original/asm-generic/fcntl.h
index c154b9d..9e5b035 100644
--- a/original/asm-generic/fcntl.h
+++ b/original/asm-generic/fcntl.h
@@ -3,8 +3,18 @@
#include <linux/types.h>
-/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
- located on an ext2 file system */
+/*
+ * FMODE_EXEC is 0x20
+ * FMODE_NONOTIFY is 0x1000000
+ * These cannot be used by userspace O_* until internal and external open
+ * flags are split.
+ * -Eric Paris
+ */
+
+/*
+ * When introducing new O_* bits, please check its uniqueness in fcntl_init().
+ */
+
#define O_ACCMODE 00000003
#define O_RDONLY 00000000
#define O_WRONLY 00000001
@@ -27,8 +37,8 @@
#ifndef O_NONBLOCK
#define O_NONBLOCK 00004000
#endif
-#ifndef O_SYNC
-#define O_SYNC 00010000
+#ifndef O_DSYNC
+#define O_DSYNC 00010000 /* used to be O_SYNC, see below */
#endif
#ifndef FASYNC
#define FASYNC 00020000 /* fcntl, for BSD compatibility */
@@ -48,6 +58,32 @@
#ifndef O_NOATIME
#define O_NOATIME 01000000
#endif
+#ifndef O_CLOEXEC
+#define O_CLOEXEC 02000000 /* set close_on_exec */
+#endif
+
+/*
+ * Before Linux 2.6.33 only O_DSYNC semantics were implemented, but using
+ * the O_SYNC flag. We continue to use the existing numerical value
+ * for O_DSYNC semantics now, but using the correct symbolic name for it.
+ * This new value is used to request true Posix O_SYNC semantics. It is
+ * defined in this strange way to make sure applications compiled against
+ * new headers get at least O_DSYNC semantics on older kernels.
+ *
+ * This has the nice side-effect that we can simply test for O_DSYNC
+ * wherever we do not care if O_DSYNC or O_SYNC is used.
+ *
+ * Note: __O_SYNC must never be used directly.
+ */
+#ifndef O_SYNC
+#define __O_SYNC 04000000
+#define O_SYNC (__O_SYNC|O_DSYNC)
+#endif
+
+#ifndef O_PATH
+#define O_PATH 010000000
+#endif
+
#ifndef O_NDELAY
#define O_NDELAY O_NONBLOCK
#endif
@@ -71,6 +107,28 @@
#define F_GETSIG 11 /* for sockets. */
#endif
+#ifndef CONFIG_64BIT
+#ifndef F_GETLK64
+#define F_GETLK64 12 /* using 'struct flock64' */
+#define F_SETLK64 13
+#define F_SETLKW64 14
+#endif
+#endif
+
+#ifndef F_SETOWN_EX
+#define F_SETOWN_EX 15
+#define F_GETOWN_EX 16
+#endif
+
+#define F_OWNER_TID 0
+#define F_OWNER_PID 1
+#define F_OWNER_PGRP 2
+
+struct f_owner_ex {
+ int type;
+ __kernel_pid_t pid;
+};
+
/* for F_[GET|SET]FL */
#define FD_CLOEXEC 1 /* actually anything with low bit set goes */
@@ -87,11 +145,6 @@
#define F_SHLCK 8 /* or 4 */
#endif
-/* for leases */
-#ifndef F_INPROGRESS
-#define F_INPROGRESS 16
-#endif
-
/* operations for bsd flock(), also used by the kernel implementation */
#define LOCK_SH 1 /* shared lock */
#define LOCK_EX 2 /* exclusive lock */
@@ -114,21 +167,15 @@
struct flock {
short l_type;
short l_whence;
- off_t l_start;
- off_t l_len;
- pid_t l_pid;
+ __kernel_off_t l_start;
+ __kernel_off_t l_len;
+ __kernel_pid_t l_pid;
__ARCH_FLOCK_PAD
};
#endif
#ifndef CONFIG_64BIT
-#ifndef F_GETLK64
-#define F_GETLK64 12 /* using 'struct flock64' */
-#define F_SETLK64 13
-#define F_SETLKW64 14
-#endif
-
#ifndef HAVE_ARCH_STRUCT_FLOCK64
#ifndef __ARCH_FLOCK64_PAD
#define __ARCH_FLOCK64_PAD
@@ -137,9 +184,9 @@
struct flock64 {
short l_type;
short l_whence;
- loff_t l_start;
- loff_t l_len;
- pid_t l_pid;
+ __kernel_loff_t l_start;
+ __kernel_loff_t l_len;
+ __kernel_pid_t l_pid;
__ARCH_FLOCK64_PAD
};
#endif
diff --git a/original/linux/fb.h b/original/linux/fb.h
old mode 100644
new mode 100755
index 5e51864..3c10ffe
--- a/original/linux/fb.h
+++ b/original/linux/fb.h
@@ -45,6 +45,7 @@
#define FB_TYPE_INTERLEAVED_PLANES 2 /* Interleaved planes */
#define FB_TYPE_TEXT 3 /* Text/attributes */
#define FB_TYPE_VGA_PLANES 4 /* EGA/VGA planes */
+#define FB_TYPE_FOURCC 5 /* Type identified by a V4L2 FOURCC */
#define FB_AUX_TEXT_MDA 0 /* Monochrome text */
#define FB_AUX_TEXT_CGA 1 /* CGA/EGA/VGA Color text */
@@ -69,6 +70,7 @@
#define FB_VISUAL_PSEUDOCOLOR 3 /* Pseudo color (like atari) */
#define FB_VISUAL_DIRECTCOLOR 4 /* Direct color */
#define FB_VISUAL_STATIC_PSEUDOCOLOR 5 /* Pseudo color readonly */
+#define FB_VISUAL_FOURCC 6 /* Visual identified by a V4L2 FOURCC */
#define FB_ACCEL_NONE 0 /* no hardware accelerator */
#define FB_ACCEL_ATARIBLITT 1 /* Atari Blitter */
@@ -154,6 +156,8 @@
#define FB_ACCEL_PUV3_UNIGFX 0xa0 /* PKUnity-v3 Unigfx */
+#define FB_CAP_FOURCC 1 /* Device supports FOURCC-based formats */
+
struct fb_fix_screeninfo {
char id[16]; /* identification string eg "TT Builtin" */
unsigned long smem_start; /* Start of frame buffer mem */
@@ -171,7 +175,8 @@
__u32 mmio_len; /* Length of Memory Mapped I/O */
__u32 accel; /* Indicate to driver which */
/* specific chip/card we have */
- __u16 reserved[3]; /* Reserved for future compatibility */
+ __u16 capabilities; /* see FB_CAP_* */
+ __u16 reserved[2]; /* Reserved for future compatibility */
};
/* Interpretation of offset for color fields: All offsets are from the right,
@@ -252,8 +257,8 @@
__u32 yoffset; /* resolution */
__u32 bits_per_pixel; /* guess what */
- __u32 grayscale; /* != 0 Graylevels instead of colors */
-
+ __u32 grayscale; /* 0 = color, 1 = grayscale, */
+ /* >1 = FOURCC */
struct fb_bitfield red; /* bitfield in fb mem if true color, */
struct fb_bitfield green; /* else only length is significant */
struct fb_bitfield blue;
@@ -279,7 +284,8 @@
__u32 sync; /* see FB_SYNC_* */
__u32 vmode; /* see FB_VMODE_* */
__u32 rotate; /* angle we rotate counter clockwise */
- __u32 reserved[5]; /* Reserved for future compatibility */
+ __u32 colorspace; /* colorspace for FOURCC-based modes */
+ __u32 reserved[4]; /* Reserved for future compatibility */
};
struct fb_cmap {
@@ -407,7 +413,6 @@
#include <linux/fs.h>
#include <linux/init.h>
-#include <linux/device.h>
#include <linux/workqueue.h>
#include <linux/notifier.h>
#include <linux/list.h>
@@ -445,8 +450,6 @@
#define FB_MISC_PRIM_COLOR 1
#define FB_MISC_1ST_DETAIL 2 /* First Detailed Timing is preferred */
-#define FB_MISC_HDMI 4 /* display supports HDMI signaling */
-
struct fb_chroma {
__u32 redx; /* in fraction of 1024 */
__u32 greenx;
@@ -1005,6 +1008,7 @@
/* drivers/video/fbmem.c */
extern int register_framebuffer(struct fb_info *fb_info);
extern int unregister_framebuffer(struct fb_info *fb_info);
+extern int unlink_framebuffer(struct fb_info *fb_info);
extern void remove_conflicting_framebuffers(struct apertures_struct *a,
const char *name, bool primary);
extern int fb_prepare_logo(struct fb_info *fb_info, int rotate);
@@ -1051,7 +1055,8 @@
struct inode *inode,
struct file *file);
extern void fb_deferred_io_cleanup(struct fb_info *info);
-extern int fb_deferred_io_fsync(struct file *file, int datasync);
+extern int fb_deferred_io_fsync(struct file *file, loff_t start,
+ loff_t end, int datasync);
static inline bool fb_be_math(struct fb_info *info)
{
@@ -1111,7 +1116,6 @@
/* drivers/video/modedb.c */
#define VESA_MODEDB_SIZE 34
-#define CEA_MODEDB_SIZE 65
extern void fb_var_to_videomode(struct fb_videomode *mode,
const struct fb_var_screeninfo *var);
extern void fb_videomode_to_var(struct fb_var_screeninfo *var,
@@ -1164,7 +1168,7 @@
extern const char *fb_mode_option;
extern const struct fb_videomode vesa_modes[];
-extern const struct fb_videomode cea_modes[];
+extern const struct fb_videomode cea_modes[64];
struct fb_modelist {
struct list_head list;
diff --git a/original/linux/genlock.h b/original/linux/genlock.h
new file mode 100644
index 0000000..587c49d
--- /dev/null
+++ b/original/linux/genlock.h
@@ -0,0 +1,52 @@
+#ifndef _GENLOCK_H_
+#define _GENLOCK_H_
+
+#ifdef __KERNEL__
+
+struct genlock;
+struct genlock_handle;
+
+struct genlock_handle *genlock_get_handle(void);
+struct genlock_handle *genlock_get_handle_fd(int fd);
+void genlock_put_handle(struct genlock_handle *handle);
+struct genlock *genlock_create_lock(struct genlock_handle *);
+struct genlock *genlock_attach_lock(struct genlock_handle *, int fd);
+int genlock_wait(struct genlock_handle *handle, u32 timeout);
+/* genlock_release_lock was deprecated */
+int genlock_lock(struct genlock_handle *handle, int op, int flags,
+ u32 timeout);
+#endif
+
+#define GENLOCK_UNLOCK 0
+#define GENLOCK_WRLOCK 1
+#define GENLOCK_RDLOCK 2
+
+#define GENLOCK_NOBLOCK (1 << 0)
+#define GENLOCK_WRITE_TO_READ (1 << 1)
+
+struct genlock_lock {
+ int fd;
+ int op;
+ int flags;
+ int timeout;
+};
+
+#define GENLOCK_IOC_MAGIC 'G'
+
+#define GENLOCK_IOC_NEW _IO(GENLOCK_IOC_MAGIC, 0)
+#define GENLOCK_IOC_EXPORT _IOR(GENLOCK_IOC_MAGIC, 1, \
+ struct genlock_lock)
+#define GENLOCK_IOC_ATTACH _IOW(GENLOCK_IOC_MAGIC, 2, \
+ struct genlock_lock)
+
+/* Deprecated */
+#define GENLOCK_IOC_LOCK _IOW(GENLOCK_IOC_MAGIC, 3, \
+ struct genlock_lock)
+
+/* Deprecated */
+#define GENLOCK_IOC_RELEASE _IO(GENLOCK_IOC_MAGIC, 4)
+#define GENLOCK_IOC_WAIT _IOW(GENLOCK_IOC_MAGIC, 5, \
+ struct genlock_lock)
+#define GENLOCK_IOC_DREADLOCK _IOW(GENLOCK_IOC_MAGIC, 6, \
+ struct genlock_lock)
+#endif
diff --git a/original/linux/ion.h b/original/linux/ion.h
index 111982f..e72c09e 100644
--- a/original/linux/ion.h
+++ b/original/linux/ion.h
@@ -27,7 +27,9 @@
* @ION_HEAP_TYPE_CARVEOUT: memory allocated from a prereserved
* carveout heap, allocations are physically
* contiguous
- * @ION_HEAP_END: helper for iterating over heaps
+ * @ION_NUM_HEAPS: helper for iterating over heaps, a bit mask
+ * is used to identify the heaps, so only 32
+ * total heap types are supported
*/
enum ion_heap_type {
ION_HEAP_TYPE_SYSTEM,
@@ -35,13 +37,22 @@
ION_HEAP_TYPE_CARVEOUT,
ION_HEAP_TYPE_CUSTOM, /* must be last so device specific heaps always
are at the end of this enum */
- ION_NUM_HEAPS,
+ ION_NUM_HEAPS = 16,
};
#define ION_HEAP_SYSTEM_MASK (1 << ION_HEAP_TYPE_SYSTEM)
#define ION_HEAP_SYSTEM_CONTIG_MASK (1 << ION_HEAP_TYPE_SYSTEM_CONTIG)
#define ION_HEAP_CARVEOUT_MASK (1 << ION_HEAP_TYPE_CARVEOUT)
+/**
+ * heap flags - the lower 16 bits are used by core ion, the upper 16
+ * bits are reserved for use by the heaps themselves.
+ */
+#define ION_FLAG_CACHED 1 /* mappings of this buffer should be
+ cached, ion will do cache
+ maintenance when the buffer is
+ mapped for dma */
+
#ifdef __KERNEL__
struct ion_device;
struct ion_heap;
@@ -87,6 +98,17 @@
};
/**
+ * ion_reserve() - reserve memory for ion heaps if applicable
+ * @data: platform data specifying starting physical address and
+ * size
+ *
+ * Calls memblock reserve to set aside memory for heaps that are
+ * located at specific memory addresses or of specfic sizes not
+ * managed by the kernel
+ */
+void ion_reserve(struct ion_platform_data *data);
+
+/**
* ion_client_create() - allocate a client and returns it
* @dev: the global ion device
* @heap_mask: mask of heaps this client can allocate from
@@ -110,14 +132,18 @@
* @len: size of the allocation
* @align: requested allocation alignment, lots of hardware blocks have
* alignment requirements of some kind
- * @flags: mask of heaps to allocate from, if multiple bits are set
+ * @heap_mask: mask of heaps to allocate from, if multiple bits are set
* heaps will be tried in order from lowest to highest order bit
+ * @flags: heap flags, the low 16 bits are consumed by ion, the high 16
+ * bits are passed on to the respective heap and can be heap
+ * custom
*
* Allocate memory in one of the heaps provided in heap mask and return
* an opaque handle to it.
*/
struct ion_handle *ion_alloc(struct ion_client *client, size_t len,
- size_t align, unsigned int flags);
+ size_t align, unsigned int heap_mask,
+ unsigned int flags);
/**
* ion_free - free a handle
@@ -138,7 +164,7 @@
* This function queries the heap for a particular handle to get the
* handle's physical address. It't output is only correct if
* a heap returns physically contiguous memory -- in other cases
- * this api should not be implemented -- ion_map_dma should be used
+ * this api should not be implemented -- ion_sg_table should be used
* instead. Returns -EINVAL if the handle is invalid. This has
* no implications on the reference counting of the handle --
* the returned value may not be valid if the caller is not
@@ -148,6 +174,17 @@
ion_phys_addr_t *addr, size_t *len);
/**
+ * ion_map_dma - return an sg_table describing a handle
+ * @client: the client
+ * @handle: the handle
+ *
+ * This function returns the sg_table describing
+ * a particular ion handle.
+ */
+struct sg_table *ion_sg_table(struct ion_client *client,
+ struct ion_handle *handle);
+
+/**
* ion_map_kernel - create mapping for the given handle
* @client: the client
* @handle: handle to map
@@ -165,58 +202,23 @@
void ion_unmap_kernel(struct ion_client *client, struct ion_handle *handle);
/**
- * ion_map_dma - create a dma mapping for a given handle
+ * ion_share_dma_buf() - given an ion client, create a dma-buf fd
* @client: the client
- * @handle: handle to map
- *
- * Return an sglist describing the given handle
+ * @handle: the handle
*/
-struct scatterlist *ion_map_dma(struct ion_client *client,
- struct ion_handle *handle);
+int ion_share_dma_buf(struct ion_client *client, struct ion_handle *handle);
/**
- * ion_unmap_dma() - destroy a dma mapping for a handle
+ * ion_import_dma_buf() - given an dma-buf fd from the ion exporter get handle
* @client: the client
- * @handle: handle to unmap
- */
-void ion_unmap_dma(struct ion_client *client, struct ion_handle *handle);
-
-/**
- * ion_share() - given a handle, obtain a buffer to pass to other clients
- * @client: the client
- * @handle: the handle to share
+ * @fd: the dma-buf fd
*
- * Given a handle, return a buffer which exists in a global name
- * space and can be passed to other clients. Should be passed into ion_import
- * to obtain a new handle for this buffer.
+ * Given an dma-buf fd that was allocated through ion via ion_share_dma_buf,
+ * import that fd and return a handle representing it. If a dma-buf from
+ * another exporter is passed in this function will return ERR_PTR(-EINVAL)
*/
-struct ion_buffer *ion_share(struct ion_client *client,
- struct ion_handle *handle);
+struct ion_handle *ion_import_dma_buf(struct ion_client *client, int fd);
-/**
- * ion_import() - given an buffer in another client, import it
- * @client: this blocks client
- * @buffer: the buffer to import (as obtained from ion_share)
- *
- * Given a buffer, add it to the client and return the handle to use to refer
- * to it further. This is called to share a handle from one kernel client to
- * another.
- */
-struct ion_handle *ion_import(struct ion_client *client,
- struct ion_buffer *buffer);
-
-/**
- * ion_import_fd() - given an fd obtained via ION_IOC_SHARE ioctl, import it
- * @client: this blocks client
- * @fd: the fd
- *
- * A helper function for drivers that will be recieving ion buffers shared
- * with them from userspace. These buffers are represented by a file
- * descriptor obtained as the return from the ION_IOC_SHARE ioctl.
- * This function coverts that fd into the underlying buffer, and returns
- * the handle to use to refer to it further.
- */
-struct ion_handle *ion_import_fd(struct ion_client *client, int fd);
#endif /* __KERNEL__ */
/**
@@ -231,6 +233,7 @@
* struct ion_allocation_data - metadata passed from userspace for allocations
* @len: size of the allocation
* @align: required alignment of the allocation
+ * @heap_mask: mask of heaps to allocate from
* @flags: flags passed to heap
* @handle: pointer that will be populated with a cookie to use to refer
* to this allocation
@@ -240,6 +243,7 @@
struct ion_allocation_data {
size_t len;
size_t align;
+ unsigned int heap_mask;
unsigned int flags;
struct ion_handle *handle;
};
@@ -326,7 +330,17 @@
* descriptor obtained from ION_IOC_SHARE and returns the struct with the handle
* filed set to the corresponding opaque handle.
*/
-#define ION_IOC_IMPORT _IOWR(ION_IOC_MAGIC, 5, int)
+#define ION_IOC_IMPORT _IOWR(ION_IOC_MAGIC, 5, struct ion_fd_data)
+
+/**
+ * DOC: ION_IOC_SYNC - syncs a shared file descriptors to memory
+ *
+ * Deprecated in favor of using the dma_buf api's correctly (syncing
+ * will happend automatically when the buffer is mapped to a device).
+ * If necessary should be used after touching a cached buffer from the cpu,
+ * this will make the buffer in memory coherent.
+ */
+#define ION_IOC_SYNC _IOWR(ION_IOC_MAGIC, 7, struct ion_fd_data)
/**
* DOC: ION_IOC_CUSTOM - call architecture specific ion ioctl
diff --git a/original/linux/media.h b/original/linux/media.h
new file mode 100644
index 0000000..0ef8833
--- /dev/null
+++ b/original/linux/media.h
@@ -0,0 +1,132 @@
+/*
+ * Multimedia device API
+ *
+ * Copyright (C) 2010 Nokia Corporation
+ *
+ * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+ * Sakari Ailus <sakari.ailus@iki.fi>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __LINUX_MEDIA_H
+#define __LINUX_MEDIA_H
+
+#include <linux/ioctl.h>
+#include <linux/types.h>
+#include <linux/version.h>
+
+#define MEDIA_API_VERSION KERNEL_VERSION(0, 1, 0)
+
+struct media_device_info {
+ char driver[16];
+ char model[32];
+ char serial[40];
+ char bus_info[32];
+ __u32 media_version;
+ __u32 hw_revision;
+ __u32 driver_version;
+ __u32 reserved[31];
+};
+
+#define MEDIA_ENT_ID_FLAG_NEXT (1 << 31)
+
+#define MEDIA_ENT_TYPE_SHIFT 16
+#define MEDIA_ENT_TYPE_MASK 0x00ff0000
+#define MEDIA_ENT_SUBTYPE_MASK 0x0000ffff
+
+#define MEDIA_ENT_T_DEVNODE (1 << MEDIA_ENT_TYPE_SHIFT)
+#define MEDIA_ENT_T_DEVNODE_V4L (MEDIA_ENT_T_DEVNODE + 1)
+#define MEDIA_ENT_T_DEVNODE_FB (MEDIA_ENT_T_DEVNODE + 2)
+#define MEDIA_ENT_T_DEVNODE_ALSA (MEDIA_ENT_T_DEVNODE + 3)
+#define MEDIA_ENT_T_DEVNODE_DVB (MEDIA_ENT_T_DEVNODE + 4)
+
+#define MEDIA_ENT_T_V4L2_SUBDEV (2 << MEDIA_ENT_TYPE_SHIFT)
+#define MEDIA_ENT_T_V4L2_SUBDEV_SENSOR (MEDIA_ENT_T_V4L2_SUBDEV + 1)
+#define MEDIA_ENT_T_V4L2_SUBDEV_FLASH (MEDIA_ENT_T_V4L2_SUBDEV + 2)
+#define MEDIA_ENT_T_V4L2_SUBDEV_LENS (MEDIA_ENT_T_V4L2_SUBDEV + 3)
+
+#define MEDIA_ENT_FL_DEFAULT (1 << 0)
+
+struct media_entity_desc {
+ __u32 id;
+ char name[32];
+ __u32 type;
+ __u32 revision;
+ __u32 flags;
+ __u32 group_id;
+ __u16 pads;
+ __u16 links;
+
+ __u32 reserved[4];
+
+ union {
+ /* Node specifications */
+ struct {
+ __u32 major;
+ __u32 minor;
+ } v4l;
+ struct {
+ __u32 major;
+ __u32 minor;
+ } fb;
+ struct {
+ __u32 card;
+ __u32 device;
+ __u32 subdevice;
+ } alsa;
+ int dvb;
+
+ /* Sub-device specifications */
+ /* Nothing needed yet */
+ __u8 raw[184];
+ };
+};
+
+#define MEDIA_PAD_FL_SINK (1 << 0)
+#define MEDIA_PAD_FL_SOURCE (1 << 1)
+
+struct media_pad_desc {
+ __u32 entity; /* entity ID */
+ __u16 index; /* pad index */
+ __u32 flags; /* pad flags */
+ __u32 reserved[2];
+};
+
+#define MEDIA_LNK_FL_ENABLED (1 << 0)
+#define MEDIA_LNK_FL_IMMUTABLE (1 << 1)
+#define MEDIA_LNK_FL_DYNAMIC (1 << 2)
+
+struct media_link_desc {
+ struct media_pad_desc source;
+ struct media_pad_desc sink;
+ __u32 flags;
+ __u32 reserved[2];
+};
+
+struct media_links_enum {
+ __u32 entity;
+ /* Should have enough room for pads elements */
+ struct media_pad_desc __user *pads;
+ /* Should have enough room for links elements */
+ struct media_link_desc __user *links;
+ __u32 reserved[4];
+};
+
+#define MEDIA_IOC_DEVICE_INFO _IOWR('|', 0x00, struct media_device_info)
+#define MEDIA_IOC_ENUM_ENTITIES _IOWR('|', 0x01, struct media_entity_desc)
+#define MEDIA_IOC_ENUM_LINKS _IOWR('|', 0x02, struct media_links_enum)
+#define MEDIA_IOC_SETUP_LINK _IOWR('|', 0x03, struct media_link_desc)
+
+#endif /* __LINUX_MEDIA_H */
diff --git a/original/linux/mfd/msm-adie-codec.h b/original/linux/mfd/msm-adie-codec.h
new file mode 100644
index 0000000..651d34a
--- /dev/null
+++ b/original/linux/mfd/msm-adie-codec.h
@@ -0,0 +1,146 @@
+#ifndef __LINUX_MFD_MSM_ADIE_CODEC_H
+#define __LINUX_MFD_MSM_ADIE_CODEC_H
+
+#include <linux/types.h>
+
+/* Value Represents a entry */
+#define ADIE_CODEC_ACTION_ENTRY 0x1
+/* Value representing a delay wait */
+#define ADIE_CODEC_ACTION_DELAY_WAIT 0x2
+/* Value representing a stage reached */
+#define ADIE_CODEC_ACTION_STAGE_REACHED 0x3
+
+/* This value is the state after the client sets the path */
+#define ADIE_CODEC_PATH_OFF 0x0050
+
+/* State to which client asks the drv to proceed to where it can
+ * set up the clocks and 0-fill PCM buffers
+ */
+#define ADIE_CODEC_DIGITAL_READY 0x0100
+
+/* State to which client asks the drv to proceed to where it can
+ * start sending data after internal steady state delay
+ */
+#define ADIE_CODEC_DIGITAL_ANALOG_READY 0x1000
+
+
+/* Client Asks adie to switch off the Analog portion of the
+ * the internal codec. After the use of this path
+ */
+#define ADIE_CODEC_ANALOG_OFF 0x0750
+
+
+/* Client Asks adie to switch off the digital portion of the
+ * the internal codec. After switching off the analog portion.
+ *
+ * 0-fill PCM may or maynot be sent at this point
+ *
+ */
+#define ADIE_CODEC_DIGITAL_OFF 0x0600
+
+/* State to which client asks the drv to write the default values
+ * to the registers */
+#define ADIE_CODEC_FLASH_IMAGE 0x0001
+
+/* Path type */
+#define ADIE_CODEC_RX 0
+#define ADIE_CODEC_TX 1
+#define ADIE_CODEC_LB 3
+#define ADIE_CODEC_MAX 4
+
+#define ADIE_CODEC_PACK_ENTRY(reg, mask, val) ((val)|(mask << 8)|(reg << 16))
+
+#define ADIE_CODEC_UNPACK_ENTRY(packed, reg, mask, val) \
+ do { \
+ ((reg) = ((packed >> 16) & (0xff))); \
+ ((mask) = ((packed >> 8) & (0xff))); \
+ ((val) = ((packed) & (0xff))); \
+ } while (0);
+
+struct adie_codec_action_unit {
+ u32 type;
+ u32 action;
+};
+
+struct adie_codec_hwsetting_entry{
+ struct adie_codec_action_unit *actions;
+ u32 action_sz;
+ u32 freq_plan;
+ u32 osr;
+ /* u32 VolMask;
+ * u32 SidetoneMask;
+ */
+};
+
+struct adie_codec_dev_profile {
+ u32 path_type; /* RX or TX */
+ u32 setting_sz;
+ struct adie_codec_hwsetting_entry *settings;
+};
+
+struct adie_codec_register {
+ u8 reg;
+ u8 mask;
+ u8 val;
+};
+
+struct adie_codec_register_image {
+ struct adie_codec_register *regs;
+ u32 img_sz;
+};
+
+struct adie_codec_path;
+
+struct adie_codec_anc_data {
+ u32 size;
+ u32 writes[];
+};
+
+struct adie_codec_operations {
+ int codec_id;
+ int (*codec_open) (struct adie_codec_dev_profile *profile,
+ struct adie_codec_path **path_pptr);
+ int (*codec_close) (struct adie_codec_path *path_ptr);
+ int (*codec_setpath) (struct adie_codec_path *path_ptr,
+ u32 freq_plan, u32 osr);
+ int (*codec_proceed_stage) (struct adie_codec_path *path_ptr,
+ u32 state);
+ u32 (*codec_freq_supported) (struct adie_codec_dev_profile *profile,
+ u32 requested_freq);
+ int (*codec_enable_sidetone) (struct adie_codec_path *rx_path_ptr,
+ u32 enable);
+ int (*codec_enable_anc) (struct adie_codec_path *rx_path_ptr,
+ u32 enable, struct adie_codec_anc_data *calibration_writes);
+ int (*codec_set_device_digital_volume) (
+ struct adie_codec_path *path_ptr,
+ u32 num_channels,
+ u32 vol_percentage);
+
+ int (*codec_set_device_analog_volume) (struct adie_codec_path *path_ptr,
+ u32 num_channels,
+ u32 volume);
+ int (*codec_set_master_mode) (struct adie_codec_path *path_ptr,
+ u8 master);
+};
+
+int adie_codec_register_codec_operations(
+ const struct adie_codec_operations *codec_ops);
+int adie_codec_open(struct adie_codec_dev_profile *profile,
+ struct adie_codec_path **path_pptr);
+int adie_codec_setpath(struct adie_codec_path *path_ptr,
+ u32 freq_plan, u32 osr);
+int adie_codec_proceed_stage(struct adie_codec_path *path_ptr, u32 state);
+int adie_codec_close(struct adie_codec_path *path_ptr);
+u32 adie_codec_freq_supported(struct adie_codec_dev_profile *profile,
+ u32 requested_freq);
+int adie_codec_enable_sidetone(struct adie_codec_path *rx_path_ptr, u32 enable);
+int adie_codec_enable_anc(struct adie_codec_path *rx_path_ptr, u32 enable,
+ struct adie_codec_anc_data *calibration_writes);
+int adie_codec_set_device_digital_volume(struct adie_codec_path *path_ptr,
+ u32 num_channels, u32 vol_percentage /* in percentage */);
+
+int adie_codec_set_device_analog_volume(struct adie_codec_path *path_ptr,
+ u32 num_channels, u32 volume /* in percentage */);
+
+int adie_codec_set_master_mode(struct adie_codec_path *path_ptr, u8 master);
+#endif
diff --git a/original/linux/mfd/timpani-audio.h b/original/linux/mfd/timpani-audio.h
new file mode 100644
index 0000000..49fd49b
--- /dev/null
+++ b/original/linux/mfd/timpani-audio.h
@@ -0,0 +1,5016 @@
+#ifndef __LINUX_MFD_TIMPANI_AUDIO_H
+#define __LINUX_MFD_TIMPANI_AUDIO_H
+
+/*
+ * MREF
+ */
+#define TIMPANI_A_MREF (0x3)
+#define TIMPANI_MREF_RWC "RW"
+#define TIMPANI_MREF_POR 0xe2
+#define TIMPANI_MREF_S 0
+#define TIMPANI_MREF_M 0xFF
+
+#define TIMPANI_MREF_MREF_BG_EN_S 7
+#define TIMPANI_MREF_MREF_BG_EN_M 0x80
+#define TIMPANI_MREF_MREF_BG_EN_ENABLE 0x0
+#define TIMPANI_MREF_MREF_BG_EN_DISABLE 0x1
+
+#define TIMPANI_MREF_MREF_BG_REF_CUR_EN_S 6
+#define TIMPANI_MREF_MREF_BG_REF_CUR_EN_M 0x40
+#define TIMPANI_MREF_MREF_BG_REF_CUR_EN_ENABLE_NORMAL_OP 0x0
+#define TIMPANI_MREF_MREF_BG_REF_CUR_EN_DISABLE 0x1
+
+#define TIMPANI_MREF_MREF_200K_MODE_EN_S 5
+#define TIMPANI_MREF_MREF_200K_MODE_EN_M 0x20
+#define TIMPANI_MREF_MREF_200K_MODE_EN_ENABLE 0x0
+#define TIMPANI_MREF_MREF_200K_MODE_EN_DISABLE 0x1
+
+#define TIMPANI_MREF_MREF_PRE_CHARGE_EN_S 4
+#define TIMPANI_MREF_MREF_PRE_CHARGE_EN_M 0x10
+#define TIMPANI_MREF_MREF_PRE_CHARGE_EN_DISABLE 0x0
+#define TIMPANI_MREF_MREF_PRE_CHARGE_EN_ENABLE 0x1
+
+#define TIMPANI_MREF_MREF_100UA_CUR_CONN_S 3
+#define TIMPANI_MREF_MREF_100UA_CUR_CONN_M 0x8
+#define TIMPANI_MREF_MREF_100UA_CUR_CONN_ON_CHIP_RESISTOR_NORMAL_OP 0x0
+#define TIMPANI_MREF_MREF_100UA_CUR_CONN_ATEST 0x1
+
+#define TIMPANI_MREF_MREF_PTAT_CURRENT_S 2
+#define TIMPANI_MREF_MREF_PTAT_CURRENT_M 0x4
+#define TIMPANI_MREF_MREF_PTAT_CURRENT_V_10UA_PTAT_NORMAL_OP 0x0
+#define TIMPANI_MREF_MREF_PTAT_CURRENT_V_5UA_PTAT_BIAS_CURRENT 0x1
+
+#define TIMPANI_MREF_MREF_400K_MODE_EN_S 1
+#define TIMPANI_MREF_MREF_400K_MODE_EN_M 0x2
+#define TIMPANI_MREF_MREF_400K_MODE_EN_ENABLE 0x0
+#define TIMPANI_MREF_MREF_400K_MODE_EN_DISABLE 0x1
+
+#define TIMPANI_MREF_RESERVED_S 0
+#define TIMPANI_MREF_RESERVED_M 0x1
+
+
+/* For CDAC_IDAC_REF_CUR */
+#define TIMPANI_A_CDAC_IDAC_REF_CUR (0x4)
+#define TIMPANI_CDAC_IDAC_REF_CUR_RWC "RW"
+#define TIMPANI_CDAC_IDAC_REF_CUR_POR 0x8c
+#define TIMPANI_CDAC_IDAC_REF_CUR_S 0
+#define TIMPANI_CDAC_IDAC_REF_CUR_M 0xFF
+
+
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_S 5
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_M 0xE0
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_4UA 0x0
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_6UA 0x1
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_8UA 0x2
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_9UA 0x3
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_10UA_NORMAL_OP 0x4
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_11UA 0x5
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_13UA 0x6
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_15UA 0x7
+
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_S 2
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_M 0x1C
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_8_5UA 0x0
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_9_0UA 0x1
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_9_5UA 0x2
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_10_0UA_NORMAL_OP 0x3
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_10_5UA 0x4
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_11_0UA 0x5
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_11_5UA 0x6
+#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_12_0UA 0x7
+
+#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_S 0
+#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_M 0x3
+#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_2UA 0x0
+#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_3UA 0x1
+#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_5UA_NORMAL_OP 0x2
+#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_8UA 0x3
+
+
+/* -- For TXADC12_REF_CURR */
+#define TIMPANI_A_TXADC12_REF_CURR (0x5)
+#define TIMPANI_TXADC12_REF_CURR_RWC "RW"
+#define TIMPANI_TXADC12_REF_CURR_POR 0xa0
+#define TIMPANI_TXADC12_REF_CURR_S 0
+#define TIMPANI_TXADC12_REF_CURR_M 0xFF
+
+
+#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_S 6
+#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_M 0xC0
+#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_50UA 0x0
+#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_45UA 0x1
+#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_40UA_NORMAL_OP 0x2
+#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_35UA 0x3
+
+#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_S 4
+#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_M 0x30
+#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_50UA 0x0
+#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_45UA 0x1
+#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_40UA_NORMAL_OP 0x2
+#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_35UA 0x3
+
+#define TIMPANI_TXADC12_REF_CURR_RESERVED_S 0
+#define TIMPANI_TXADC12_REF_CURR_RESERVED_M 0xF
+
+
+/* -- For TXADC3_EN */
+#define TIMPANI_A_TXADC3_EN (0x9)
+#define TIMPANI_TXADC3_EN_RWC "RW"
+#define TIMPANI_TXADC3_EN_POR 0
+#define TIMPANI_TXADC3_EN_S 0
+#define TIMPANI_TXADC3_EN_M 0xFF
+
+
+#define TIMPANI_TXADC3_EN_TXADC3_REF_EN_S 7
+#define TIMPANI_TXADC3_EN_TXADC3_REF_EN_M 0x80
+#define TIMPANI_TXADC3_EN_TXADC3_REF_EN_DISABLE 0x0
+#define TIMPANI_TXADC3_EN_TXADC3_REF_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC3_EN_TXADC3_DAC_REF_CUR_COMPENSATION_EN_S 6
+#define TIMPANI_TXADC3_EN_TXADC3_DAC_REF_CUR_COMPENSATION_EN_M 0x40
+#define TIMPANI_TXADC3_EN_TXADC3_DAC_REF_CUR_COMPENSATION_EN_DISABLE 0x0
+#define TIMPANI_TXADC3_EN_TXADC3_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_S 5
+#define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_M 0x20
+#define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_DISABLE 0x0
+#define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC3_EN_TXADC3_OTA2_EN_S 4
+#define TIMPANI_TXADC3_EN_TXADC3_OTA2_EN_M 0x10
+#define TIMPANI_TXADC3_EN_TXADC3_OTA2_EN_DISABLE 0x0
+#define TIMPANI_TXADC3_EN_TXADC3_OTA2_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_S 3
+#define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_M 0x8
+#define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_DISABLE 0x0
+#define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_S 2
+#define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_M 0x4
+#define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_DISABLE 0x0
+#define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_S 1
+#define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_M 0x2
+#define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_DISABLE 0x0
+#define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC3_EN_RESERVED_S 0
+#define TIMPANI_TXADC3_EN_RESERVED_M 0x1
+
+
+/* -- For TXADC4_EN */
+#define TIMPANI_A_TXADC4_EN (0xA)
+#define TIMPANI_TXADC4_EN_RWC "RW"
+#define TIMPANI_TXADC4_EN_POR 0
+#define TIMPANI_TXADC4_EN_S 0
+#define TIMPANI_TXADC4_EN_M 0xFF
+
+
+#define TIMPANI_TXADC4_EN_TXADC4_REF_EN_S 7
+#define TIMPANI_TXADC4_EN_TXADC4_REF_EN_M 0x80
+#define TIMPANI_TXADC4_EN_TXADC4_REF_EN_DISABLE 0x0
+#define TIMPANI_TXADC4_EN_TXADC4_REF_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC4_EN_TXADC4_DAC_REF_CUR_COMPENSATION_EN_S 6
+#define TIMPANI_TXADC4_EN_TXADC4_DAC_REF_CUR_COMPENSATION_EN_M 0x40
+#define TIMPANI_TXADC4_EN_TXADC4_DAC_REF_CUR_COMPENSATION_EN_DISABLE 0x0
+#define TIMPANI_TXADC4_EN_TXADC4_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_S 5
+#define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_M 0x20
+#define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_DISABLE 0x0
+#define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC4_EN_TXADC4_OTA2_EN_S 4
+#define TIMPANI_TXADC4_EN_TXADC4_OTA2_EN_M 0x10
+#define TIMPANI_TXADC4_EN_TXADC4_OTA2_EN_DISABLE 0x0
+#define TIMPANI_TXADC4_EN_TXADC4_OTA2_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_S 3
+#define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_M 0x8
+#define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_DISABLE 0x0
+#define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_S 2
+#define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_M 0x4
+#define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_DISABLE 0x0
+#define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_S 1
+#define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_M 0x2
+#define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_DISABLE 0x0
+#define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC4_EN_RESERVED_S 0
+#define TIMPANI_TXADC4_EN_RESERVED_M 0x1
+
+
+/* -- For CODEC_TXADC_STATUS_REGISTER_1 */
+#define TIMPANI_A_CODEC_TXADC_STATUS_REGISTER_1 (0xB)
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_RWC "R"
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_POR 0
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_S 0
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_M 0xFF
+
+
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC1_DEM_ERROR_S 7
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC1_DEM_ERROR_M 0x80
+
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC2_DEM_ERROR_S 6
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC2_DEM_ERROR_M 0x40
+
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC3_DEM_ERROR_S 5
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC3_DEM_ERROR_M 0x20
+
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC4_DEM_ERROR_S 4
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC4_DEM_ERROR_M 0x10
+
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_RESERVED_S 0
+#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_RESERVED_M 0xF
+
+
+/* -- For TXFE1 */
+#define TIMPANI_A_TXFE1 (0xD)
+#define TIMPANI_TXFE1_RWC "RW"
+#define TIMPANI_TXFE1_POR 0
+#define TIMPANI_TXFE1_S 0
+#define TIMPANI_TXFE1_M 0xFF
+
+
+#define TIMPANI_TXFE1_TXFE1_EN_S 7
+#define TIMPANI_TXFE1_TXFE1_EN_M 0x80
+#define TIMPANI_TXFE1_TXFE1_EN_DISABLE 0x0
+#define TIMPANI_TXFE1_TXFE1_EN_ENABLE 0x1
+
+#define TIMPANI_TXFE1_TXFE1_GAIN_S 5
+#define TIMPANI_TXFE1_TXFE1_GAIN_M 0x60
+#define TIMPANI_TXFE1_TXFE1_GAIN_V_0DB 0x0
+#define TIMPANI_TXFE1_TXFE1_GAIN_V_4_5DB 0x1
+#define TIMPANI_TXFE1_TXFE1_GAIN_V_24DB_1 0x2
+#define TIMPANI_TXFE1_TXFE1_GAIN_V_24DB_2 0x3
+
+#define TIMPANI_TXFE1_TXFE1_IN_MIC1_CONN_S 4
+#define TIMPANI_TXFE1_TXFE1_IN_MIC1_CONN_M 0x10
+#define TIMPANI_TXFE1_TXFE1_IN_MIC1_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE1_TXFE1_IN_MIC1_CONN_CONNECT 0x1
+
+#define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_S 3
+#define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_M 0x8
+#define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_CONNECT 0x1
+
+#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_S 2
+#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_M 0x4
+#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_CONNECT 0x1
+
+#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_S 1
+#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_M 0x2
+#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_CONNECT 0x1
+
+#define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_S 0
+#define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_M 0x1
+#define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_CONNECT 0x1
+
+
+/* -- For TXFE2 */
+#define TIMPANI_A_TXFE2 (0xE)
+#define TIMPANI_TXFE2_RWC "RW"
+#define TIMPANI_TXFE2_POR 0
+#define TIMPANI_TXFE2_S 0
+#define TIMPANI_TXFE2_M 0xFF
+
+
+#define TIMPANI_TXFE2_TXFE2_EN_S 7
+#define TIMPANI_TXFE2_TXFE2_EN_M 0x80
+#define TIMPANI_TXFE2_TXFE2_EN_DISABLE 0x0
+#define TIMPANI_TXFE2_TXFE2_EN_ENABLE 0x1
+
+#define TIMPANI_TXFE2_TXFE2_GAIN_S 5
+#define TIMPANI_TXFE2_TXFE2_GAIN_M 0x60
+#define TIMPANI_TXFE2_TXFE2_GAIN_V_0DB 0x0
+#define TIMPANI_TXFE2_TXFE2_GAIN_V_4_5DB 0x1
+#define TIMPANI_TXFE2_TXFE2_GAIN_V_24DB_1 0x2
+#define TIMPANI_TXFE2_TXFE2_GAIN_V_24DB_2 0x3
+
+#define TIMPANI_TXFE2_TXFE2_IN_MIC1_CONN_S 4
+#define TIMPANI_TXFE2_TXFE2_IN_MIC1_CONN_M 0x10
+#define TIMPANI_TXFE2_TXFE2_IN_MIC1_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE2_TXFE2_IN_MIC1_CONN_CONNECT 0x1
+
+#define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_S 3
+#define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_M 0x8
+#define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_CONNECT 0x1
+
+#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_S 2
+#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_M 0x4
+#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_CONNECT 0x1
+
+#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_S 1
+#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_M 0x2
+#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_CONNECT 0x1
+
+#define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_S 0
+#define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_M 0x1
+#define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_CONNECT 0x1
+
+
+/* -- For TXFE12_ATEST */
+#define TIMPANI_A_TXFE12_ATEST (0xF)
+#define TIMPANI_TXFE12_ATEST_RWC "RW"
+#define TIMPANI_TXFE12_ATEST_POR 0
+#define TIMPANI_TXFE12_ATEST_S 0
+#define TIMPANI_TXFE12_ATEST_M 0xFF
+
+
+#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_SHORT_TO_VICM_EN_S 7
+#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_SHORT_TO_VICM_EN_M 0x80
+#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_SHORT_TO_VICM_EN_DISABLE 0x0
+#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_SHORT_TO_VICM_EN_ENABLE 0x1
+
+#define TIMPANI_TXFE12_ATEST_TXFE1_BYPASS_EN_S 6
+#define TIMPANI_TXFE12_ATEST_TXFE1_BYPASS_EN_M 0x40
+#define TIMPANI_TXFE12_ATEST_TXFE1_BYPASS_EN_DISABLE 0x0
+#define TIMPANI_TXFE12_ATEST_TXFE1_BYPASS_EN_ENABLE 0x1
+
+#define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_S 5
+#define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_M 0x20
+#define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_CONNECT 0x1
+
+#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_ATEST_CONN_S 4
+#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_ATEST_CONN_M 0x10
+#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_ATEST_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_ATEST_CONN_CONNECT 0x1
+
+#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_S 3
+#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_M 0x8
+#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_DISABLE 0x0
+#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_ENABLE 0x1
+
+#define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_S 2
+#define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_M 0x4
+#define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_DISABLE 0x0
+#define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_ENABLE 0x1
+
+#define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_S 1
+#define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_M 0x2
+#define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_CONNECT 0x1
+
+#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_S 0
+#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_M 0x1
+#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_CONNECT 0x1
+
+
+/* -- For TXFE_CLT */
+#define TIMPANI_A_TXFE_CLT (0x10)
+#define TIMPANI_TXFE_CLT_RWC "RW"
+#define TIMPANI_TXFE_CLT_POR 0x68
+#define TIMPANI_TXFE_CLT_S 0
+#define TIMPANI_TXFE_CLT_M 0xFF
+
+
+#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_S 5
+#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_M 0xE0
+#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_125V 0x0
+#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_100V 0x1
+#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_075V 0x2
+#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_050V_NORMAL_OP 0x3
+#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_025V 0x4
+#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_000V 0x5
+#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_0_975V 0x6
+#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_0_950V 0x7
+
+#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_S 3
+#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_M 0x18
+#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_3UA 0x0
+#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_4UA_NORMAL_OP 0x1
+#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_6UA 0x2
+#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_8UA 0x3
+
+#define TIMPANI_TXFE_CLT_RESERVED_S 0
+#define TIMPANI_TXFE_CLT_RESERVED_M 0x7
+
+
+/* -- For TXADC1_EN */
+#define TIMPANI_A_TXADC1_EN (0x11)
+#define TIMPANI_TXADC1_EN_RWC "RW"
+#define TIMPANI_TXADC1_EN_POR 0
+#define TIMPANI_TXADC1_EN_S 0
+#define TIMPANI_TXADC1_EN_M 0xFF
+
+
+#define TIMPANI_TXADC1_EN_TXADC1_REF_EN_S 7
+#define TIMPANI_TXADC1_EN_TXADC1_REF_EN_M 0x80
+#define TIMPANI_TXADC1_EN_TXADC1_REF_EN_DISABLE 0x0
+#define TIMPANI_TXADC1_EN_TXADC1_REF_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC1_EN_TXADC1_DAC_REF_CUR_COMPENSATION_EN_S 6
+#define TIMPANI_TXADC1_EN_TXADC1_DAC_REF_CUR_COMPENSATION_EN_M 0x40
+#define TIMPANI_TXADC1_EN_TXADC1_DAC_REF_CUR_COMPENSATION_EN_DISABLE 0x0
+#define TIMPANI_TXADC1_EN_TXADC1_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_S 5
+#define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_M 0x20
+#define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_DISABLE 0x0
+#define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC1_EN_TXADC1_OTA2_EN_S 4
+#define TIMPANI_TXADC1_EN_TXADC1_OTA2_EN_M 0x10
+#define TIMPANI_TXADC1_EN_TXADC1_OTA2_EN_DISABLE 0x0
+#define TIMPANI_TXADC1_EN_TXADC1_OTA2_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_S 3
+#define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_M 0x8
+#define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_DISABLE 0x0
+#define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_S 2
+#define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_M 0x4
+#define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_DISABLE 0x0
+#define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_S 1
+#define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_M 0x2
+#define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_DISABLE 0x0
+#define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC1_EN_RESERVED_S 0
+#define TIMPANI_TXADC1_EN_RESERVED_M 0x1
+
+
+/* -- For TXADC2_EN */
+#define TIMPANI_A_TXADC2_EN (0x12)
+#define TIMPANI_TXADC2_EN_RWC "RW"
+#define TIMPANI_TXADC2_EN_POR 0
+#define TIMPANI_TXADC2_EN_S 0
+#define TIMPANI_TXADC2_EN_M 0xFF
+
+
+#define TIMPANI_TXADC2_EN_TXADC2_REF_EN_S 7
+#define TIMPANI_TXADC2_EN_TXADC2_REF_EN_M 0x80
+#define TIMPANI_TXADC2_EN_TXADC2_REF_EN_DISABLE 0x0
+#define TIMPANI_TXADC2_EN_TXADC2_REF_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC2_EN_TXADC2_DAC_REF_CUR_COMPENSATION_EN_S 6
+#define TIMPANI_TXADC2_EN_TXADC2_DAC_REF_CUR_COMPENSATION_EN_M 0x40
+#define TIMPANI_TXADC2_EN_TXADC2_DAC_REF_CUR_COMPENSATION_EN_DISABLE 0x0
+#define TIMPANI_TXADC2_EN_TXADC2_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_S 5
+#define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_M 0x20
+#define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_DISABLE 0x0
+#define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC2_EN_TXADC2_OTA2_EN_S 4
+#define TIMPANI_TXADC2_EN_TXADC2_OTA2_EN_M 0x10
+#define TIMPANI_TXADC2_EN_TXADC2_OTA2_EN_DISABLE 0x0
+#define TIMPANI_TXADC2_EN_TXADC2_OTA2_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_S 3
+#define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_M 0x8
+#define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_DISABLE 0x0
+#define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_S 2
+#define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_M 0x4
+#define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_DISABLE 0x0
+#define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_S 1
+#define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_M 0x2
+#define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_DISABLE 0x0
+#define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC2_EN_RESERVED_S 0
+#define TIMPANI_TXADC2_EN_RESERVED_M 0x1
+
+
+/* -- For TXADC_CTL */
+#define TIMPANI_A_TXADC_CTL (0x13)
+#define TIMPANI_TXADC_CTL_RWC "RW"
+#define TIMPANI_TXADC_CTL_POR 0x58
+#define TIMPANI_TXADC_CTL_S 0
+#define TIMPANI_TXADC_CTL_M 0xFF
+
+
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_S 6
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_M 0xC0
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_5UA 0x0
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_10UA_NORMAL_OP 0x1
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_15UA 0x2
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_20UA 0x3
+
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_S 4
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_M 0x30
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_40UA 0x0
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_80UA 0x1
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_120UA 0x2
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_160UA 0x3
+
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_S 2
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_M 0xC
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_8V 0x0
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_7V 0x1
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_6V_NORMAL_OP 0x2
+#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_5V 0x3
+
+#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_S 0
+#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_M 0x3
+#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_20UA_NORMAL_OP 0x0
+#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_40UA 0x1
+#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_80UA 0x2
+#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_160UA 0x3
+
+
+/* -- For TXADC_CTL2 */
+#define TIMPANI_A_TXADC_CTL2 (0x14)
+#define TIMPANI_TXADC_CTL2_RWC "RW"
+#define TIMPANI_TXADC_CTL2_POR 0x64
+#define TIMPANI_TXADC_CTL2_S 0
+#define TIMPANI_TXADC_CTL2_M 0xFF
+
+
+#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_S 6
+#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_M 0xC0
+#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_333MV 0x0
+#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_356MV_NORMAL_OP 0x1
+#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_378MV 0x2
+#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_400MV 0x3
+
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_S 4
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_M 0x30
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_50UA 0x0
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_100UA 0x1
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_200UA_NORMAL_OP 0x2
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_400UA 0x3
+
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_S 2
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_M 0xC
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_1V 0x0
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_15V_NORMAL_OP 0x1
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_2V 0x2
+#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_25V 0x3
+
+#define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_S 1
+#define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_M 0x2
+#define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_V_50UA_NORMAL_OP 0x0
+#define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_V_100UA 0x1
+
+#define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_S 0
+#define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_M 0x1
+#define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_DISABLE 0x0
+#define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_ENABLE_NORMAL_OP 0x1
+
+
+/* -- For TXADC_CTL3 */
+#define TIMPANI_A_TXADC_CTL3 (0x15)
+#define TIMPANI_TXADC_CTL3_RWC "RW"
+#define TIMPANI_TXADC_CTL3_POR 0x64
+#define TIMPANI_TXADC_CTL3_S 0
+#define TIMPANI_TXADC_CTL3_M 0xFF
+
+
+#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_S 6
+#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_M 0xC0
+#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_0_85V 0x0
+#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_0_90V_NORMAL_OP 0x1
+#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_0_95V 0x2
+#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_1_00V 0x3
+
+#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_S 4
+#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_M 0x30
+#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_10UA 0x0
+#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_15UA 0x1
+#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_20UA_NORMAL_OP 0x2
+#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_25UA 0x3
+
+#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_S 2
+#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_M 0xC
+#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_5UA 0x0
+#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_10UA_NORMAL_OP 0x1
+#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_15UA 0x2
+#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_20UA 0x3
+
+#define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_S 1
+#define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_M 0x2
+#define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_V_5UA_NORMAL_OP 0x0
+#define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_V_10UA 0x1
+
+#define TIMPANI_TXADC_CTL3_RESERVED_S 0
+#define TIMPANI_TXADC_CTL3_RESERVED_M 0x1
+
+
+/* -- For TXADC_CHOP_CTL */
+#define TIMPANI_A_TXADC_CHOP_CTL (0x16)
+#define TIMPANI_TXADC_CHOP_CTL_RWC "RW"
+#define TIMPANI_TXADC_CHOP_CTL_POR 0
+#define TIMPANI_TXADC_CHOP_CTL_S 0
+#define TIMPANI_TXADC_CHOP_CTL_M 0xFF
+
+
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_EN_S 7
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_EN_M 0x80
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_EN_DISABLE 0x0
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_EN_ENABLE 0x1
+
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_S 4
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_M 0x70
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_2_NORMAL_OP 0x0
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_4 0x1
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_8 0x2
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_16 0x3
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_32 0x4
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_64 0x5
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_128 0x6
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_256 0x7
+
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_S 3
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_M 0x8
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_NORMAL_OP 0x0
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_RESET_CHOP 0x1
+
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_S 2
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_M 0x4
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_FALLING_EDGE_CK1 0x0
+#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_FALLING_EDGE_CK2 0x1
+
+#define TIMPANI_TXADC_CHOP_CTL_RESERVED_S 0
+#define TIMPANI_TXADC_CHOP_CTL_RESERVED_M 0x3
+
+
+/* -- For TXFE3 */
+#define TIMPANI_A_TXFE3 (0x18)
+#define TIMPANI_TXFE3_RWC "RW"
+#define TIMPANI_TXFE3_POR 0
+#define TIMPANI_TXFE3_S 0
+#define TIMPANI_TXFE3_M 0xFF
+
+
+#define TIMPANI_TXFE3_TXFE3_EN_S 7
+#define TIMPANI_TXFE3_TXFE3_EN_M 0x80
+#define TIMPANI_TXFE3_TXFE3_EN_DISABLE 0x0
+#define TIMPANI_TXFE3_TXFE3_EN_ENABLE 0x1
+
+#define TIMPANI_TXFE3_TXFE3_GAIN_S 5
+#define TIMPANI_TXFE3_TXFE3_GAIN_M 0x60
+#define TIMPANI_TXFE3_TXFE3_GAIN_V_0DB 0x0
+#define TIMPANI_TXFE3_TXFE3_GAIN_V_4_5DB 0x1
+#define TIMPANI_TXFE3_TXFE3_GAIN_V_24DB_1 0x2
+#define TIMPANI_TXFE3_TXFE3_GAIN_V_24DB_2 0x3
+
+#define TIMPANI_TXFE3_RESERVED_1_S 2
+#define TIMPANI_TXFE3_RESERVED_1_M 0x1C
+
+#define TIMPANI_TXFE3_TXFE3_IN_CONN_S 1
+#define TIMPANI_TXFE3_TXFE3_IN_CONN_M 0x2
+#define TIMPANI_TXFE3_TXFE3_IN_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE3_TXFE3_IN_CONN_LINE_IN_L 0x1
+
+#define TIMPANI_TXFE3_RESERVED_2_S 0
+#define TIMPANI_TXFE3_RESERVED_2_M 0x1
+
+
+/* -- For TXFE4 */
+#define TIMPANI_A_TXFE4 (0x19)
+#define TIMPANI_TXFE4_RWC "RW"
+#define TIMPANI_TXFE4_POR 0
+#define TIMPANI_TXFE4_S 0
+#define TIMPANI_TXFE4_M 0xFF
+
+
+#define TIMPANI_TXFE4_TXFE4_EN_S 7
+#define TIMPANI_TXFE4_TXFE4_EN_M 0x80
+#define TIMPANI_TXFE4_TXFE4_EN_DISABLE 0x0
+#define TIMPANI_TXFE4_TXFE4_EN_ENABLE 0x1
+
+#define TIMPANI_TXFE4_TXFE4_GAIN_S 5
+#define TIMPANI_TXFE4_TXFE4_GAIN_M 0x60
+#define TIMPANI_TXFE4_TXFE4_GAIN_V_0DB 0x0
+#define TIMPANI_TXFE4_TXFE4_GAIN_V_4_5DB 0x1
+#define TIMPANI_TXFE4_TXFE4_GAIN_V_24DB_1 0x2
+#define TIMPANI_TXFE4_TXFE4_GAIN_V_24DB_2 0x3
+
+#define TIMPANI_TXFE4_RESERVED_1_S 2
+#define TIMPANI_TXFE4_RESERVED_1_M 0x1C
+
+#define TIMPANI_TXFE4_TXFE4_IN_CONN_S 1
+#define TIMPANI_TXFE4_TXFE4_IN_CONN_M 0x2
+#define TIMPANI_TXFE4_TXFE4_IN_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE4_TXFE4_IN_CONN_LINE_IN_R 0x1
+
+#define TIMPANI_TXFE4_RESERVED_2_S 0
+#define TIMPANI_TXFE4_RESERVED_2_M 0x1
+
+
+/* -- For TXFE3_ATEST */
+#define TIMPANI_A_TXFE3_ATEST (0x1A)
+#define TIMPANI_TXFE3_ATEST_RWC "RW"
+#define TIMPANI_TXFE3_ATEST_POR 0
+#define TIMPANI_TXFE3_ATEST_S 0
+#define TIMPANI_TXFE3_ATEST_M 0xFF
+
+
+#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_SHORT_TO_VICM_EN_S 7
+#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_SHORT_TO_VICM_EN_M 0x80
+#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_SHORT_TO_VICM_EN_DISABLE 0x0
+#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_SHORT_TO_VICM_EN_ENABLE 0x1
+
+#define TIMPANI_TXFE3_ATEST_TXFE3_BYPASS_EN_S 6
+#define TIMPANI_TXFE3_ATEST_TXFE3_BYPASS_EN_M 0x40
+#define TIMPANI_TXFE3_ATEST_TXFE3_BYPASS_EN_DISABLE 0x0
+#define TIMPANI_TXFE3_ATEST_TXFE3_BYPASS_EN_ENABLE 0x1
+
+#define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_S 5
+#define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_M 0x20
+#define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_CONNECT 0x1
+
+#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_ATEST_CONN_S 4
+#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_ATEST_CONN_M 0x10
+#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_ATEST_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_ATEST_CONN_CONNECT 0x1
+
+#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_S 3
+#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_M 0x8
+#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_DISABLE 0x0
+#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_ENABLE 0x1
+
+#define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_S 2
+#define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_M 0x4
+#define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_DISABLE 0x0
+#define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_ENABLE 0x1
+
+#define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_S 1
+#define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_M 0x2
+#define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_CONNECT 0x1
+
+#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_S 0
+#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_M 0x1
+#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_NO_CONNECT 0x0
+#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_CONNECT 0x1
+
+
+/* -- For TXFE_DIFF_SE */
+#define TIMPANI_A_TXFE_DIFF_SE (0x1B)
+#define TIMPANI_TXFE_DIFF_SE_RWC "RW"
+#define TIMPANI_TXFE_DIFF_SE_POR 0
+#define TIMPANI_TXFE_DIFF_SE_S 0
+#define TIMPANI_TXFE_DIFF_SE_M 0xFF
+
+
+#define TIMPANI_TXFE_DIFF_SE_RESERVED_S 4
+#define TIMPANI_TXFE_DIFF_SE_RESERVED_M 0xF0
+
+#define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_S 3
+#define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_M 0x8
+#define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_DIFF 0x0
+#define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_SINGLE_ENDED 0x1
+
+#define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_S 2
+#define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_M 0x4
+#define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_DIFF 0x0
+#define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_SINGLE_ENDED 0x1
+
+#define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_S 1
+#define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_M 0x2
+#define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_DIFF 0x0
+#define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_SINGLE_ENDED 0x1
+
+#define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_S 0
+#define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_M 0x1
+#define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_DIFF 0x0
+#define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_SINGLE_ENDED 0x1
+
+
+/* -- For CDAC_RX_CLK_CTL */
+#define TIMPANI_A_CDAC_RX_CLK_CTL (0x20)
+#define TIMPANI_CDAC_RX_CLK_CTL_RWC "RW"
+#define TIMPANI_CDAC_RX_CLK_CTL_POR 0x98
+#define TIMPANI_CDAC_RX_CLK_CTL_S 0
+#define TIMPANI_CDAC_RX_CLK_CTL_M 0xFF
+
+
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_EN_S 7
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_EN_M 0x80
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_EN_DISABLE 0x0
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_EN_ENABLE_NORMAL_OP 0x1
+
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_CTRL_EN_S 6
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_CTRL_EN_M 0x40
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_CTRL_EN_DISABLE_NORMAL_OP 0x0
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_CTRL_EN_ENABLE 0x1
+
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_S 2
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_M 0x3C
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_6NS 0x0
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_8_4NS 0x1
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_10_8NS 0x2
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_13_2NS 0x3
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_15_6NS 0x4
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_18NS 0x5
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_20_4NS_NORMAL_OP 0x6
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_22_8NS 0x7
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_25_2NS 0x8
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_27_6NS 0x9
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_30NS 0xA
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_32_4NS 0xB
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_34_8NS 0xC
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_37_2NS 0xD
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_39_6NS 0xE
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_42NS 0xF
+
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_S 1
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_M 0x2
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_ENABLE 0x1
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_DISABLE 0x0
+
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_S 0
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_M 0x1
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_NO_CONNECT 0x0
+#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_CONNECT 0x1
+
+
+/* -- For CDAC_BUFF_CTL */
+#define TIMPANI_A_CDAC_BUFF_CTL (0x21)
+#define TIMPANI_CDAC_BUFF_CTL_RWC "RW"
+#define TIMPANI_CDAC_BUFF_CTL_POR 0x60
+#define TIMPANI_CDAC_BUFF_CTL_S 0
+#define TIMPANI_CDAC_BUFF_CTL_M 0xFF
+
+
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_S 5
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_M 0xE0
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_40UA 0x0
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_60UA_NORMAL_OP 0x1
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_80UA 0x2
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_100UA 0x3
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_120UA 0x4
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_140UA 0x5
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_160UA 0x6
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_180UA 0x7
+
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_S 3
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_M 0x18
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_20UA 0x0
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_30UA_NORMAL_OP 0x1
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_40UA 0x2
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_50UA 0x3
+
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_S 1
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_M 0x6
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_5UA_5UA 0x0
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_5UA_10UA 0x1
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_10UA_5UA 0x2
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_10UA_10UA 0x3
+
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_S 0
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_M 0x1
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_CURRENT_TO_VCOM_NORMAL_OP 0x0
+#define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_MASTER_BIAS_TO_VCOM 0x1
+
+
+/* -- For CDAC_REF_CTL1 */
+#define TIMPANI_A_CDAC_REF_CTL1 (0x22)
+#define TIMPANI_CDAC_REF_CTL1_RWC "RW"
+#define TIMPANI_CDAC_REF_CTL1_POR 0xe1
+#define TIMPANI_CDAC_REF_CTL1_S 0
+#define TIMPANI_CDAC_REF_CTL1_M 0xFF
+
+
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_S 5
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_M 0xE0
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_8V 0x0
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_825V 0x1
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_85V 0x2
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_9V 0x3
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_925V 0x4
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_95V_NORMAL_OP 0x5
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_975 0x6
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_2_0V 0x7
+
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_S 2
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_M 0x1C
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_1V 0x0
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_125V 0x1
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_15V_NORMAL_OP 0x2
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_175V 0x3
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_2V 0x4
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_25V 0x5
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_275V 0x6
+#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_3V 0x7
+
+#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_S 0
+#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_M 0x3
+#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_025V 0x0
+#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_05V_NORMAL_OP 0x1
+#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_075V 0x2
+#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_1V 0x3
+
+
+/* -- For IDAC_DWA_FIR_CTL */
+#define TIMPANI_A_IDAC_DWA_FIR_CTL (0x23)
+#define TIMPANI_IDAC_DWA_FIR_CTL_RWC "RW"
+#define TIMPANI_IDAC_DWA_FIR_CTL_POR 0x28
+#define TIMPANI_IDAC_DWA_FIR_CTL_S 0
+#define TIMPANI_IDAC_DWA_FIR_CTL_M 0xFF
+
+
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_CLK_NON_OL_TIME_S 7
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_CLK_NON_OL_TIME_M 0x80
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_CLK_NON_OL_TIME_NORMAL_OP 0x0
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_CLK_NON_OL_TIME_V_150PSEC_REDUCTION 0x1
+
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_S 4
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_M 0x70
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR0 0x0
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR1 0x1
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR2 0x2
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR3 0x3
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR4 0x4
+
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_S 3
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_M 0x8
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_INTERNAL_NORMAL_OP 0x1
+#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_EXTERNAL 0x0
+
+#define TIMPANI_IDAC_DWA_FIR_CTL_RESERVED_S 0
+#define TIMPANI_IDAC_DWA_FIR_CTL_RESERVED_M 0x7
+
+
+/* -- For CDAC_REF_CTL2 */
+#define TIMPANI_A_CDAC_REF_CTL2 (0x24)
+#define TIMPANI_CDAC_REF_CTL2_RWC "RW"
+#define TIMPANI_CDAC_REF_CTL2_POR 0xc
+#define TIMPANI_CDAC_REF_CTL2_S 0
+#define TIMPANI_CDAC_REF_CTL2_M 0xFF
+
+
+#define TIMPANI_CDAC_REF_CTL2_RESERVED_1_S 7
+#define TIMPANI_CDAC_REF_CTL2_RESERVED_1_M 0x80
+
+#define TIMPANI_CDAC_REF_CTL2_CDAC_L_EN_S 6
+#define TIMPANI_CDAC_REF_CTL2_CDAC_L_EN_M 0x40
+#define TIMPANI_CDAC_REF_CTL2_CDAC_L_EN_DISABLE 0x0
+#define TIMPANI_CDAC_REF_CTL2_CDAC_L_EN_ENABLE 0x1
+
+#define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_S 5
+#define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_M 0x20
+#define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_DISABLE 0x0
+#define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_ENABLE 0x1
+
+#define TIMPANI_CDAC_REF_CTL2_RESERVED_2_S 4
+#define TIMPANI_CDAC_REF_CTL2_RESERVED_2_M 0x10
+
+#define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_S 2
+#define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_M 0xC
+#define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_CLK_SYNC_CK11DBAR 0x1
+#define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_CLK_SYNC_CK21 0x3
+
+#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_S 0
+#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_M 0x3
+#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_V_256 0x0
+#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_V_128 0x1
+#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_V_64 0x3
+
+
+/* -- For CDAC_CTL1 */
+#define TIMPANI_A_CDAC_CTL1 (0x25)
+#define TIMPANI_CDAC_CTL1_RWC "RW"
+#define TIMPANI_CDAC_CTL1_POR 0xb
+#define TIMPANI_CDAC_CTL1_S 0
+#define TIMPANI_CDAC_CTL1_M 0xFF
+
+
+#define TIMPANI_CDAC_CTL1_RESERVED_S 6
+#define TIMPANI_CDAC_CTL1_RESERVED_M 0xC0
+
+#define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_S 5
+#define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_M 0x20
+#define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_DISABLE 0x0
+#define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_ENABLE 0x1
+
+#define TIMPANI_CDAC_CTL1_CDAC_R_OUT_SHORT_EN_S 4
+#define TIMPANI_CDAC_CTL1_CDAC_R_OUT_SHORT_EN_M 0x10
+#define TIMPANI_CDAC_CTL1_CDAC_R_OUT_SHORT_EN_DISABLE 0x0
+#define TIMPANI_CDAC_CTL1_CDAC_R_OUT_SHORT_EN_ENABLE 0x1
+
+#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_S 2
+#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_M 0xC
+#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_0V 0x0
+#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_025V 0x1
+#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_05V_NORMAL_OP 0x2
+#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_0752V 0x3
+
+#define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_S 1
+#define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_M 0x2
+#define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_DISABLE 0x0
+#define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_ENABLE_NORMAL_OP 0x1
+
+#define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_S 0
+#define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_M 0x1
+#define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_INTERNAL_NORMAL_OP 0x1
+#define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_EXTERNAL_REGISTER_RESET 0x0
+
+
+/* -- For CDAC_CTL2 */
+#define TIMPANI_A_CDAC_CTL2 (0x26)
+#define TIMPANI_CDAC_CTL2_RWC "RW"
+#define TIMPANI_CDAC_CTL2_POR 0xd0
+#define TIMPANI_CDAC_CTL2_S 0
+#define TIMPANI_CDAC_CTL2_M 0xFF
+
+
+#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_S 5
+#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_M 0xE0
+#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_10UA 0x0
+#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_8_75UA 0x1
+#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_7_5UA 0x2
+#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_6_25UA 0x3
+#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_5UA 0x4
+#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_3_75UA 0x5
+#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_2_5UA_NORMAL_OP 0x6
+#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_1_25UA 0x7
+
+#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_S 2
+#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_M 0x1C
+#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_10UA 0x0
+#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_8_75UA 0x1
+#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_7_5UA 0x2
+#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_6_25UA 0x3
+#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_5UA_NORMAL_OP 0x4
+#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_3_75UA 0x5
+#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_2_5UA 0x6
+#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_1_25UA 0x7
+
+#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_S 0
+#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_M 0x3
+#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_FS 0x0
+#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_FS_BY_8 0x1
+#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_FS_BY_16 0x2
+
+
+/* -- For IDAC_L_CTL */
+#define TIMPANI_A_IDAC_L_CTL (0x28)
+#define TIMPANI_IDAC_L_CTL_RWC "RW"
+#define TIMPANI_IDAC_L_CTL_POR 0xe
+#define TIMPANI_IDAC_L_CTL_S 0
+#define TIMPANI_IDAC_L_CTL_M 0xFF
+
+
+#define TIMPANI_IDAC_L_CTL_IDAC_L_EN_S 7
+#define TIMPANI_IDAC_L_CTL_IDAC_L_EN_M 0x80
+#define TIMPANI_IDAC_L_CTL_IDAC_L_EN_DISABLE 0x0
+#define TIMPANI_IDAC_L_CTL_IDAC_L_EN_ENABLE 0x1
+
+#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_S 5
+#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_M 0x60
+#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_GROUND 0x0
+#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_IBIAS_X_R_REF 0x1
+#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_BG_VOLTAGE_NORMAL_OP 0x2
+#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_VDD_BY_2 0x3
+
+#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_S 3
+#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_M 0x18
+#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_NEG_1_5DB 0x0
+#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_V_0_0DB_NORMAL_OP 0x1
+#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_POS_1_5DB 0x2
+#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_POS_3_0DB 0x3
+
+#define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_S 2
+#define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_M 0x4
+#define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_V_30K 0x0
+#define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_V_10K_NORMAL_OP 0x1
+
+#define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_S 1
+#define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_M 0x2
+#define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_ASYNCHRONOUSLY 0x0
+#define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_ENABLE_NORMAL_OP 0x1
+
+#define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_S 0
+#define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_M 0x1
+#define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_REPLICA_BIAS_NORMAL_OP 0x0
+#define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_SERVO_LOOP_BIAS 0x1
+
+
+/* -- For IDAC_R_CTL */
+#define TIMPANI_A_IDAC_R_CTL (0x29)
+#define TIMPANI_IDAC_R_CTL_RWC "RW"
+#define TIMPANI_IDAC_R_CTL_POR 0xe
+#define TIMPANI_IDAC_R_CTL_S 0
+#define TIMPANI_IDAC_R_CTL_M 0xFF
+
+
+#define TIMPANI_IDAC_R_CTL_IDAC_R_EN_S 7
+#define TIMPANI_IDAC_R_CTL_IDAC_R_EN_M 0x80
+#define TIMPANI_IDAC_R_CTL_IDAC_R_EN_DISABLED 0x0
+#define TIMPANI_IDAC_R_CTL_IDAC_R_EN_ENABLED 0x1
+
+#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_S 5
+#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_M 0x60
+#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_GROUND 0x0
+#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_IBIAS_X_R_REF 0x1
+#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_BG_VOLTAGE_NORMAL_OP 0x2
+#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_VDD_BY_2 0x3
+
+#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_S 3
+#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_M 0x18
+#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_NEG_1_5DB 0x0
+#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_V_0_0DB_NORMAL_OP 0x1
+#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_POS_1_5DB 0x2
+#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_POS_3_0DB 0x3
+
+#define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_S 2
+#define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_M 0x4
+#define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_V_30K 0x0
+#define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_V_10K_NORMAL_OP 0x1
+
+#define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_S 1
+#define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_M 0x2
+#define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_ASYNCHRONOUSLY 0x0
+#define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_ENABLE_NORMAL_OP 0x1
+
+#define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_S 0
+#define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_M 0x1
+#define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_REPLICA_BIAS_NORMAL_OP 0x0
+#define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_SERVO_LOOP_BIAS 0x1
+
+
+/* -- For PA_MASTER_BIAS */
+#define TIMPANI_A_PA_MASTER_BIAS (0x2D)
+#define TIMPANI_PA_MASTER_BIAS_RWC "RW"
+#define TIMPANI_PA_MASTER_BIAS_POR 0x6f
+#define TIMPANI_PA_MASTER_BIAS_S 0
+#define TIMPANI_PA_MASTER_BIAS_M 0xFF
+
+
+#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_S 5
+#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_M 0xE0
+#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_17_5UA 0x0
+#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_15_0UA 0x1
+#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_12_5UA 0x2
+#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_10_0UA 0x3
+#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_7_5UA 0x4
+#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_5_0UA 0x5
+#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_2_5UA 0x6
+#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_0_0UA 0x7
+
+#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_S 2
+#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_M 0x1C
+#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_17_5UA 0x0
+#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_15_0UA 0x1
+#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_12_5UA 0x2
+#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_10_0UA 0x3
+#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_7_5UA 0x4
+#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_5_0UA 0x5
+#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_2_5UA 0x6
+#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_0_0UA 0x7
+
+#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_S 0
+#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_M 0x3
+#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_6_25UA 0x0
+#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_5_0UA 0x1
+#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_3_75UA 0x2
+#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_2_5UA 0x3
+
+
+/* -- For PA_CLASSD_BIAS */
+#define TIMPANI_A_PA_CLASSD_BIAS (0x2E)
+#define TIMPANI_PA_CLASSD_BIAS_RWC "RW"
+#define TIMPANI_PA_CLASSD_BIAS_POR 0x55
+#define TIMPANI_PA_CLASSD_BIAS_S 0
+#define TIMPANI_PA_CLASSD_BIAS_M 0xFF
+
+
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_S 6
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_M 0xC0
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_V_6_25UA 0x0
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_V_5_0UA 0x1
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_V_3_75UA 0x2
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_V_2_5UA 0x3
+
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_S 4
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_M 0x30
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_6_25UA 0x0
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_5_0U 0x1
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_3_75UA 0x2
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_2_5UA 0x3
+
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_S 2
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_M 0xC
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_6_25UA 0x0
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_5_0UA 0x1
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_3_75UA 0x2
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_2_5UA 0x3
+
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_S 0
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_M 0x3
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_6_25UA 0x0
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_5_0UA 0x1
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_3_75UA 0x2
+#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_2_5UA 0x3
+
+
+/* -- For AUXPGA_CUR */
+#define TIMPANI_A_AUXPGA_CUR (0x2F)
+#define TIMPANI_AUXPGA_CUR_RWC "RW"
+#define TIMPANI_AUXPGA_CUR_POR 0x44
+#define TIMPANI_AUXPGA_CUR_S 0
+#define TIMPANI_AUXPGA_CUR_M 0xFF
+
+
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_S 4
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_M 0xF0
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0UA 0x0
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0_3125UA 0x1
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0_625UA 0x2
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0_9375UA 0x3
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_1_25UA 0x4
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_1_5625UA 0x5
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_1_875UA 0x6
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_2_1875UA 0x7
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_2_5UA 0x8
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_2_8125UA 0x9
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_3_125UA 0xA
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_3_4375UA 0xB
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_3_75UA 0xC
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_4_0625UA 0xD
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_4_375UA 0xE
+#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_4_6875UA 0xF
+
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_S 0
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_M 0xF
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0UA 0x0
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0_3125UA 0x1
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0_625UA 0x2
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0_9375UA 0x3
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_1_25UA 0x4
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_1_5625UA 0x5
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_1_875UA 0x6
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_2_1875UA 0x7
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_2_5UA 0x8
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_2_8125UA 0x9
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_3_125UA 0xA
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_3_4375UA 0xB
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_3_75UA 0xC
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_4_0625UA 0xD
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_4_375UA 0xE
+#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_4_6875UA 0xF
+
+
+/* -- For AUXPGA_CM */
+#define TIMPANI_A_AUXPGA_CM (0x30)
+#define TIMPANI_AUXPGA_CM_RWC "RW"
+#define TIMPANI_AUXPGA_CM_POR 0x92
+#define TIMPANI_AUXPGA_CM_S 0
+#define TIMPANI_AUXPGA_CM_M 0xFF
+
+
+#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_S 5
+#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_M 0xE0
+#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_7_5UA 0x0
+#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_7_925UA 0x1
+#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_8_75UA 0x2
+#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_9_375UA 0x3
+#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_10UA 0x4
+#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_10_625UA 0x5
+#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_11_25UA 0x6
+#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_11_875UA 0x7
+
+#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_S 2
+#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_M 0x1C
+#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_7_5UA 0x0
+#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_7_925UA 0x1
+#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_8_75UA 0x2
+#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_9_375UA 0x3
+#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_10UA 0x4
+#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_10_625UA 0x5
+#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_11_25UA 0x6
+#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_11_875UA 0x7
+
+#define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_S 1
+#define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_M 0x2
+#define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_VCMI_TO_R2R_CM 0x1
+#define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_R2R_CM_FLOATING 0x0
+
+#define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_S 0
+#define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_M 0x1
+#define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_GEN_VCM_LOCALLY 0x1
+#define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_BG_VCM 0x0
+
+
+/* -- For PA_HPH_EARPA_MSTB_EN */
+#define TIMPANI_A_PA_HPH_EARPA_MSTB_EN (0x31)
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_RWC "RW"
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_POR 0x4
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_S 0
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_M 0xFF
+
+
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_EN_S 7
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_EN_M 0x80
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_EN_DISABLE 0x0
+
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_BIAS_EN_S 6
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_BIAS_EN_M 0x40
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_BIAS_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_BIAS_EN_DISABLE 0x0
+
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_S 5
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_M 0x20
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_DISABLE 0x0
+
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_BIAS_EN_S 4
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_BIAS_EN_M 0x10
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_BIAS_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_BIAS_EN_DISABLE 0x0
+
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_S 3
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_M 0x8
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_DISABLE 0x0
+
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_S 2
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_M 0x4
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_CAPLESS 0x1
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_LEGACY 0x0
+
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_S 1
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_M 0x2
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_DISABLE 0x0
+
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_S 0
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_M 0x1
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_DISABLE 0x0
+
+
+/* -- For PA_LINE_AUXO_EN */
+#define TIMPANI_A_PA_LINE_AUXO_EN (0x32)
+#define TIMPANI_PA_LINE_AUXO_EN_RWC "RW"
+#define TIMPANI_PA_LINE_AUXO_EN_POR 0
+#define TIMPANI_PA_LINE_AUXO_EN_S 0
+#define TIMPANI_PA_LINE_AUXO_EN_M 0xFF
+
+
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_EN_S 7
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_EN_M 0x80
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_EN_ENABLE 0x1
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_EN_DISABLE 0x0
+
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_BIAS_EN_S 6
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_BIAS_EN_M 0x40
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_BIAS_EN_ENABLE 0x1
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_BIAS_EN_DISABLE 0x0
+
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_S 5
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_M 0x20
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_ENABLE 0x1
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_DISABLE 0x0
+
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_BIAS_EN_S 4
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_BIAS_EN_M 0x10
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_BIAS_EN_ENABLE 0x1
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_BIAS_EN_DISABLE 0x0
+
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_S 3
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_M 0x8
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_ENABLE 0x1
+#define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_DISABLE 0x0
+
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_S 2
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_M 0x4
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_ENABLE 0x1
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_DISABLE 0x0
+
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_S 1
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_M 0x2
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_ENABLE 0x1
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_DISABLE 0x0
+
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_S 0
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_M 0x1
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_ENABLE 0x1
+#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_DISABLE 0x0
+
+
+/* -- For PA_CLASSD_AUXPGA_EN */
+#define TIMPANI_A_PA_CLASSD_AUXPGA_EN (0x33)
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_RWC "RW"
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_POR 0
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_S 0
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_M 0xFF
+
+
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_MUTE_S 7
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_MUTE_M 0x80
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_MUTE_MUTE 0x1
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_MUTE_UNMUTE 0x0
+
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_MUTE_S 6
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_MUTE_M 0x40
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_MUTE_MUTE 0x1
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_MUTE_UNMUTE 0x0
+
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_S 5
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_M 0x20
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_ENABLE 0x1
+
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_EN_S 4
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_EN_M 0x10
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_EN_ENABLE 0x1
+
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_S 3
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_M 0x8
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_ENABLE 0x1
+
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_S 2
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_M 0x4
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_ENABLE 0x1
+
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_S 1
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_M 0x2
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_ENABLE 0x1
+
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_S 0
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_M 0x1
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_ENABLE 0x1
+
+
+/* -- For PA_LINE_L_GAIN */
+#define TIMPANI_A_PA_LINE_L_GAIN (0x34)
+#define TIMPANI_PA_LINE_L_GAIN_RWC "RW"
+#define TIMPANI_PA_LINE_L_GAIN_POR 0xac
+#define TIMPANI_PA_LINE_L_GAIN_S 0
+#define TIMPANI_PA_LINE_L_GAIN_M 0xFF
+
+
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_S 2
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_M 0xFC
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_POS_1_5 0x0
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_POS_0_0 0x1
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_1_5 0x2
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_3_0 0x3
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_4_5 0x4
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_6_0 0x5
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_7_5 0x6
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_9_0 0x7
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_10_5 0x8
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_12_0 0x9
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_13_5 0xA
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_15_0 0xB
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_16_5 0xC
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_18_0 0xD
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_19_5 0xE
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_21_0 0xF
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_22_5 0x10
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_24_0 0x11
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_25_5 0x12
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_27_0 0x13
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_28_5 0x14
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_30_0 0x15
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_31_5 0x16
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_33_0 0x17
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_34_5 0x18
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_36_0 0x19
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_37_5 0x1A
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_39_0 0x1B
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_40_5 0x1C
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_42_0 0x1D
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_43_5 0x1E
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_45_0 0x1F
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_46_5 0x20
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_48_0 0x21
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_49_5 0x22
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_51_0 0x23
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_52_5 0x24
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_54_0 0x25
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_55_5 0x26
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_57_0 0x27
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_58_5 0x28
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_60_0 0x29
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_61_5 0x2A
+#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_63_0 0x2B
+
+#define TIMPANI_PA_LINE_L_GAIN_RESERVED_S 0
+#define TIMPANI_PA_LINE_L_GAIN_RESERVED_M 0x3
+
+
+/* -- For PA_LINE_R_GAIN */
+#define TIMPANI_A_PA_LINE_R_GAIN (0x35)
+#define TIMPANI_PA_LINE_R_GAIN_RWC "RW"
+#define TIMPANI_PA_LINE_R_GAIN_POR 0xac
+#define TIMPANI_PA_LINE_R_GAIN_S 0
+#define TIMPANI_PA_LINE_R_GAIN_M 0xFF
+
+
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_S 2
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_M 0xFC
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_POS_1_5 0x0
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_POS_0_0 0x1
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_1_5 0x2
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_3_0 0x3
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_4_5 0x4
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_6_0 0x5
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_7_5 0x6
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_9_0 0x7
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_10_5 0x8
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_12_0 0x9
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_13_5 0xA
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_15_0 0xB
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_16_5 0xC
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_18_0 0xD
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_19_5 0xE
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_21_0 0xF
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_22_5 0x10
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_24_0 0x11
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_25_5 0x12
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_27_0 0x13
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_28_5 0x14
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_30_0 0x15
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_31_5 0x16
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_33_0 0x17
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_34_5 0x18
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_36_0 0x19
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_37_5 0x1A
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_39_0 0x1B
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_40_5 0x1C
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_42_0 0x1D
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_43_5 0x1E
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_45_0 0x1F
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_46_5 0x20
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_48_0 0x21
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_49_5 0x22
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_51_0 0x23
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_52_5 0x24
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_54_0 0x25
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_55_5 0x26
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_57_0 0x27
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_58_5 0x28
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_60_0 0x29
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_61_5 0x2A
+#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_63_0 0x2B
+
+#define TIMPANI_PA_LINE_R_GAIN_RESERVED_S 0
+#define TIMPANI_PA_LINE_R_GAIN_RESERVED_M 0x3
+
+
+/* -- For PA_HPH_L_GAIN */
+#define TIMPANI_A_PA_HPH_L_GAIN (0x36)
+#define TIMPANI_PA_HPH_L_GAIN_RWC "RW"
+#define TIMPANI_PA_HPH_L_GAIN_POR 0xae
+#define TIMPANI_PA_HPH_L_GAIN_S 0
+#define TIMPANI_PA_HPH_L_GAIN_M 0xFF
+
+
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_S 2
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_M 0xFC
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_POS_1_5 0x0
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_POS_0_0 0x1
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_1_5 0x2
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_3_0 0x3
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_4_5 0x4
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_6_0 0x5
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_7_5 0x6
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_9_0 0x7
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_10_5 0x8
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_12_0 0x9
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_13_5 0xA
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_15_0 0xB
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_16_5 0xC
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_18_0 0xD
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_19_5 0xE
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_21_0 0xF
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_22_5 0x10
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_24_0 0x11
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_25_5 0x12
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_27_0 0x13
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_28_5 0x14
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_30_0 0x15
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_31_5 0x16
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_33_0 0x17
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_34_5 0x18
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_36_0 0x19
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_37_5 0x1A
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_39_0 0x1B
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_40_5 0x1C
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_42_0 0x1D
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_43_5 0x1E
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_45_0 0x1F
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_46_5 0x20
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_48_0 0x21
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_49_5 0x22
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_51_0 0x23
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_52_5 0x24
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_54_0 0x25
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_55_5 0x26
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_57_0 0x27
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_58_5 0x28
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_60_0 0x29
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_61_5 0x2A
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_63_0 0x2B
+
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_S 1
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_M 0x2
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_MUTE 0x1
+#define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_UNMUTE 0x0
+
+#define TIMPANI_PA_HPH_L_GAIN_RESERVED_S 0
+#define TIMPANI_PA_HPH_L_GAIN_RESERVED_M 0x1
+
+
+/* -- For PA_HPH_R_GAIN */
+#define TIMPANI_A_PA_HPH_R_GAIN (0x37)
+#define TIMPANI_PA_HPH_R_GAIN_RWC "RW"
+#define TIMPANI_PA_HPH_R_GAIN_POR 0xae
+#define TIMPANI_PA_HPH_R_GAIN_S 0
+#define TIMPANI_PA_HPH_R_GAIN_M 0xFF
+
+
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_S 2
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_M 0xFC
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_POS_1_5 0x0
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_POS_0_0 0x1
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_1_5 0x2
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_3_0 0x3
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_4_5 0x4
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_6_0 0x5
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_7_5 0x6
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_9_0 0x7
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_10_5 0x8
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_12_0 0x9
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_13_5 0xA
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_15_0 0xB
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_16_5 0xC
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_18_0 0xD
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_19_5 0xE
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_21_0 0xF
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_22_5 0x10
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_24_0 0x11
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_25_5 0x12
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_27_0 0x13
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_28_5 0x14
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_30_0 0x15
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_31_5 0x16
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_33_0 0x17
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_34_5 0x18
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_36_0 0x19
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_37_5 0x1A
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_39_0 0x1B
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_40_5 0x1C
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_42_0 0x1D
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_43_5 0x1E
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_45_0 0x1F
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_46_5 0x20
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_48_0 0x21
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_49_5 0x22
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_51_0 0x23
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_52_5 0x24
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_54_0 0x25
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_55_5 0x26
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_57_0 0x27
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_58_5 0x28
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_60_0 0x29
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_61_5 0x2A
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_63_0 0x2B
+
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_S 1
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_M 0x2
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_MUTE 0x1
+#define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_UNMUTE 0x0
+
+#define TIMPANI_PA_HPH_R_GAIN_RESERVED_S 0
+#define TIMPANI_PA_HPH_R_GAIN_RESERVED_M 0x1
+
+
+/* -- For AUXPGA_LR_GAIN */
+#define TIMPANI_A_AUXPGA_LR_GAIN (0x38)
+#define TIMPANI_AUXPGA_LR_GAIN_RWC "RW"
+#define TIMPANI_AUXPGA_LR_GAIN_POR 0xaa
+#define TIMPANI_AUXPGA_LR_GAIN_S 0
+#define TIMPANI_AUXPGA_LR_GAIN_M 0xFF
+
+
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_S 4
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_M 0xF0
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_30DB 0x0
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_27DB 0x1
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_24DB 0x2
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_21DB 0x3
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_18DB 0x4
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_15DB 0x5
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_12DB 0x6
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_9_0DB 0x7
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_6_0DB 0x8
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_3_0DB 0x9
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_0_0DB 0xA
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_3_0DB 0xB
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_6_0DB 0xC
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_9_0DB 0xD
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_12_0DB_1 0xE
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_12_0DB_2 0xF
+
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_S 0
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_M 0xF
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_30DB 0x0
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_27DB 0x1
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_24DB 0x2
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_21DB 0x3
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_18DB 0x4
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_15DB 0x5
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_12DB 0x6
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_9_0DB 0x7
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_6_0DB 0x8
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_3_0DB 0x9
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_0_0DB 0xA
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_3_0DB 0xB
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_6_0DB 0xC
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_9_0DB 0xD
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_12_0DB_1 0xE
+#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_12_0DB_2 0xF
+
+
+/* -- For PA_AUXO_EARPA_CONN */
+#define TIMPANI_A_PA_AUXO_EARPA_CONN (0x39)
+#define TIMPANI_PA_AUXO_EARPA_CONN_RWC "RW"
+#define TIMPANI_PA_AUXO_EARPA_CONN_POR 0
+#define TIMPANI_PA_AUXO_EARPA_CONN_S 0
+#define TIMPANI_PA_AUXO_EARPA_CONN_M 0xFF
+
+
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_AUXPGA_L_CONN_S 7
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_AUXPGA_L_CONN_M 0x80
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_AUXPGA_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_AUXPGA_L_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_IDAC_L_CONN_S 6
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_IDAC_L_CONN_M 0x40
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_IDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_IDAC_L_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_S 5
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_M 0x20
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_AUXO_EARPA_CONN_RESERVED_S 4
+#define TIMPANI_PA_AUXO_EARPA_CONN_RESERVED_M 0x10
+
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_S 3
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_M 0x8
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_V_3_52DB 0x1
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_V_2_02DB 0x0
+
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_S 2
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_M 0x4
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_S 1
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_M 0x2
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_S 0
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_M 0x1
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_CONNECT 0x1
+
+
+/* -- For PA_LINE_ST_CONN */
+#define TIMPANI_A_PA_LINE_ST_CONN (0x3A)
+#define TIMPANI_PA_LINE_ST_CONN_RWC "RW"
+#define TIMPANI_PA_LINE_ST_CONN_POR 0
+#define TIMPANI_PA_LINE_ST_CONN_S 0
+#define TIMPANI_PA_LINE_ST_CONN_M 0xFF
+
+
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_AUXPGA_L_CONN_S 7
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_AUXPGA_L_CONN_M 0x80
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_AUXPGA_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_AUXPGA_L_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_IDAC_L_CONN_S 6
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_IDAC_L_CONN_M 0x40
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_IDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_IDAC_L_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_S 5
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_M 0x20
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_AUXPGA_R_CONN_S 4
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_AUXPGA_R_CONN_M 0x10
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_AUXPGA_R_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_AUXPGA_R_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_S 3
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_M 0x8
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_S 2
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_M 0x4
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_S 0
+#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_M 0x3
+#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_NONE 0x0
+#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_V_1_25UA 0x1
+#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_V_2_5UA 0x2
+#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_V_3_75UA 0x3
+
+
+/* -- For PA_LINE_MONO_CONN */
+#define TIMPANI_A_PA_LINE_MONO_CONN (0x3B)
+#define TIMPANI_PA_LINE_MONO_CONN_RWC "RW"
+#define TIMPANI_PA_LINE_MONO_CONN_POR 0
+#define TIMPANI_PA_LINE_MONO_CONN_S 0
+#define TIMPANI_PA_LINE_MONO_CONN_M 0xFF
+
+
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_CONN_S 7
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_CONN_M 0x80
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_CONN_S 6
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_CONN_M 0x40
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_S 5
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_M 0x20
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_INV_CONN_S 4
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_INV_CONN_M 0x10
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_INV_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_INV_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_S 3
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_M 0x8
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_S 2
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_M 0x4
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_S 0
+#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_M 0x3
+#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_NONE 0x0
+#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_V_1_25UA 0x1
+#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_V_2_5UA 0x2
+#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_V_3_75UA 0x3
+
+
+/* -- For PA_HPH_ST_CONN */
+#define TIMPANI_A_PA_HPH_ST_CONN (0x3C)
+#define TIMPANI_PA_HPH_ST_CONN_RWC "RW"
+#define TIMPANI_PA_HPH_ST_CONN_POR 0
+#define TIMPANI_PA_HPH_ST_CONN_S 0
+#define TIMPANI_PA_HPH_ST_CONN_M 0xFF
+
+
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_AUXPGA_L_CONN_S 7
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_AUXPGA_L_CONN_M 0x80
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_AUXPGA_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_AUXPGA_L_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_IDAC_L_CONN_S 6
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_IDAC_L_CONN_M 0x40
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_IDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_IDAC_L_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_S 5
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_M 0x20
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_AUXPGA_R_CONN_S 4
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_AUXPGA_R_CONN_M 0x10
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_AUXPGA_R_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_AUXPGA_R_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_S 3
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_M 0x8
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_S 2
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_M 0x4
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_S 1
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_M 0x2
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_DISABLE 0x1
+#define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_ENABLE 0x0
+
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_S 0
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_M 0x1
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_DISABLE 0x1
+#define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_ENABLE 0x0
+
+
+/* -- For PA_HPH_MONO_CONN */
+#define TIMPANI_A_PA_HPH_MONO_CONN (0x3D)
+#define TIMPANI_PA_HPH_MONO_CONN_RWC "RW"
+#define TIMPANI_PA_HPH_MONO_CONN_POR 0
+#define TIMPANI_PA_HPH_MONO_CONN_S 0
+#define TIMPANI_PA_HPH_MONO_CONN_M 0xFF
+
+
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_CONN_S 7
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_CONN_M 0x80
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_CONN_S 6
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_CONN_M 0x40
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_S 5
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_M 0x20
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_INV_CONN_S 4
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_INV_CONN_M 0x10
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_INV_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_INV_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_S 3
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_M 0x8
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_S 2
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_M 0x4
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_HPH_MONO_CONN_RESERVED_S 0
+#define TIMPANI_PA_HPH_MONO_CONN_RESERVED_M 0x3
+
+
+/* -- For PA_CLASSD_CONN */
+#define TIMPANI_A_PA_CLASSD_CONN (0x3E)
+#define TIMPANI_PA_CLASSD_CONN_RWC "RW"
+#define TIMPANI_PA_CLASSD_CONN_POR 0
+#define TIMPANI_PA_CLASSD_CONN_S 0
+#define TIMPANI_PA_CLASSD_CONN_M 0xFF
+
+
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_CDAC_CONN_S 7
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_CDAC_CONN_M 0x80
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_CDAC_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_CDAC_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_IDAC_CONN_S 6
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_IDAC_CONN_M 0x40
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_IDAC_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_IDAC_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_S 5
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_M 0x20
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_NO_CONNECT 0x0
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_CONNECT 0x1
+
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_PA_MODE_S 4
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_PA_MODE_M 0x10
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_PA_MODE_MONO_DIFF 0x1
+#define TIMPANI_PA_CLASSD_CONN_CLASSD_PA_MODE_STEREO 0x0
+
+#define TIMPANI_PA_CLASSD_CONN_RESERVED_S 0
+#define TIMPANI_PA_CLASSD_CONN_RESERVED_M 0xF
+
+
+/* -- For PA_CNP_CTL */
+#define TIMPANI_A_PA_CNP_CTL (0x3F)
+#define TIMPANI_PA_CNP_CTL_RWC "RW"
+#define TIMPANI_PA_CNP_CTL_POR 0x07
+#define TIMPANI_PA_CNP_CTL_S 0
+#define TIMPANI_PA_CNP_CTL_M 0xFF
+
+
+#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_S 6
+#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_M 0xC0
+#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_1_75_NA 0x0
+#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_3_5_NA_NORMAL_OP 0x1
+#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_5_25_NA 0x2
+#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_10_NA 0x3
+
+#define TIMPANI_PA_CNP_CTL_RESERVED_S 4
+#define TIMPANI_PA_CNP_CTL_RESERVED_M 0x30
+
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_S 3
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_M 0x8
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_DISABLE 0x0
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_ENABLE 0x1
+
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_S 0
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_M 0x7
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_220_V 0x0
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_243_V 0x1
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_266_V 0x2
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_290_V 0x3
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_341_V 0x4
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_339_V 0x5
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_365_V 0x6
+#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_391_V 0x7
+
+
+/* -- For PA_CLASSD_L_CTL */
+#define TIMPANI_A_PA_CLASSD_L_CTL (0x40)
+#define TIMPANI_PA_CLASSD_L_CTL_RWC "RW"
+#define TIMPANI_PA_CLASSD_L_CTL_POR 0x08
+#define TIMPANI_PA_CLASSD_L_CTL_S 0
+#define TIMPANI_PA_CLASSD_L_CTL_M 0xFF
+
+
+#define TIMPANI_PA_CLASSD_L_CTL_RESERVED_S 6
+#define TIMPANI_PA_CLASSD_L_CTL_RESERVED_M 0xC0
+
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_S 5
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_M 0x20
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_NORMAL_OP 0x0
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_RESET_PA_LOGIC 0x1
+
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_INT_RESET_S 4
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_INT_RESET_M 0x10
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_INT_RESET_NORMAL_OP 0x0
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_INT_RESET_DISCHARGE_CAPS 0x1
+
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_S 2
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_M 0xC
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_GND 0x0
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_IBIAS_X_R_REF 0x1
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_BG_VOLTAGE 0x2
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_VDD_BY_2 0x3
+
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_S 1
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_M 0x2
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_NORMAL_OP 0x0
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_PA_OUT_TO_VDD 0x1
+
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_S 0
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_M 0x1
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_NORMAL_OP 0x0
+#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_PA_OUT_TO_GND 0x1
+
+
+/* -- For PA_CLASSD_R_CTL */
+#define TIMPANI_A_PA_CLASSD_R_CTL (0x41)
+#define TIMPANI_PA_CLASSD_R_CTL_RWC "RW"
+#define TIMPANI_PA_CLASSD_R_CTL_POR 0x08
+#define TIMPANI_PA_CLASSD_R_CTL_S 0
+#define TIMPANI_PA_CLASSD_R_CTL_M 0xFF
+
+
+#define TIMPANI_PA_CLASSD_R_CTL_RESERVED_S 6
+#define TIMPANI_PA_CLASSD_R_CTL_RESERVED_M 0xC0
+
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_S 5
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_M 0x20
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_NORMAL_OP 0x0
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_RESET_PA_LOGIC 0x1
+
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_INT_RESET_S 4
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_INT_RESET_M 0x10
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_INT_RESET_NORMAL_OP 0x0
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_INT_RESET_DISCHARGE_CAPS 0x1
+
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_S 2
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_M 0xC
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_GND 0x0
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_IBIAS_X_R_REF 0x1
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_BG_VOLTAGE 0x2
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_VDD_BY_2 0x3
+
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_S 1
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_M 0x2
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_NORMAL_OP 0x0
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_PA_OUT_TO_VDD 0x1
+
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_S 0
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_M 0x1
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_NORMAL_OP 0x0
+#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_PA_OUT_TO_GND 0x1
+
+
+/* -- For PA_CLASSD_INT2_CTL */
+#define TIMPANI_A_PA_CLASSD_INT2_CTL (0x42)
+#define TIMPANI_PA_CLASSD_INT2_CTL_RWC "RW"
+#define TIMPANI_PA_CLASSD_INT2_CTL_POR 0xb0
+#define TIMPANI_PA_CLASSD_INT2_CTL_S 0
+#define TIMPANI_PA_CLASSD_INT2_CTL_M 0xFF
+
+
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_S 6
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_M 0xC0
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_5_0PF 0x0
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_7_5PF 0x1
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_10PF 0x2
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_15PF 0x3
+
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_S 4
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_M 0x30
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_100K 0x0
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_150K 0x1
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_175K 0x2
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_200K 0x3
+
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_S 2
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_M 0xC
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_5_0PF 0x0
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_7_5PF 0x1
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_10PF 0x2
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_15PF 0x3
+
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_S 0
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_M 0x3
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_100K 0x0
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_150K 0x1
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_175K 0x2
+#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_200K 0x3
+
+
+/* -- For PA_HPH_L_OCP_CLK_CTL */
+#define TIMPANI_A_PA_HPH_L_OCP_CLK_CTL (0x43)
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_RWC "RW"
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_POR 0xf2
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_S 0
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_M 0xFF
+
+
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_DIV_2_EN_S 7
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_DIV_2_EN_M 0x80
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_DIV_2_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_DIV_2_EN_DISABLE 0x0
+
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_EN_S 6
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_EN_M 0x40
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_EN_DISABLE 0x0
+
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_S 4
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_M 0x30
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV2 0x0
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV4 0x1
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV6 0x2
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV8 0x3
+
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_S 3
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_M 0x8
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_CLK_FROM_CH_2 0x1
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_CLK_FROM_CH_1 0x0
+
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_S 2
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_M 0x4
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_DISABLE 0x0
+
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_S 0
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_M 0x3
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_4 0x0
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_8 0x1
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_12 0x2
+#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_16 0x3
+
+
+/* -- For PA_CLASSD_L_SW_CTL */
+#define TIMPANI_A_PA_CLASSD_L_SW_CTL (0x44)
+#define TIMPANI_PA_CLASSD_L_SW_CTL_RWC "RW"
+#define TIMPANI_PA_CLASSD_L_SW_CTL_POR 0x37
+#define TIMPANI_PA_CLASSD_L_SW_CTL_S 0
+#define TIMPANI_PA_CLASSD_L_SW_CTL_M 0xFF
+
+
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_S 6
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_M 0xC0
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_1 0x0
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_2 0x1
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_3 0x2
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_4 0x3
+
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_S 4
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_M 0x30
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_3_OF_6_UNITS 0x0
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_4_OF_6_UNITS 0x1
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_5_OF_6_UNITS 0x2
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_6_OF_6_UNITS 0x3
+
+#define TIMPANI_PA_CLASSD_L_SW_CTL_RESERVED_S 3
+#define TIMPANI_PA_CLASSD_L_SW_CTL_RESERVED_M 0x8
+
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_S 2
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_M 0x4
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_ENABLE 0x1
+
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_S 1
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_M 0x2
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_ENABLE 0x1
+
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_S 0
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_M 0x1
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_POWER_GROUND 0x0
+#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_RST_MIDPOINT 0x1
+
+/* -- For PA_CLASSD_L_OCP1 */
+#define TIMPANI_A_PA_CLASSD_L_OCP1 (0x45)
+#define TIMPANI_PA_CLASSD_L_OCP1_RWC "RW"
+#define TIMPANI_PA_CLASSD_L_OCP1_POR 0xff
+#define TIMPANI_PA_CLASSD_L_OCP1_S 0
+#define TIMPANI_PA_CLASSD_L_OCP1_M 0xFF
+
+
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_EN_S 7
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_EN_M 0x80
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_EN_ENABLE 0x1
+
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_LOCK_S 6
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_LOCK_M 0x40
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_LOCK_NEVER_LOCKS 0x0
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_LOCK_LOCKS 0x1
+
+#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_S 4
+#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_M 0x30
+#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_100MA_83_3MA_66_7MA_50MA 0x0
+#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_133MA_111MA_88_7MA_66_7MA 0x1
+#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_166MA_138MA_111MA_83_3MA 0x2
+#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_200MA_166MA_133MA_100MA 0x3
+
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_S 0
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_M 0xF
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_1 0x1
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_2 0x2
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_3 0x3
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_4 0x4
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_5 0x5
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_6 0x6
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_7 0x7
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_8 0x8
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_9 0x9
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_10 0xA
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_11 0xB
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_12 0xC
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_13 0xD
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_14 0xE
+#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_15 0xF
+
+/* -- For PA_CLASSD_L_OCP2 */
+#define TIMPANI_A_PA_CLASSD_L_OCP2 (0x46)
+#define TIMPANI_PA_CLASSD_L_OCP2_RWC "RW"
+#define TIMPANI_PA_CLASSD_L_OCP2_POR 0x77
+#define TIMPANI_PA_CLASSD_L_OCP2_S 0
+#define TIMPANI_PA_CLASSD_L_OCP2_M 0xFF
+
+
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_S 4
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_M 0xF0
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_255 0x0
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_511 0x1
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_767 0x2
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_1023 0x3
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_1279 0x4
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_1535 0x5
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_1791 0x6
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_2047 0x7
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_2303 0x8
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_2559 0x9
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_2815 0xA
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_3071 0xB
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_3327 0xC
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_3583 0xD
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_3839 0xE
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_4095 0xF
+
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_S 0
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_M 0xF
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_255 0x0
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_511 0x1
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_767 0x2
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_1023 0x3
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_1279 0x4
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_1535 0x5
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_1791 0x6
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_2047 0x7
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_2303 0x8
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_2559 0x9
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_2815 0xA
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_3071 0xB
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_3327 0xC
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_3583 0xD
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_3839 0xE
+#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_4095 0xF
+
+
+/* -- For PA_HPH_R_OCP_CLK_CTL */
+#define TIMPANI_A_PA_HPH_R_OCP_CLK_CTL (0x47)
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_RWC "RW"
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_POR 0xf2
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_S 0
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_M 0xFF
+
+
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_DIV_2_EN_S 7
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_DIV_2_EN_M 0x80
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_DIV_2_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_DIV_2_EN_DISABLE 0x0
+
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_EN_S 6
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_EN_M 0x40
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_EN_DISABLE 0x0
+
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_S 4
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_M 0x30
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV2 0x0
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV4 0x1
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV6 0x2
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV8 0x3
+
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_S 3
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_M 0x8
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_CLK_FROM_CH_2 0x1
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_CLK_FROM_CH_1 0x0
+
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_S 2
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_M 0x4
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_DISABLE 0x0
+
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_S 0
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_M 0x3
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_4 0x0
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_8 0x1
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_12 0x2
+#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_16 0x3
+
+
+/* -- For PA_CLASSD_R_SW_CTL */
+#define TIMPANI_A_PA_CLASSD_R_SW_CTL (0x48)
+#define TIMPANI_PA_CLASSD_R_SW_CTL_RWC "RW"
+#define TIMPANI_PA_CLASSD_R_SW_CTL_POR 0x37
+#define TIMPANI_PA_CLASSD_R_SW_CTL_S 0
+#define TIMPANI_PA_CLASSD_R_SW_CTL_M 0xFF
+
+
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_S 6
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_M 0xC0
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_1 0x0
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_2 0x1
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_3 0x2
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_4 0x3
+
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_S 4
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_M 0x30
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_3_OF_6_UNITS 0x0
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_4_OF_6_UNITS 0x1
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_5_OF_6_UNITS 0x2
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_6_OF_6_UNITS 0x3
+
+#define TIMPANI_PA_CLASSD_R_SW_CTL_RESERVED_S 3
+#define TIMPANI_PA_CLASSD_R_SW_CTL_RESERVED_M 0x8
+
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_S 2
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_M 0x4
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_ENABLE 0x1
+
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_S 1
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_M 0x2
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_ENABLE 0x1
+
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_S 0
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_M 0x1
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_POWER_GROUND 0x0
+#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_RST_MIDPOINT 0x1
+
+
+/* -- For PA_CLASSD_R_OCP1 */
+#define TIMPANI_A_PA_CLASSD_R_OCP1 (0x49)
+#define TIMPANI_PA_CLASSD_R_OCP1_RWC "RW"
+#define TIMPANI_PA_CLASSD_R_OCP1_POR 0xff
+#define TIMPANI_PA_CLASSD_R_OCP1_S 0
+#define TIMPANI_PA_CLASSD_R_OCP1_M 0xFF
+
+
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_EN_S 7
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_EN_M 0x80
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_EN_DISABLE 0x0
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_EN_ENABLE 0x1
+
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_LOCK_S 6
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_LOCK_M 0x40
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_LOCK_NEVER_LOCKS 0x0
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_LOCK_LOCKS 0x1
+
+#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_S 4
+#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_M 0x30
+#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_100MA_83_3MA_66_7MA_50MA 0x0
+#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_133MA_111MA_88_7MA_66_7MA 0x1
+#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_166MA_138MA_111MA_83_3MA 0x2
+#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_200MA_166MA_133MA_100MA 0x3
+
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_S 0
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_M 0xF
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_1 0x1
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_2 0x2
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_3 0x3
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_4 0x4
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_5 0x5
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_6 0x6
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_7 0x7
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_8 0x8
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_9 0x9
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_10 0xA
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_11 0xB
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_12 0xC
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_13 0xD
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_14 0xE
+#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_15 0xF
+
+
+/* -- For PA_CLASSD_R_OCP2 */
+#define TIMPANI_A_PA_CLASSD_R_OCP2 (0x4A)
+#define TIMPANI_PA_CLASSD_R_OCP2_RWC "RW"
+#define TIMPANI_PA_CLASSD_R_OCP2_POR 0x77
+#define TIMPANI_PA_CLASSD_R_OCP2_S 0
+#define TIMPANI_PA_CLASSD_R_OCP2_M 0xFF
+
+
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_S 4
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_M 0xF0
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_255 0x0
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_511 0x1
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_767 0x2
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_1023 0x3
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_1279 0x4
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_1535 0x5
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_1791 0x6
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_2047 0x7
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_2303 0x8
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_2559 0x9
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_2815 0xA
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_3071 0xB
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_3327 0xC
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_3583 0xD
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_3839 0xE
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_4095 0xF
+
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_S 0
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_M 0xF
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_255 0x0
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_511 0x1
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_767 0x2
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_1023 0x3
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_1279 0x4
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_1535 0x5
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_1791 0x6
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_2047 0x7
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_2303 0x8
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_2559 0x9
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_2815 0xA
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_3071 0xB
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_3327 0xC
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_3583 0xD
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_3839 0xE
+#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_4095 0xF
+
+
+/* -- For PA_HPH_CTL1 */
+#define TIMPANI_A_PA_HPH_CTL1 (0x4B)
+#define TIMPANI_PA_HPH_CTL1_RWC "RW"
+#define TIMPANI_PA_HPH_CTL1_POR 0x44
+#define TIMPANI_PA_HPH_CTL1_S 0
+#define TIMPANI_PA_HPH_CTL1_M 0xFF
+
+
+#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_S 4
+#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_M 0xF0
+#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_400PER 0x1
+#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_200PER 0x2
+#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_133PER 0x3
+#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_100PER 0x4
+#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_66PER 0x6
+#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_50PER 0x8
+#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_33PER 0xC
+
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_S 3
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_M 0x8
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_DISABLE 0x0
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_ENABLE 0x1
+
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_S 0
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_M 0x7
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_300MA 0x0
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_350MA 0x2
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_365MA 0x3
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_150MA 0x4
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_190MA 0x6
+#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_220MA 0x7
+
+
+/* -- For PA_HPH_CTL2 */
+#define TIMPANI_A_PA_HPH_CTL2 (0x4C)
+#define TIMPANI_PA_HPH_CTL2_RWC "RW"
+#define TIMPANI_PA_HPH_CTL2_POR 0xC8
+#define TIMPANI_PA_HPH_CTL2_S 0
+#define TIMPANI_PA_HPH_CTL2_M 0xFF
+
+
+#define TIMPANI_PA_HPH_CTL2_HPH_SW_VNEG_CTL_S 7
+#define TIMPANI_PA_HPH_CTL2_HPH_SW_VNEG_CTL_M 0x80
+#define TIMPANI_PA_HPH_CTL2_HPH_SW_VNEG_CTL_VNEG 0x1
+#define TIMPANI_PA_HPH_CTL2_HPH_SW_VNEG_CTL_VSS 0x0
+
+#define TIMPANI_PA_HPH_CTL2_HPH_VNEG_PS_GAIN_S 6
+#define TIMPANI_PA_HPH_CTL2_HPH_VNEG_PS_GAIN_M 0x40
+#define TIMPANI_PA_HPH_CTL2_HPH_VNEG_PS_GAIN_V_1_5 0x1
+#define TIMPANI_PA_HPH_CTL2_HPH_VNEG_PS_GAIN_V_2_5 0x0
+
+#define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_S 5
+#define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_M 0x20
+#define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_DISABLE 0x0
+
+#define TIMPANI_PA_HPH_CTL2_HPH_OCP_EN_S 4
+#define TIMPANI_PA_HPH_CTL2_HPH_OCP_EN_M 0x10
+#define TIMPANI_PA_HPH_CTL2_HPH_OCP_EN_ENABLE 0x1
+#define TIMPANI_PA_HPH_CTL2_HPH_OCP_EN_DISABLE 0x0
+
+#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_S 2
+#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_M 0xC
+#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_GROUND 0x0
+#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_IBIAS_ON_RESISTOR 0x1
+#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_BG 0x2
+#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_AVDD_BY_2 0x3
+
+#define TIMPANI_PA_HPH_CTL2_HPH_OUT_SHUNT_EN_S 1
+#define TIMPANI_PA_HPH_CTL2_HPH_OUT_SHUNT_EN_M 0x2
+#define TIMPANI_PA_HPH_CTL2_HPH_OUT_SHUNT_EN_DISABLE 0x0
+#define TIMPANI_PA_HPH_CTL2_HPH_OUT_SHUNT_EN_ENABLE 0x1
+
+#define TIMPANI_PA_HPH_CTL2_RESERVED_S 0
+#define TIMPANI_PA_HPH_CTL2_RESERVED_M 0x1
+
+
+/* -- For PA_LINE_AUXO_CTL */
+#define TIMPANI_A_PA_LINE_AUXO_CTL (0x4D)
+#define TIMPANI_PA_LINE_AUXO_CTL_RWC "RW"
+#define TIMPANI_PA_LINE_AUXO_CTL_POR 0x2
+#define TIMPANI_PA_LINE_AUXO_CTL_S 0
+#define TIMPANI_PA_LINE_AUXO_CTL_M 0xFF
+
+
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_S 6
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_M 0xC0
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_1_75NA 0x0
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_3_5NA 0x1
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_5_25NA 0x2
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_10NA 0x3
+
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_S 4
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_M 0x30
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_60UA 0x0
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_30UA_1 0x1
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_30UA_2 0x2
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_15UA 0x3
+
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_S 2
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_M 0xC
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_60UA 0x0
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_30UA_1 0x1
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_30UA_2 0x2
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_15UA 0x3
+
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_S 0
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_M 0x3
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_VSSA 0x0
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_BG 0x2
+#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_VDDA_BY_2 0x3
+
+
+/* -- For PA_AUXO_EARPA_CTL */
+#define TIMPANI_A_PA_AUXO_EARPA_CTL (0x4E)
+#define TIMPANI_PA_AUXO_EARPA_CTL_RWC "RW"
+#define TIMPANI_PA_AUXO_EARPA_CTL_POR 0xe
+#define TIMPANI_PA_AUXO_EARPA_CTL_S 0
+#define TIMPANI_PA_AUXO_EARPA_CTL_M 0xFF
+
+
+#define TIMPANI_PA_AUXO_EARPA_CTL_RESERVED_S 6
+#define TIMPANI_PA_AUXO_EARPA_CTL_RESERVED_M 0xC0
+
+#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_S 4
+#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_M 0x30
+#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_60UA 0x0
+#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_30UA 0x1
+#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_30UA_SAME_AS_01 0x2
+#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_15UA 0x3
+
+#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_S 3
+#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_M 0x8
+#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_NEG_4_5DB 0x1
+#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_NEG_3_0DB 0x0
+
+#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_S 1
+#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_M 0x6
+#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_12_5UA 0x0
+#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_10_0UA 0x1
+#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_7_5UA 0x2
+#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_5_0UA 0x3
+
+#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_S 0
+#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_M 0x1
+#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_BG 0x1
+#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_LOCAL_VCM 0x0
+
+
+/* -- For PA_EARO_CTL */
+#define TIMPANI_A_PA_EARO_CTL (0x4F)
+#define TIMPANI_PA_EARO_CTL_RWC "RW"
+#define TIMPANI_PA_EARO_CTL_POR 0x0
+#define TIMPANI_PA_EARO_CTL_S 0
+#define TIMPANI_PA_EARO_CTL_M 0xFF
+
+
+#define TIMPANI_PA_EARO_CTL_EARPA_STARTUP_S 7
+#define TIMPANI_PA_EARO_CTL_EARPA_STARTUP_M 0x80
+#define TIMPANI_PA_EARO_CTL_EARPA_STARTUP_NORMAL_OP 0x0
+#define TIMPANI_PA_EARO_CTL_EARPA_STARTUP_CONNECT_INPUTS_TO_GROUND 0x1
+
+#define TIMPANI_PA_EARO_CTL_EARPA_BYPASS_INPUT_CM_S 6
+#define TIMPANI_PA_EARO_CTL_EARPA_BYPASS_INPUT_CM_M 0x40
+#define TIMPANI_PA_EARO_CTL_EARPA_BYPASS_INPUT_CM_NO_BYPASS 0x0
+#define TIMPANI_PA_EARO_CTL_EARPA_BYPASS_INPUT_CM_BYPASS 0x1
+
+#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_S 3
+#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_M 0x38
+#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_213UA 0x0
+#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_280UA 0x1
+#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_408UA_1 0x2
+#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_780UA_1 0x3
+#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_408UA_2 0x4
+#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_530UA 0x5
+#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_780UA_2 0x6
+#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_1480UA 0x7
+
+#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_S 0
+#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_M 0x7
+#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_213UA 0x0
+#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_280UA 0x1
+#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_408UA_1 0x2
+#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_780UA_1 0x3
+#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_408UA_2 0x4
+#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_530UA 0x5
+#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_780UA_2 0x6
+#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_1480UA 0x7
+
+
+/* -- For PA_MASTER_BIAS_CUR */
+#define TIMPANI_A_PA_MASTER_BIAS_CUR (0x50)
+#define TIMPANI_PA_MASTER_BIAS_CUR_RWC "RW"
+#define TIMPANI_PA_MASTER_BIAS_CUR_POR 0xea
+#define TIMPANI_PA_MASTER_BIAS_CUR_S 0
+#define TIMPANI_PA_MASTER_BIAS_CUR_M 0xFF
+
+
+#define TIMPANI_PA_MASTER_BIAS_CUR_RAMPGEN_MASTER_BIAS_CUR_S 7
+#define TIMPANI_PA_MASTER_BIAS_CUR_RAMPGEN_MASTER_BIAS_CUR_M 0x80
+#define TIMPANI_PA_MASTER_BIAS_CUR_RAMPGEN_MASTER_BIAS_CUR_V_2_5UA 0x1
+#define TIMPANI_PA_MASTER_BIAS_CUR_RAMPGEN_MASTER_BIAS_CUR_V_5UA 0x0
+
+#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_S 5
+#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_M 0x60
+#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_10UA 0x0
+#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_7_5UA 0x1
+#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_5_0UA 0x2
+#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_2_5UA 0x3
+
+#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_S 3
+#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_M 0x18
+#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_6_25UA 0x0
+#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_5_0UA 0x1
+#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_3_75UA 0x2
+#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_2_5UA 0x3
+
+#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_S 1
+#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_M 0x6
+#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_6_25UA 0x0
+#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_5_0UA 0x1
+#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_3_75UA 0x2
+#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_2_5UA 0x3
+
+#define TIMPANI_PA_MASTER_BIAS_CUR_RESERVED_S 0
+#define TIMPANI_PA_MASTER_BIAS_CUR_RESERVED_M 0x1
+
+
+/* -- For PA_CLASSD_SC_STATUS */
+#define TIMPANI_A_PA_CLASSD_SC_STATUS (0x51)
+#define TIMPANI_PA_CLASSD_SC_STATUS_RWC "R"
+#define TIMPANI_PA_CLASSD_SC_STATUS_POR 0
+#define TIMPANI_PA_CLASSD_SC_STATUS_S 0
+#define TIMPANI_PA_CLASSD_SC_STATUS_M 0xFF
+
+
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_SC_DET_S 7
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_SC_DET_M 0x80
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_SC_DET_NORMAL_OP 0x0
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_SC_DET_SC_DET 0x1
+
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_PWR_STAGE_HI_Z_S 6
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_PWR_STAGE_HI_Z_M 0x40
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_PWR_STAGE_HI_Z_NORMAL_OP 0x0
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_PWR_STAGE_HI_Z_POWER_STAGE_OFF 0x1
+
+#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_1_S 4
+#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_1_M 0x30
+
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_S 3
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_M 0x8
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_NORMAL_OP 0x0
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_SC_DET 0x1
+
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_S 2
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_M 0x4
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_NORMAL_OP 0x0
+#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_POWER_STAGE_OFF 0x1
+
+#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_2_S 1
+#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_2_M 0x2
+
+#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_S 0
+#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_M 0x1
+
+
+/* -- For PA_HPH_SC_STATUS */
+#define TIMPANI_A_PA_HPH_SC_STATUS (0x52)
+#define TIMPANI_PA_HPH_SC_STATUS_RWC "R"
+#define TIMPANI_PA_HPH_SC_STATUS_POR 0
+#define TIMPANI_PA_HPH_SC_STATUS_S 0
+#define TIMPANI_PA_HPH_SC_STATUS_M 0xFF
+
+
+#define TIMPANI_PA_HPH_SC_STATUS_HPH_L_SC_DET_S 7
+#define TIMPANI_PA_HPH_SC_STATUS_HPH_L_SC_DET_M 0x80
+#define TIMPANI_PA_HPH_SC_STATUS_HPH_L_SC_DET_NORMAL_OP 0x0
+#define TIMPANI_PA_HPH_SC_STATUS_HPH_L_SC_DET_SC_DET 0x1
+
+#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_1_S 4
+#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_1_M 0x70
+
+#define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_S 3
+#define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_M 0x8
+#define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_NORMAL_OP 0x0
+#define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_SC_DET 0x1
+
+#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_2_S 2
+#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_2_M 0x4
+
+#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_S 0
+#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_M 0x3
+
+
+/* -- For ATEST_EN */
+#define TIMPANI_A_ATEST_EN (0x53)
+#define TIMPANI_ATEST_EN_RWC "RW"
+#define TIMPANI_ATEST_EN_POR 0
+#define TIMPANI_ATEST_EN_S 0
+#define TIMPANI_ATEST_EN_M 0xFF
+
+
+#define TIMPANI_ATEST_EN_ATEST_EN_S 7
+#define TIMPANI_ATEST_EN_ATEST_EN_M 0x80
+#define TIMPANI_ATEST_EN_ATEST_EN_DISABLE 0x0
+#define TIMPANI_ATEST_EN_ATEST_EN_ENABLE 0x1
+
+#define TIMPANI_ATEST_EN_RESERVED_S 0
+#define TIMPANI_ATEST_EN_RESERVED_M 0x7F
+
+
+/* -- For ATEST_TSHKADC */
+#define TIMPANI_A_ATEST_TSHKADC (0x54)
+#define TIMPANI_ATEST_TSHKADC_RWC "RW"
+#define TIMPANI_ATEST_TSHKADC_POR 0
+#define TIMPANI_ATEST_TSHKADC_S 0
+#define TIMPANI_ATEST_TSHKADC_M 0xFF
+
+
+#define TIMPANI_ATEST_TSHKADC_RESERVED_S 4
+#define TIMPANI_ATEST_TSHKADC_RESERVED_M 0xF0
+
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_S 2
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_M 0xC
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_MUX1 0x1
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_MUX2 0x2
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_MUX3 0x3
+
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_S 0
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_M 0x3
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_MUX1 0x1
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_MUX2 0x2
+#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_MUX3 0x3
+
+
+/* -- For ATEST_TXADC13 */
+#define TIMPANI_A_ATEST_TXADC13 (0x55)
+#define TIMPANI_ATEST_TXADC13_RWC "RW"
+#define TIMPANI_ATEST_TXADC13_POR 0
+#define TIMPANI_ATEST_TXADC13_S 0
+#define TIMPANI_ATEST_TXADC13_M 0xFF
+
+
+#define TIMPANI_ATEST_TXADC13_RESERVED_S 7
+#define TIMPANI_ATEST_TXADC13_RESERVED_M 0x80
+
+#define TIMPANI_ATEST_TXADC13_ATEST_SEL_L_S 6
+#define TIMPANI_ATEST_TXADC13_ATEST_SEL_L_M 0x40
+#define TIMPANI_ATEST_TXADC13_ATEST_SEL_L_TXADC1 0x0
+#define TIMPANI_ATEST_TXADC13_ATEST_SEL_L_TXADC3 0x1
+
+#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_S 3
+#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_M 0x38
+#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_ICMP1_TO_ATEST1 0x1
+#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_IOTA2_TO_ATEST1 0x2
+#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_IOTA1_TO_ATEST1 0x3
+#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_VICM_TO_ATEST1 0x4
+#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_VTH_P_TO_ATEST1 0x5
+#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_VREFP_TO_ATEST1 0x6
+
+#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_S 0
+#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_M 0x7
+#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_IDACREF_TO_ATEST2 0x1
+#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_IB_10U_TO_ATEST2 0x2
+#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_VREFMID_TO_ATEST2 0x3
+#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_VOCM_TO_ATEST2 0x4
+#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_VTH_N_TO_ATEST2 0x5
+#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_VREFN_TO_ATEST2 0x6
+
+
+/* -- For ATEST_TXADC24 */
+#define TIMPANI_A_ATEST_TXADC24 (0x56)
+#define TIMPANI_ATEST_TXADC24_RWC "RW"
+#define TIMPANI_ATEST_TXADC24_POR 0
+#define TIMPANI_ATEST_TXADC24_S 0
+#define TIMPANI_ATEST_TXADC24_M 0xFF
+
+
+#define TIMPANI_ATEST_TXADC24_RESERVED_S 7
+#define TIMPANI_ATEST_TXADC24_RESERVED_M 0x80
+
+#define TIMPANI_ATEST_TXADC24_ATEST_SEL_R_S 6
+#define TIMPANI_ATEST_TXADC24_ATEST_SEL_R_M 0x40
+#define TIMPANI_ATEST_TXADC24_ATEST_SEL_R_TXADC1 0x0
+#define TIMPANI_ATEST_TXADC24_ATEST_SEL_R_TXADC3 0x1
+
+#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_S 3
+#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_M 0x38
+#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_ICMP1_TO_ATEST1 0x1
+#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_IOTA2_TO_ATEST1 0x2
+#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_IOTA1_TO_ATEST1 0x3
+#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_VICM_TO_ATEST1 0x4
+#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_VTH_P_TO_ATEST1 0x5
+#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_VREFP_TO_ATEST1 0x6
+
+#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_S 0
+#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_M 0x7
+#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_IDACREF_TO_ATEST2 0x1
+#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_IB_10U_TO_ATEST2 0x2
+#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_VREFMID_TO_ATEST2 0x3
+#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_VOCM_TO_ATEST2 0x4
+#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_VTH_N_TO_ATEST2 0x5
+#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_VREFN_TO_ATEST2 0x6
+
+
+/* -- For ATEST_AUXPGA */
+#define TIMPANI_A_ATEST_AUXPGA (0x57)
+#define TIMPANI_ATEST_AUXPGA_RWC "RW"
+#define TIMPANI_ATEST_AUXPGA_POR 0
+#define TIMPANI_ATEST_AUXPGA_S 0
+#define TIMPANI_ATEST_AUXPGA_M 0xFF
+
+
+#define TIMPANI_ATEST_AUXPGA_ATEST1_AUXPGA_INT_VCM_CONN_S 7
+#define TIMPANI_ATEST_AUXPGA_ATEST1_AUXPGA_INT_VCM_CONN_M 0x80
+#define TIMPANI_ATEST_AUXPGA_ATEST1_AUXPGA_INT_VCM_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_AUXPGA_ATEST1_AUXPGA_INT_VCM_CONN_CONNECT 0x1
+
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMI_VDD_CONN_S 6
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMI_VDD_CONN_M 0x40
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMI_VDD_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMI_VDD_CONN_CONNECT 0x1
+
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_S 5
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_M 0x20
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_CONNECT 0x1
+
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_R_CONN_S 4
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_R_CONN_M 0x10
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_R_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_R_CONN_CONNECT 0x1
+
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_S 3
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_M 0x8
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_CONNECT 0x1
+
+#define TIMPANI_ATEST_AUXPGA_RESERVED_S 0
+#define TIMPANI_ATEST_AUXPGA_RESERVED_M 0x7
+
+
+/* -- For ATEST_CDAC */
+#define TIMPANI_A_ATEST_CDAC (0x58)
+#define TIMPANI_ATEST_CDAC_RWC "RW"
+#define TIMPANI_ATEST_CDAC_POR 0
+#define TIMPANI_ATEST_CDAC_S 0
+#define TIMPANI_ATEST_CDAC_M 0xFF
+
+
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_IN_CONN_S 7
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_IN_CONN_M 0x80
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_IN_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_IN_CONN_CONNECT 0x1
+
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_OUT_CONN_S 6
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_OUT_CONN_M 0x40
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_OUT_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_OUT_CONN_CONNECT 0x1
+
+#define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_S 5
+#define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_M 0x20
+#define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_CONNECT 0x1
+
+#define TIMPANI_ATEST_CDAC_ATEST_FILTER_R_OUT_CONN_S 4
+#define TIMPANI_ATEST_CDAC_ATEST_FILTER_R_OUT_CONN_M 0x10
+#define TIMPANI_ATEST_CDAC_ATEST_FILTER_R_OUT_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_CDAC_ATEST_FILTER_R_OUT_CONN_CONNECT 0x1
+
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_S 2
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_M 0xC
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_TEST1 0x1
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_TEST2 0x2
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_TEST3 0x3
+
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_S 0
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_M 0x3
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_TEST1 0x1
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_TEST2 0x2
+#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_TEST3 0x3
+
+
+/* -- For ATEST_IDAC */
+#define TIMPANI_A_ATEST_IDAC (0x59)
+#define TIMPANI_ATEST_IDAC_RWC "RW"
+#define TIMPANI_ATEST_IDAC_POR 0
+#define TIMPANI_ATEST_IDAC_S 0
+#define TIMPANI_ATEST_IDAC_M 0xFF
+
+
+#define TIMPANI_ATEST_IDAC_ATEST1_LR_CONN_S 7
+#define TIMPANI_ATEST_IDAC_ATEST1_LR_CONN_M 0x80
+#define TIMPANI_ATEST_IDAC_ATEST1_LR_CONN_RIGHT 0x1
+#define TIMPANI_ATEST_IDAC_ATEST1_LR_CONN_LEFT 0x0
+
+#define TIMPANI_ATEST_IDAC_ATEST1_CONN_S 4
+#define TIMPANI_ATEST_IDAC_ATEST1_CONN_M 0x70
+#define TIMPANI_ATEST_IDAC_ATEST1_CONN_IDAC_NEG_OUT 0x7
+#define TIMPANI_ATEST_IDAC_ATEST1_CONN_CT_FILTER_POS_OUT 0x6
+#define TIMPANI_ATEST_IDAC_ATEST1_CONN_CT_FILTER_IBIAS 0x5
+#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_1 0x4
+#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_2 0x3
+#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_3 0x2
+#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_4 0x1
+#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_5 0x0
+
+#define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_S 3
+#define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_M 0x8
+#define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_RIGHT 0x1
+#define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_LEFT 0x0
+
+#define TIMPANI_ATEST_IDAC_ATEST2_CONN_S 0
+#define TIMPANI_ATEST_IDAC_ATEST2_CONN_M 0x7
+#define TIMPANI_ATEST_IDAC_ATEST2_CONN_IDAC_POS_OUT 0x7
+#define TIMPANI_ATEST_IDAC_ATEST2_CONN_CT_FILTER_NEG_OUT 0x6
+#define TIMPANI_ATEST_IDAC_ATEST2_CONN_IDAC_IBIAS 0x5
+#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_1 0x4
+#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_2 0x3
+#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_3 0x2
+#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_4 0x1
+#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_5 0x0
+
+
+/* -- For ATEST_PA1 */
+#define TIMPANI_A_ATEST_PA1 (0x5A)
+#define TIMPANI_ATEST_PA1_RWC "RW"
+#define TIMPANI_ATEST_PA1_POR 0
+#define TIMPANI_ATEST_PA1_S 0
+#define TIMPANI_ATEST_PA1_M 0xFF
+
+
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_FSV_NP_CONN_S 7
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_FSV_NP_CONN_M 0x80
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_FSV_NP_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_FSV_NP_CONN_EN 0x1
+
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_NCASC_NMIRR_CONN_S 6
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_NCASC_NMIRR_CONN_M 0x40
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_NCASC_NMIRR_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_NCASC_NMIRR_CONN_EN 0x1
+
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_S 5
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_M 0x20
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_EN 0x1
+
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_VCM_PTAIL1_CONN_S 4
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_VCM_PTAIL1_CONN_M 0x10
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_VCM_PTAIL1_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_VCM_PTAIL1_CONN_EN 0x1
+
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_S 3
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_M 0x8
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_EN 0x1
+
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_S 2
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_M 0x4
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_EN 0x1
+
+#define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_S 1
+#define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_M 0x2
+#define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_PASS 0x0
+#define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_GATE 0x1
+
+#define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_S 0
+#define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_M 0x1
+#define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_CONNECT 0x1
+
+
+/* -- For ATEST_CLASSD */
+#define TIMPANI_A_ATEST_CLASSD (0x5B)
+#define TIMPANI_ATEST_CLASSD_RWC "RW"
+#define TIMPANI_ATEST_CLASSD_POR 0
+#define TIMPANI_ATEST_CLASSD_S 0
+#define TIMPANI_ATEST_CLASSD_M 0xFF
+
+
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_S 4
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_M 0xF0
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_NO_CONNECT_1 0x0
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_SC_OCP 0x1
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_CDAC_CLK 0x2
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_POS_CDAC 0x3
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_BREAK_BEFORE_MAKE_OUT_CP 0x4
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_COMP_OUT 0x5
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_INT2_POS_OUT 0x6
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_INT1_POS_OUT 0x7
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_NO_CONNECT_2 0x8
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_SC_OCP_SIGNAL 0x9
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_CDAC_CLK 0xA
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_POS_CDAC 0xB
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_BREAK_BEFORE_MAKE_OUT_CP 0xC
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_COMP_OUT 0xD
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_INT2_POS_OUT 0xE
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_INT1_POS_OUT 0xF
+
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_S 0
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_M 0xF
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_NO_CONNECT_1 0x0
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_HI_Z_OCP 0x1
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_OCP_CLOCK 0x2
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_NEG_CDAC 0x3
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_BREAK_BEFORE_MAKE_OUT_CN 0x4
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_CM_BUFF_OUT 0x5
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_INT2_NEG_OUT 0x6
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_INT1_NEG_OUT 0x7
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_NO_CONNECT_2 0x8
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_HI_Z_OCP 0x9
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_OCP_CLOCK 0xA
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_NEGATIVE_CDAC 0xB
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_BREAK_BEFORE_MAKE_OUT_CN 0xC
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_CM_BUFF_OUT 0xD
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_INTR2_NEG_OUT 0xE
+#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_INT1_NEG_OUT 0xF
+
+
+/* -- For ATEST_LINEO_AUXO */
+#define TIMPANI_A_ATEST_LINEO_AUXO (0x5C)
+#define TIMPANI_ATEST_LINEO_AUXO_RWC "RW"
+#define TIMPANI_ATEST_LINEO_AUXO_POR 0
+#define TIMPANI_ATEST_LINEO_AUXO_S 0
+#define TIMPANI_ATEST_LINEO_AUXO_M 0xFF
+
+
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_EN_S 7
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_EN_M 0x80
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_EN_DISABLE 0x0
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_EN_ENABLE 0x1
+
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_VCM_CONN_S 6
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_VCM_CONN_M 0x40
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_VCM_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_VCM_CONN_CONNECT 0x1
+
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_S 5
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_M 0x20
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_EN 0x1
+
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NMOS_PMOS_CONN_S 4
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NMOS_PMOS_CONN_M 0x10
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NMOS_PMOS_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NMOS_PMOS_CONN_EN 01
+
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NREFIN_STG1OP_CONN_S 3
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NREFIN_STG1OP_CONN_M 0x8
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NREFIN_STG1OP_CONN_NO_CONNECT 0x0
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NREFIN_STG1OP_CONN_EN 01
+
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_S 2
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_M 0x4
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_DISABLE 0x0
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_EN 0x1
+
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_S 1
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_M 0x2
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_DISABLE 0x0
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_EN 0x1
+
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_S 0
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_M 0x1
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_DISABLE 0x0
+#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_EN 0x1
+
+
+/* -- For CDC_RESET_CTL */
+#define TIMPANI_A_CDC_RESET_CTL (0x80)
+#define TIMPANI_CDC_RESET_CTL_RWC "RW"
+#define TIMPANI_CDC_RESET_CTL_POR 0
+#define TIMPANI_CDC_RESET_CTL_S 0
+#define TIMPANI_CDC_RESET_CTL_M 0x7F
+
+
+#define TIMPANI_CDC_RESET_CTL_ARB_SOFT_RESET_S 6
+#define TIMPANI_CDC_RESET_CTL_ARB_SOFT_RESET_M 0x40
+
+#define TIMPANI_CDC_RESET_CTL_TX2_SOFT_RESET_R_S 5
+#define TIMPANI_CDC_RESET_CTL_TX2_SOFT_RESET_R_M 0x20
+
+#define TIMPANI_CDC_RESET_CTL_TX2_SOFT_RESET_L_S 4
+#define TIMPANI_CDC_RESET_CTL_TX2_SOFT_RESET_L_M 0x10
+
+#define TIMPANI_CDC_RESET_CTL_RX2_SOFT_RESET_S 3
+#define TIMPANI_CDC_RESET_CTL_RX2_SOFT_RESET_M 0x8
+
+#define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_R_S 2
+#define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_R_M 0x4
+
+#define TIMPANI_CDC_RESET_CTL_RX1_SOFT_RESET_S 1
+#define TIMPANI_CDC_RESET_CTL_RX1_SOFT_RESET_M 0x2
+
+#define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_L_S 0
+#define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_L_M 0x1
+
+
+/* -- For CDC_RX1_CTL */
+#define TIMPANI_A_CDC_RX1_CTL (0x81)
+#define TIMPANI_CDC_RX1_CTL_RWC "RW"
+#define TIMPANI_CDC_RX1_CTL_POR 0xc
+#define TIMPANI_CDC_RX1_CTL_S 0
+#define TIMPANI_CDC_RX1_CTL_M 0x3F
+
+
+#define TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_R_S 5
+#define TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_R_M 0x20
+
+#define TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_L_S 4
+#define TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_L_M 0x10
+
+#define TIMPANI_CDC_RX1_CTL_RX1_RATE_S 2
+#define TIMPANI_CDC_RX1_CTL_RX1_RATE_M 0xC
+#define TIMPANI_CDC_RX1_CTL_RX1_RATE_OSR_256 0x3
+#define TIMPANI_CDC_RX1_CTL_RX1_RATE_OSR_128 0x1
+#define TIMPANI_CDC_RX1_CTL_RX1_RATE_OSR_64 0x0
+
+#define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_S 1
+#define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_M 0x2
+#define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_BR_32 0x1
+#define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_BR_64 0x0
+
+#define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_S 0
+#define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_M 0x1
+#define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_MASTER 0x1
+#define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_SLAVE 0x0
+
+
+/* -- For CDC_TX_I2S_CTL */
+#define TIMPANI_A_CDC_TX_I2S_CTL (0x82)
+#define TIMPANI_CDC_TX_I2S_CTL_RWC "RW"
+#define TIMPANI_CDC_TX_I2S_CTL_POR 0xc
+#define TIMPANI_CDC_TX_I2S_CTL_S 0
+#define TIMPANI_CDC_TX_I2S_CTL_M 0x3F
+
+
+#define TIMPANI_CDC_TX_I2S_CTL_TX2_I2S_SD_OE_S 5
+#define TIMPANI_CDC_TX_I2S_CTL_TX2_I2S_SD_OE_M 0x20
+
+#define TIMPANI_CDC_TX_I2S_CTL_TX1_I2S_SD_OE_S 4
+#define TIMPANI_CDC_TX_I2S_CTL_TX1_I2S_SD_OE_M 0x10
+
+#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_S 2
+#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_M 0xC
+#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_OSR_256 0x3
+#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_OSR_128 0x1
+#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_OSR_64 0x0
+
+#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_S 1
+#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_M 0x2
+#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_BR_32 0x1
+#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_BR_64 0x0
+
+#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_S 0
+#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_M 0x1
+#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_MASTER 0x1
+#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_SLAVE 0x0
+
+
+/* -- For CDC_CH_CTL */
+#define TIMPANI_A_CDC_CH_CTL (0x83)
+#define TIMPANI_CDC_CH_CTL_RWC "RW"
+#define TIMPANI_CDC_CH_CTL_POR 0
+#define TIMPANI_CDC_CH_CTL_S 0
+#define TIMPANI_CDC_CH_CTL_M 0xFF
+
+
+#define TIMPANI_CDC_CH_CTL_TX2_EN_R_S 7
+#define TIMPANI_CDC_CH_CTL_TX2_EN_R_M 0x80
+
+#define TIMPANI_CDC_CH_CTL_TX2_EN_L_S 6
+#define TIMPANI_CDC_CH_CTL_TX2_EN_L_M 0x40
+
+#define TIMPANI_CDC_CH_CTL_RX2_EN_R_S 5
+#define TIMPANI_CDC_CH_CTL_RX2_EN_R_M 0x20
+
+#define TIMPANI_CDC_CH_CTL_RX2_EN_L_S 4
+#define TIMPANI_CDC_CH_CTL_RX2_EN_L_M 0x10
+
+#define TIMPANI_CDC_CH_CTL_TX1_EN_R_S 3
+#define TIMPANI_CDC_CH_CTL_TX1_EN_R_M 0x8
+
+#define TIMPANI_CDC_CH_CTL_TX1_EN_L_S 2
+#define TIMPANI_CDC_CH_CTL_TX1_EN_L_M 0x4
+
+#define TIMPANI_CDC_CH_CTL_RX1_EN_R_S 1
+#define TIMPANI_CDC_CH_CTL_RX1_EN_R_M 0x2
+
+#define TIMPANI_CDC_CH_CTL_RX1_EN_L_S 0
+#define TIMPANI_CDC_CH_CTL_RX1_EN_L_M 0x1
+
+
+/* -- For CDC_RX1LG */
+#define TIMPANI_A_CDC_RX1LG (0x84)
+#define TIMPANI_CDC_RX1LG_RWC "RW"
+#define TIMPANI_CDC_RX1LG_POR 0xac
+#define TIMPANI_CDC_RX1LG_S 0
+#define TIMPANI_CDC_RX1LG_M 0xFF
+
+
+#define TIMPANI_CDC_RX1LG_GAIN_S 0
+#define TIMPANI_CDC_RX1LG_GAIN_M 0xFF
+
+
+/* -- For CDC_RX1RG */
+#define TIMPANI_A_CDC_RX1RG (0x85)
+#define TIMPANI_CDC_RX1RG_RWC "RW"
+#define TIMPANI_CDC_RX1RG_POR 0xac
+#define TIMPANI_CDC_RX1RG_S 0
+#define TIMPANI_CDC_RX1RG_M 0xFF
+
+
+#define TIMPANI_CDC_RX1RG_GAIN_S 0
+#define TIMPANI_CDC_RX1RG_GAIN_M 0xFF
+
+
+/* -- For CDC_TX1LG */
+#define TIMPANI_A_CDC_TX1LG (0x86)
+#define TIMPANI_CDC_TX1LG_RWC "RW"
+#define TIMPANI_CDC_TX1LG_POR 0xac
+#define TIMPANI_CDC_TX1LG_S 0
+#define TIMPANI_CDC_TX1LG_M 0xFF
+
+
+#define TIMPANI_CDC_TX1LG_GAIN_S 0
+#define TIMPANI_CDC_TX1LG_GAIN_M 0xFF
+
+
+/* -- For CDC_TX1RG */
+#define TIMPANI_A_CDC_TX1RG (0x87)
+#define TIMPANI_CDC_TX1RG_RWC "RW"
+#define TIMPANI_CDC_TX1RG_POR 0xac
+#define TIMPANI_CDC_TX1RG_S 0
+#define TIMPANI_CDC_TX1RG_M 0xFF
+
+
+#define TIMPANI_CDC_TX1RG_GAIN_S 0
+#define TIMPANI_CDC_TX1RG_GAIN_M 0xFF
+
+
+/* -- For CDC_RX_PGA_TIMER */
+#define TIMPANI_A_CDC_RX_PGA_TIMER (0x88)
+#define TIMPANI_CDC_RX_PGA_TIMER_RWC "RW"
+#define TIMPANI_CDC_RX_PGA_TIMER_POR 0xff
+#define TIMPANI_CDC_RX_PGA_TIMER_S 0
+#define TIMPANI_CDC_RX_PGA_TIMER_M 0xFF
+
+
+#define TIMPANI_CDC_RX_PGA_TIMER_TIMER_VAL_S 0
+#define TIMPANI_CDC_RX_PGA_TIMER_TIMER_VAL_M 0xFF
+
+
+/* -- For CDC_TX_PGA_TIMER */
+#define TIMPANI_A_CDC_TX_PGA_TIMER (0x89)
+#define TIMPANI_CDC_TX_PGA_TIMER_RWC "RW"
+#define TIMPANI_CDC_TX_PGA_TIMER_POR 0xff
+#define TIMPANI_CDC_TX_PGA_TIMER_S 0
+#define TIMPANI_CDC_TX_PGA_TIMER_M 0xFF
+
+
+#define TIMPANI_CDC_TX_PGA_TIMER_TIMER_VAL_S 0
+#define TIMPANI_CDC_TX_PGA_TIMER_TIMER_VAL_M 0xFF
+
+
+/* -- For CDC_GCTL1 */
+#define TIMPANI_A_CDC_GCTL1 (0x8A)
+#define TIMPANI_CDC_GCTL1_RWC "RW"
+#define TIMPANI_CDC_GCTL1_POR 0x33
+#define TIMPANI_CDC_GCTL1_S 0
+#define TIMPANI_CDC_GCTL1_M 0xFF
+
+
+#define TIMPANI_CDC_GCTL1_TX1_PGA_UPDATE_R_S 7
+#define TIMPANI_CDC_GCTL1_TX1_PGA_UPDATE_R_M 0x80
+
+#define TIMPANI_CDC_GCTL1_TX1_PGA_UPDATE_L_S 6
+#define TIMPANI_CDC_GCTL1_TX1_PGA_UPDATE_L_M 0x40
+
+#define TIMPANI_CDC_GCTL1_TX1_PGA_MUTE_EN_R_S 5
+#define TIMPANI_CDC_GCTL1_TX1_PGA_MUTE_EN_R_M 0x20
+
+#define TIMPANI_CDC_GCTL1_TX1_PGA_MUTE_EN_L_S 4
+#define TIMPANI_CDC_GCTL1_TX1_PGA_MUTE_EN_L_M 0x10
+
+#define TIMPANI_CDC_GCTL1_RX1_PGA_UPDATE_R_S 3
+#define TIMPANI_CDC_GCTL1_RX1_PGA_UPDATE_R_M 0x8
+
+#define TIMPANI_CDC_GCTL1_RX1_PGA_UPDATE_L_S 2
+#define TIMPANI_CDC_GCTL1_RX1_PGA_UPDATE_L_M 0x4
+
+#define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_R_S 1
+#define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_R_M 0x2
+
+#define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_L_S 0
+#define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_L_M 0x1
+
+
+/* -- For CDC_TX1L_STG */
+#define TIMPANI_A_CDC_TX1L_STG (0x8B)
+#define TIMPANI_CDC_TX1L_STG_RWC "RW"
+#define TIMPANI_CDC_TX1L_STG_POR 0xac
+#define TIMPANI_CDC_TX1L_STG_S 0
+#define TIMPANI_CDC_TX1L_STG_M 0xFF
+
+
+#define TIMPANI_CDC_TX1L_STG_GAIN_S 0
+#define TIMPANI_CDC_TX1L_STG_GAIN_M 0xFF
+
+
+/* -- For CDC_ST_CTL */
+#define TIMPANI_A_CDC_ST_CTL (0x8C)
+#define TIMPANI_CDC_ST_CTL_RWC "RW"
+#define TIMPANI_CDC_ST_CTL_POR 0x55
+#define TIMPANI_CDC_ST_CTL_S 0
+#define TIMPANI_CDC_ST_CTL_M 0xFF
+
+
+#define TIMPANI_CDC_ST_CTL_TX2_R_SIDETONE_UPDATE_S 7
+#define TIMPANI_CDC_ST_CTL_TX2_R_SIDETONE_UPDATE_M 0x80
+
+#define TIMPANI_CDC_ST_CTL_TX2_R_SIDETONE_MUTE_EN_S 6
+#define TIMPANI_CDC_ST_CTL_TX2_R_SIDETONE_MUTE_EN_M 0x40
+
+#define TIMPANI_CDC_ST_CTL_TX2_L_SIDETONE_UPDATE_S 5
+#define TIMPANI_CDC_ST_CTL_TX2_L_SIDETONE_UPDATE_M 0x20
+
+#define TIMPANI_CDC_ST_CTL_TX2_L_SIDETONE_MUTE_EN_S 4
+#define TIMPANI_CDC_ST_CTL_TX2_L_SIDETONE_MUTE_EN_M 0x10
+
+#define TIMPANI_CDC_ST_CTL_TX1_R_SIDETONE_UPDATE_S 3
+#define TIMPANI_CDC_ST_CTL_TX1_R_SIDETONE_UPDATE_M 0x8
+
+#define TIMPANI_CDC_ST_CTL_TX1_R_SIDETONE_MUTE_EN_S 2
+#define TIMPANI_CDC_ST_CTL_TX1_R_SIDETONE_MUTE_EN_M 0x4
+
+#define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_UPDATE_S 1
+#define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_UPDATE_M 0x2
+
+#define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_MUTE_EN_S 0
+#define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_MUTE_EN_M 0x1
+
+
+/* -- For CDC_RX1L_DCOFFSET */
+#define TIMPANI_A_CDC_RX1L_DCOFFSET (0x8D)
+#define TIMPANI_CDC_RX1L_DCOFFSET_RWC "RW"
+#define TIMPANI_CDC_RX1L_DCOFFSET_POR 0
+#define TIMPANI_CDC_RX1L_DCOFFSET_S 0
+#define TIMPANI_CDC_RX1L_DCOFFSET_M 0xFF
+
+
+#define TIMPANI_CDC_RX1L_DCOFFSET_OFFSET_S 0
+#define TIMPANI_CDC_RX1L_DCOFFSET_OFFSET_M 0xFF
+
+
+/* -- For CDC_RX1R_DCOFFSET */
+#define TIMPANI_A_CDC_RX1R_DCOFFSET (0x8E)
+#define TIMPANI_CDC_RX1R_DCOFFSET_RWC "RW"
+#define TIMPANI_CDC_RX1R_DCOFFSET_POR 0
+#define TIMPANI_CDC_RX1R_DCOFFSET_S 0
+#define TIMPANI_CDC_RX1R_DCOFFSET_M 0xFF
+
+
+#define TIMPANI_CDC_RX1R_DCOFFSET_OFFSET_S 0
+#define TIMPANI_CDC_RX1R_DCOFFSET_OFFSET_M 0xFF
+
+
+/* -- For CDC_BYPASS_CTL1 */
+#define TIMPANI_A_CDC_BYPASS_CTL1 (0x8F)
+#define TIMPANI_CDC_BYPASS_CTL1_RWC "RW"
+#define TIMPANI_CDC_BYPASS_CTL1_POR 0x2
+#define TIMPANI_CDC_BYPASS_CTL1_S 0
+#define TIMPANI_CDC_BYPASS_CTL1_M 0xF
+
+
+#define TIMPANI_CDC_BYPASS_CTL1_DITHER_BP_S 3
+#define TIMPANI_CDC_BYPASS_CTL1_DITHER_BP_M 0x8
+
+#define TIMPANI_CDC_BYPASS_CTL1_DITHER_SHAPE_SEL_S 2
+#define TIMPANI_CDC_BYPASS_CTL1_DITHER_SHAPE_SEL_M 0x4
+
+#define TIMPANI_CDC_BYPASS_CTL1_DITHER_DLY_SEL_S 1
+#define TIMPANI_CDC_BYPASS_CTL1_DITHER_DLY_SEL_M 0x2
+
+#define TIMPANI_CDC_BYPASS_CTL1_RX1_HPF_BP_S 0
+#define TIMPANI_CDC_BYPASS_CTL1_RX1_HPF_BP_M 0x1
+
+
+/* -- For CDC_PDM_CONFIG */
+#define TIMPANI_A_CDC_PDM_CONFIG (0x90)
+#define TIMPANI_CDC_PDM_CONFIG_RWC "RW"
+#define TIMPANI_CDC_PDM_CONFIG_POR 0
+#define TIMPANI_CDC_PDM_CONFIG_S 0
+#define TIMPANI_CDC_PDM_CONFIG_M 0xF
+
+
+#define TIMPANI_CDC_PDM_CONFIG_PDM_SEL_S 0
+#define TIMPANI_CDC_PDM_CONFIG_PDM_SEL_M 0xF
+
+
+/* -- For CDC_TESTMODE1 */
+#define TIMPANI_A_CDC_TESTMODE1 (0x91)
+#define TIMPANI_CDC_TESTMODE1_RWC "RW"
+#define TIMPANI_CDC_TESTMODE1_POR 0
+#define TIMPANI_CDC_TESTMODE1_S 0
+#define TIMPANI_CDC_TESTMODE1_M 0x3F
+
+
+#define TIMPANI_CDC_TESTMODE1_COMP_I2C_TEST_EN_S 5
+#define TIMPANI_CDC_TESTMODE1_COMP_I2C_TEST_EN_M 0x20
+
+#define TIMPANI_CDC_TESTMODE1_RX1_TEST_EN_R_S 4
+#define TIMPANI_CDC_TESTMODE1_RX1_TEST_EN_R_M 0x10
+
+#define TIMPANI_CDC_TESTMODE1_RX1_TEST_EN_L_S 3
+#define TIMPANI_CDC_TESTMODE1_RX1_TEST_EN_L_M 0x8
+
+#define TIMPANI_CDC_TESTMODE1_TX1_TEST_EN_R_S 2
+#define TIMPANI_CDC_TESTMODE1_TX1_TEST_EN_R_M 0x4
+
+#define TIMPANI_CDC_TESTMODE1_TX1_TEST_EN_L_S 1
+#define TIMPANI_CDC_TESTMODE1_TX1_TEST_EN_L_M 0x2
+
+#define TIMPANI_CDC_TESTMODE1_A_LOOPBACK_EN1_S 0
+#define TIMPANI_CDC_TESTMODE1_A_LOOPBACK_EN1_M 0x1
+
+
+/* -- For CDC_DMIC_CLK_CTL */
+#define TIMPANI_A_CDC_DMIC_CLK_CTL (0x92)
+#define TIMPANI_CDC_DMIC_CLK_CTL_RWC "RW"
+#define TIMPANI_CDC_DMIC_CLK_CTL_POR 0
+#define TIMPANI_CDC_DMIC_CLK_CTL_S 0
+#define TIMPANI_CDC_DMIC_CLK_CTL_M 0x3F
+
+
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_S 3
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_M 0x38
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_6 0x4
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_4 0x3
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_3 0x2
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_2 0x1
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_1 0x0
+
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_S 1
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_M 0x6
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_RX_MCLK2 0x2
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_RX_MCLK1 0x1
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_TX_MCLK 0x0
+
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_CLK_EN_S 0
+#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_CLK_EN_M 0x1
+
+
+/* -- For CDC_ADC12_CLK_CTL */
+#define TIMPANI_A_CDC_ADC12_CLK_CTL (0x93)
+#define TIMPANI_CDC_ADC12_CLK_CTL_RWC "RW"
+#define TIMPANI_CDC_ADC12_CLK_CTL_POR 0
+#define TIMPANI_CDC_ADC12_CLK_CTL_S 0
+#define TIMPANI_CDC_ADC12_CLK_CTL_M 0xFF
+
+
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_S 6
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_M 0xC0
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_RX_MCLK2 0x2
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_RX_MCLK1 0x1
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_TX_MCLK 0x0
+
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_S 3
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_M 0x38
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_6 0x4
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_4 0x3
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_3 0x2
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_2 0x1
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_1 0x0
+
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_S 0
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_M 0x7
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_6 0x4
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_4 0x3
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_3 0x2
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_2 0x1
+#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_1 0x0
+
+
+/* -- For CDC_TX1_CTL */
+#define TIMPANI_A_CDC_TX1_CTL (0x94)
+#define TIMPANI_CDC_TX1_CTL_RWC "RW"
+#define TIMPANI_CDC_TX1_CTL_POR 0x1b
+#define TIMPANI_CDC_TX1_CTL_S 0
+#define TIMPANI_CDC_TX1_CTL_M 0x3F
+
+
+#define TIMPANI_CDC_TX1_CTL_TX1_DMIC_SEL_R_S 5
+#define TIMPANI_CDC_TX1_CTL_TX1_DMIC_SEL_R_M 0x20
+
+#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_S 3
+#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_M 0x18
+#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_OSR_256 0x3
+#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_OSR_128 0x1
+#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_OSR_64 0x0
+
+#define TIMPANI_CDC_TX1_CTL_TX1_DMIC_SEL_L_S 2
+#define TIMPANI_CDC_TX1_CTL_TX1_DMIC_SEL_L_M 0x4
+
+#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_S 0
+#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_M 0x3
+#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_OSR_256 0x3
+#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_OSR_128 0x1
+#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_OSR_64 0x0
+
+
+/* -- For CDC_ADC34_CLK_CTL */
+#define TIMPANI_A_CDC_ADC34_CLK_CTL (0x95)
+#define TIMPANI_CDC_ADC34_CLK_CTL_RWC "RW"
+#define TIMPANI_CDC_ADC34_CLK_CTL_POR 0
+#define TIMPANI_CDC_ADC34_CLK_CTL_S 0
+#define TIMPANI_CDC_ADC34_CLK_CTL_M 0xFF
+
+
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_S 6
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_M 0xC0
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_RX_MCLK2 0x2
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_RX_MCLK1 0x1
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_TX_MCLK 0x0
+
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_S 3
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_M 0x38
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_6 0x4
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_4 0x3
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_3 0x2
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_2 0x1
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_1 0x0
+
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_S 0
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_M 0x7
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_6 0x4
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_4 0x3
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_3 0x2
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_2 0x1
+#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_1 0x0
+
+
+/* -- For CDC_TX2_CTL */
+#define TIMPANI_A_CDC_TX2_CTL (0x96)
+#define TIMPANI_CDC_TX2_CTL_RWC "RW"
+#define TIMPANI_CDC_TX2_CTL_POR 0x1b
+#define TIMPANI_CDC_TX2_CTL_S 0
+#define TIMPANI_CDC_TX2_CTL_M 0x3F
+
+
+#define TIMPANI_CDC_TX2_CTL_TX2_DMIC_SEL_R_S 5
+#define TIMPANI_CDC_TX2_CTL_TX2_DMIC_SEL_R_M 0x20
+
+#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_S 3
+#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_M 0x18
+#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_OSR_256 0x3
+#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_OSR_128 0x1
+#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_OSR_64 0x0
+
+#define TIMPANI_CDC_TX2_CTL_TX2_DMIC_SEL_L_S 2
+#define TIMPANI_CDC_TX2_CTL_TX2_DMIC_SEL_L_M 0x4
+
+#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_S 0
+#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_M 0x3
+#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_OSR_256 0x3
+#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_OSR_128 0x1
+#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_OSR_64 0x0
+
+
+/* -- For CDC_RX1_CLK_CTL */
+#define TIMPANI_A_CDC_RX1_CLK_CTL (0x97)
+#define TIMPANI_CDC_RX1_CLK_CTL_RWC "RW"
+#define TIMPANI_CDC_RX1_CLK_CTL_POR 0x1
+#define TIMPANI_CDC_RX1_CLK_CTL_S 0
+#define TIMPANI_CDC_RX1_CLK_CTL_M 0x1F
+
+
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_S 2
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_M 0x1C
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_6 0x4
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_4 0x3
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_3 0x2
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_2 0x1
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_1 0x0
+
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_S 0
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_M 0x3
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_RX_MCLK2 0x2
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_RX_MCLK1 0x1
+#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_TX_MCLK 0x0
+
+
+/* -- For CDC_RX2_CLK_CTL */
+#define TIMPANI_A_CDC_RX2_CLK_CTL (0x98)
+#define TIMPANI_CDC_RX2_CLK_CTL_RWC "RW"
+#define TIMPANI_CDC_RX2_CLK_CTL_POR 0x2
+#define TIMPANI_CDC_RX2_CLK_CTL_S 0
+#define TIMPANI_CDC_RX2_CLK_CTL_M 0x1F
+
+
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_S 2
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_M 0x1C
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_6 0x4
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_4 0x3
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_3 0x2
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_2 0x1
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_1 0x0
+
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_S 0
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_M 0x3
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_RX_MCLK2 0x2
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_RX_MCLK1 0x1
+#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_TX_MCLK 0x0
+
+
+/* -- For CDC_DEC_ADC_SEL */
+#define TIMPANI_A_CDC_DEC_ADC_SEL (0x99)
+#define TIMPANI_CDC_DEC_ADC_SEL_RWC "RW"
+#define TIMPANI_CDC_DEC_ADC_SEL_POR 0
+#define TIMPANI_CDC_DEC_ADC_SEL_S 0
+#define TIMPANI_CDC_DEC_ADC_SEL_M 0xFF
+
+
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_S 6
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_M 0xC0
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC4 0x3
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC3 0x2
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC2 0x1
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC1 0x0
+
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_S 4
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_M 0x30
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC4 0x3
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC3 0x2
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC2 0x1
+#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC1 0x0
+
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_S 2
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_M 0xC
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC4 0x3
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC3 0x2
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC2 0x1
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC1 0x0
+
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_S 0
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_M 0x3
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC4 0x3
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC3 0x2
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC2 0x1
+#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC1 0x0
+
+
+/* -- For CDC_ANC_INPUT_MUX */
+#define TIMPANI_A_CDC_ANC_INPUT_MUX (0x9A)
+#define TIMPANI_CDC_ANC_INPUT_MUX_RWC "RW"
+#define TIMPANI_CDC_ANC_INPUT_MUX_POR 0
+#define TIMPANI_CDC_ANC_INPUT_MUX_S 0
+#define TIMPANI_CDC_ANC_INPUT_MUX_M 0xFF
+
+
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_S 6
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_M 0xC0
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX2DOR 0x3
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX2DOL 0x2
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX1DOR 0x1
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX1DOL 0x0
+
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_S 4
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_M 0x30
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC2_DIN_R 0x3
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC2_DIN_L 0x2
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC1_DIN_R 0x1
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC1_DIN_L 0x0
+
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_S 2
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_M 0xC
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX2DOR 0x3
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX2DOL 0x2
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX1DOR 0x1
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX1DOL 0x0
+
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_S 0
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_M 0x3
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC2_DIN_R 0x3
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC2_DIN_L 0x2
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC1_DIN_R 0x1
+#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC1_DIN_L 0x0
+
+
+/* -- For CDC_ANC_RX_CLK_NS_SEL */
+#define TIMPANI_A_CDC_ANC_RX_CLK_NS_SEL (0x9B)
+#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_RWC "RW"
+#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_POR 0
+#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_S 0
+#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_M 0x1
+
+
+#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_ANC_RX_CLK_NS_SEL_S 0
+#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_ANC_RX_CLK_NS_SEL_M 0x1
+
+
+/* -- For CDC_ANC_FB_TUNE_SEL */
+#define TIMPANI_A_CDC_ANC_FB_TUNE_SEL (0x9C)
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_RWC "RW"
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_POR 0
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_S 0
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_M 0x3
+
+
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_S 1
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_M 0x2
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_FB_TUNE_EN 0x1
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_FB_TUNE_DIS 0x0
+
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_S 0
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_M 0x1
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_FB_TUNE_EN 0x1
+#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_FB_TUNE_DIS 0x0
+
+
+/* -- For CLK_DIV_SYNC_CTL */
+#define TIMPANI_A_CLK_DIV_SYNC_CTL (0x9E)
+#define TIMPANI_CLK_DIV_SYNC_CTL_RWC "RW"
+#define TIMPANI_CLK_DIV_SYNC_CTL_POR 0
+#define TIMPANI_CLK_DIV_SYNC_CTL_S 0
+#define TIMPANI_CLK_DIV_SYNC_CTL_M 0x3
+
+
+#define TIMPANI_CLK_DIV_SYNC_CTL_GLBL_DIV_SYNC_S 1
+#define TIMPANI_CLK_DIV_SYNC_CTL_GLBL_DIV_SYNC_M 0x2
+
+#define TIMPANI_CLK_DIV_SYNC_CTL_TX_DIV_SYNC_S 0
+#define TIMPANI_CLK_DIV_SYNC_CTL_TX_DIV_SYNC_M 0x1
+
+
+/* -- For CDC_ADC_CLK_EN */
+#define TIMPANI_A_CDC_ADC_CLK_EN (0x9F)
+#define TIMPANI_CDC_ADC_CLK_EN_RWC "RW"
+#define TIMPANI_CDC_ADC_CLK_EN_POR 0
+#define TIMPANI_CDC_ADC_CLK_EN_S 0
+#define TIMPANI_CDC_ADC_CLK_EN_M 0xF
+
+
+#define TIMPANI_CDC_ADC_CLK_EN_A_TX2_R_EN_S 3
+#define TIMPANI_CDC_ADC_CLK_EN_A_TX2_R_EN_M 0x8
+
+#define TIMPANI_CDC_ADC_CLK_EN_A_TX2_L_EN_S 2
+#define TIMPANI_CDC_ADC_CLK_EN_A_TX2_L_EN_M 0x4
+
+#define TIMPANI_CDC_ADC_CLK_EN_A_TX1_R_EN_S 1
+#define TIMPANI_CDC_ADC_CLK_EN_A_TX1_R_EN_M 0x2
+
+#define TIMPANI_CDC_ADC_CLK_EN_A_TX1_L_EN_S 0
+#define TIMPANI_CDC_ADC_CLK_EN_A_TX1_L_EN_M 0x1
+
+
+/* -- For CDC_ST_MIXING */
+#define TIMPANI_A_CDC_ST_MIXING (0xA0)
+#define TIMPANI_CDC_ST_MIXING_RWC "RW"
+#define TIMPANI_CDC_ST_MIXING_POR 0
+#define TIMPANI_CDC_ST_MIXING_S 0
+#define TIMPANI_CDC_ST_MIXING_M 0xF
+
+
+#define TIMPANI_CDC_ST_MIXING_TX2_R_S 3
+#define TIMPANI_CDC_ST_MIXING_TX2_R_M 0x8
+
+#define TIMPANI_CDC_ST_MIXING_TX2_L_S 2
+#define TIMPANI_CDC_ST_MIXING_TX2_L_M 0x4
+
+#define TIMPANI_CDC_ST_MIXING_TX1_R_S 1
+#define TIMPANI_CDC_ST_MIXING_TX1_R_M 0x2
+
+#define TIMPANI_CDC_ST_MIXING_TX1_L_S 0
+#define TIMPANI_CDC_ST_MIXING_TX1_L_M 0x1
+
+
+/* -- For CDC_RX2_CTL */
+#define TIMPANI_A_CDC_RX2_CTL (0xA1)
+#define TIMPANI_CDC_RX2_CTL_RWC "RW"
+#define TIMPANI_CDC_RX2_CTL_POR 0xc
+#define TIMPANI_CDC_RX2_CTL_S 0
+#define TIMPANI_CDC_RX2_CTL_M 0x3F
+
+
+#define TIMPANI_CDC_RX2_CTL_SIDETONE_EN2_R_S 5
+#define TIMPANI_CDC_RX2_CTL_SIDETONE_EN2_R_M 0x20
+
+#define TIMPANI_CDC_RX2_CTL_SIDETONE_EN2_L_S 4
+#define TIMPANI_CDC_RX2_CTL_SIDETONE_EN2_L_M 0x10
+
+#define TIMPANI_CDC_RX2_CTL_RX2_RATE_S 2
+#define TIMPANI_CDC_RX2_CTL_RX2_RATE_M 0xC
+#define TIMPANI_CDC_RX2_CTL_RX2_RATE_OSR_256 0x3
+#define TIMPANI_CDC_RX2_CTL_RX2_RATE_OSR_128 0x1
+#define TIMPANI_CDC_RX2_CTL_RX2_RATE_OSR_64 0x0
+
+#define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_S 1
+#define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_M 0x2
+#define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_BR_32 0x1
+#define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_BR_64 0x0
+
+#define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_S 0
+#define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_M 0x1
+#define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_MASTER 0x1
+#define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_SLAVE 0x0
+
+
+/* -- For CDC_ARB_CLK_EN */
+#define TIMPANI_A_CDC_ARB_CLK_EN (0xA2)
+#define TIMPANI_CDC_ARB_CLK_EN_RWC "RW"
+#define TIMPANI_CDC_ARB_CLK_EN_POR 0
+#define TIMPANI_CDC_ARB_CLK_EN_S 0
+#define TIMPANI_CDC_ARB_CLK_EN_M 0x1
+
+
+#define TIMPANI_CDC_ARB_CLK_EN_ARB_CLK_EN_S 0
+#define TIMPANI_CDC_ARB_CLK_EN_ARB_CLK_EN_M 0x1
+
+
+/* -- For CDC_I2S_CTL2 */
+#define TIMPANI_A_CDC_I2S_CTL2 (0xA3)
+#define TIMPANI_CDC_I2S_CTL2_RWC "RW"
+#define TIMPANI_CDC_I2S_CTL2_POR 0
+#define TIMPANI_CDC_I2S_CTL2_S 0
+#define TIMPANI_CDC_I2S_CTL2_M 0x3F
+
+
+#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_S 3
+#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_M 0x38
+#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_DMIC 0x4
+#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX2_R 0x3
+#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX2_L 0x2
+#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX1_R 0x1
+#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX1_L 0x0
+
+#define TIMPANI_CDC_I2S_CTL2_RX2_I2SCLK_EN_S 2
+#define TIMPANI_CDC_I2S_CTL2_RX2_I2SCLK_EN_M 0x4
+
+#define TIMPANI_CDC_I2S_CTL2_RX1_I2SCLK_EN_S 1
+#define TIMPANI_CDC_I2S_CTL2_RX1_I2SCLK_EN_M 0x2
+
+#define TIMPANI_CDC_I2S_CTL2_TX_I2SCLK_EN_S 0
+#define TIMPANI_CDC_I2S_CTL2_TX_I2SCLK_EN_M 0x1
+
+
+/* -- For CDC_RX2LG */
+#define TIMPANI_A_CDC_RX2LG (0xA4)
+#define TIMPANI_CDC_RX2LG_RWC "RW"
+#define TIMPANI_CDC_RX2LG_POR 0xac
+#define TIMPANI_CDC_RX2LG_S 0
+#define TIMPANI_CDC_RX2LG_M 0xFF
+
+
+#define TIMPANI_CDC_RX2LG_GAIN_S 0
+#define TIMPANI_CDC_RX2LG_GAIN_M 0xFF
+
+
+/* -- For CDC_RX2RG */
+#define TIMPANI_A_CDC_RX2RG (0xA5)
+#define TIMPANI_CDC_RX2RG_RWC "RW"
+#define TIMPANI_CDC_RX2RG_POR 0xac
+#define TIMPANI_CDC_RX2RG_S 0
+#define TIMPANI_CDC_RX2RG_M 0xFF
+
+
+#define TIMPANI_CDC_RX2RG_GAIN_S 0
+#define TIMPANI_CDC_RX2RG_GAIN_M 0xFF
+
+
+/* -- For CDC_TX2LG */
+#define TIMPANI_A_CDC_TX2LG (0xA6)
+#define TIMPANI_CDC_TX2LG_RWC "RW"
+#define TIMPANI_CDC_TX2LG_POR 0xac
+#define TIMPANI_CDC_TX2LG_S 0
+#define TIMPANI_CDC_TX2LG_M 0xFF
+
+
+#define TIMPANI_CDC_TX2LG_GAIN_S 0
+#define TIMPANI_CDC_TX2LG_GAIN_M 0xFF
+
+
+/* -- For CDC_TX2RG */
+#define TIMPANI_A_CDC_TX2RG (0xA7)
+#define TIMPANI_CDC_TX2RG_RWC "RW"
+#define TIMPANI_CDC_TX2RG_POR 0xac
+#define TIMPANI_CDC_TX2RG_S 0
+#define TIMPANI_CDC_TX2RG_M 0xFF
+
+
+#define TIMPANI_CDC_TX2RG_GAIN_S 0
+#define TIMPANI_CDC_TX2RG_GAIN_M 0xFF
+
+
+/* -- For CDC_DMIC_MUX */
+#define TIMPANI_A_CDC_DMIC_MUX (0xA8)
+#define TIMPANI_CDC_DMIC_MUX_RWC "RW"
+#define TIMPANI_CDC_DMIC_MUX_POR 0
+#define TIMPANI_CDC_DMIC_MUX_S 0
+#define TIMPANI_CDC_DMIC_MUX_M 0xFF
+
+
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_S 6
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_M 0xC0
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC2_DIN_R 0x3
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC2_DIN_L 0x2
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC1_DIN_R 0x1
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC1_DIN_L 0x0
+
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_S 4
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_M 0x30
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC2_DIN_R 0x3
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC2_DIN_L 0x2
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC1_DIN_R 0x1
+#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC1_DIN_L 0x0
+
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_S 2
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_M 0xC
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC2_DIN_R 0x3
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC2_DIN_L 0x2
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC1_DIN_R 0x1
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC1_DIN_L 0x0
+
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_S 0
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_M 0x3
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC2_DIN_R 0x3
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC2_DIN_L 0x2
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC1_DIN_R 0x1
+#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC1_DIN_L 0x0
+
+
+/* -- For CDC_ARB_CLK_CTL */
+#define TIMPANI_A_CDC_ARB_CLK_CTL (0xA9)
+#define TIMPANI_CDC_ARB_CLK_CTL_RWC "RW"
+#define TIMPANI_CDC_ARB_CLK_CTL_POR 0
+#define TIMPANI_CDC_ARB_CLK_CTL_S 0
+#define TIMPANI_CDC_ARB_CLK_CTL_M 0x3
+
+
+#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_S 0
+#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_M 0x3
+#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_TX_MCLK 0x0
+#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_RX_MCLK1 0x1
+#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_RX_MCLK2 0x2
+#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_TCXO 0x3
+
+
+/* -- For CDC_GCTL2 */
+#define TIMPANI_A_CDC_GCTL2 (0xAA)
+#define TIMPANI_CDC_GCTL2_RWC "RW"
+#define TIMPANI_CDC_GCTL2_POR 0x33
+#define TIMPANI_CDC_GCTL2_S 0
+#define TIMPANI_CDC_GCTL2_M 0xFF
+
+
+#define TIMPANI_CDC_GCTL2_TX2_PGA_UPDATE_R_S 7
+#define TIMPANI_CDC_GCTL2_TX2_PGA_UPDATE_R_M 0x80
+
+#define TIMPANI_CDC_GCTL2_TX2_PGA_UPDATE_L_S 6
+#define TIMPANI_CDC_GCTL2_TX2_PGA_UPDATE_L_M 0x40
+
+#define TIMPANI_CDC_GCTL2_TX2_PGA_MUTE_EN_R_S 5
+#define TIMPANI_CDC_GCTL2_TX2_PGA_MUTE_EN_R_M 0x20
+
+#define TIMPANI_CDC_GCTL2_TX2_PGA_MUTE_EN_L_S 4
+#define TIMPANI_CDC_GCTL2_TX2_PGA_MUTE_EN_L_M 0x10
+
+#define TIMPANI_CDC_GCTL2_RX2_PGA_UPDATE_R_S 3
+#define TIMPANI_CDC_GCTL2_RX2_PGA_UPDATE_R_M 0x8
+
+#define TIMPANI_CDC_GCTL2_RX2_PGA_UPDATE_L_S 2
+#define TIMPANI_CDC_GCTL2_RX2_PGA_UPDATE_L_M 0x4
+
+#define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_R_S 1
+#define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_R_M 0x2
+
+#define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_L_S 0
+#define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_L_M 0x1
+
+
+/* -- For CDC_BYPASS_CTL2 */
+#define TIMPANI_A_CDC_BYPASS_CTL2 (0xAB)
+#define TIMPANI_CDC_BYPASS_CTL2_RWC "RW"
+#define TIMPANI_CDC_BYPASS_CTL2_POR 0x2D
+#define TIMPANI_CDC_BYPASS_CTL2_S 0
+#define TIMPANI_CDC_BYPASS_CTL2_M 0x3F
+
+
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_DMIC_GAIN_BP_R_S 5
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_DMIC_GAIN_BP_R_M 0x20
+
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_ADC_GAIN_BP_R_S 4
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_ADC_GAIN_BP_R_M 0x10
+
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_R_S 3
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_R_M 0x8
+
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_DMIC_GAIN_BP_L_S 2
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_DMIC_GAIN_BP_L_M 0x4
+
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_ADC_GAIN_BP_L_S 1
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_ADC_GAIN_BP_L_M 0x2
+
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_L_S 0
+#define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_L_M 0x1
+
+
+/* -- For CDC_BYPASS_CTL3 */
+#define TIMPANI_A_CDC_BYPASS_CTL3 (0xAC)
+#define TIMPANI_CDC_BYPASS_CTL3_RWC "RW"
+#define TIMPANI_CDC_BYPASS_CTL3_POR 0x2D
+#define TIMPANI_CDC_BYPASS_CTL3_S 0
+#define TIMPANI_CDC_BYPASS_CTL3_M 0x3F
+
+
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_DMIC_GAIN_BP_R_S 5
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_DMIC_GAIN_BP_R_M 0x20
+
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_ADC_GAIN_BP_R_S 4
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_ADC_GAIN_BP_R_M 0x10
+
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_R_S 3
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_R_M 0x8
+
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_DMIC_GAIN_BP_L_S 2
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_DMIC_GAIN_BP_L_M 0x4
+
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_ADC_GAIN_BP_L_S 1
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_ADC_GAIN_BP_L_M 0x2
+
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_L_S 0
+#define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_L_M 0x1
+
+
+/* -- For CDC_BYPASS_CTL4 */
+#define TIMPANI_A_CDC_BYPASS_CTL4 (0xAD)
+#define TIMPANI_CDC_BYPASS_CTL4_RWC "RW"
+#define TIMPANI_CDC_BYPASS_CTL4_POR 0x2
+#define TIMPANI_CDC_BYPASS_CTL4_S 0
+#define TIMPANI_CDC_BYPASS_CTL4_M 0xF
+
+
+#define TIMPANI_CDC_BYPASS_CTL4_DITHER_BP_S 3
+#define TIMPANI_CDC_BYPASS_CTL4_DITHER_BP_M 0x8
+
+#define TIMPANI_CDC_BYPASS_CTL4_DITHER_SHAPE_SEL_S 2
+#define TIMPANI_CDC_BYPASS_CTL4_DITHER_SHAPE_SEL_M 0x4
+
+#define TIMPANI_CDC_BYPASS_CTL4_DITHER_DLY_SEL_S 1
+#define TIMPANI_CDC_BYPASS_CTL4_DITHER_DLY_SEL_M 0x2
+
+#define TIMPANI_CDC_BYPASS_CTL4_RX2_HPF_BP_S 0
+#define TIMPANI_CDC_BYPASS_CTL4_RX2_HPF_BP_M 0x1
+
+
+/* -- For CDC_RX2L_DCOFFSET */
+#define TIMPANI_A_CDC_RX2L_DCOFFSET (0xAE)
+#define TIMPANI_CDC_RX2L_DCOFFSET_RWC "RW"
+#define TIMPANI_CDC_RX2L_DCOFFSET_POR 0
+#define TIMPANI_CDC_RX2L_DCOFFSET_S 0
+#define TIMPANI_CDC_RX2L_DCOFFSET_M 0xFF
+
+
+#define TIMPANI_CDC_RX2L_DCOFFSET_OFFSET_S 0
+#define TIMPANI_CDC_RX2L_DCOFFSET_OFFSET_M 0xFF
+
+
+/* -- For CDC_RX2R_DCOFFSET */
+#define TIMPANI_A_CDC_RX2R_DCOFFSET (0xAF)
+#define TIMPANI_CDC_RX2R_DCOFFSET_RWC "RW"
+#define TIMPANI_CDC_RX2R_DCOFFSET_POR 0
+#define TIMPANI_CDC_RX2R_DCOFFSET_S 0
+#define TIMPANI_CDC_RX2R_DCOFFSET_M 0xFF
+
+
+#define TIMPANI_CDC_RX2R_DCOFFSET_OFFSET_S 0
+#define TIMPANI_CDC_RX2R_DCOFFSET_OFFSET_M 0xFF
+
+
+/* -- For CDC_RX_MIX_CTL */
+#define TIMPANI_A_CDC_RX_MIX_CTL (0xB0)
+#define TIMPANI_CDC_RX_MIX_CTL_RWC "RW"
+#define TIMPANI_CDC_RX_MIX_CTL_POR 0
+#define TIMPANI_CDC_RX_MIX_CTL_S 0
+#define TIMPANI_CDC_RX_MIX_CTL_M 0x3
+
+
+#define TIMPANI_CDC_RX_MIX_CTL_RX2TO1_EN_S 1
+#define TIMPANI_CDC_RX_MIX_CTL_RX2TO1_EN_M 0x2
+
+#define TIMPANI_CDC_RX_MIX_CTL_RX1TO2_EN_S 0
+#define TIMPANI_CDC_RX_MIX_CTL_RX1TO2_EN_M 0x1
+
+
+/* -- For CDC_SPARE_CTL */
+#define TIMPANI_A_CDC_SPARE_CTL (0xB1)
+#define TIMPANI_CDC_SPARE_CTL_RWC "RW"
+#define TIMPANI_CDC_SPARE_CTL_POR 0
+#define TIMPANI_CDC_SPARE_CTL_S 0
+#define TIMPANI_CDC_SPARE_CTL_M 0xFF
+
+
+#define TIMPANI_CDC_SPARE_CTL_CDC_SPARE_S 0
+#define TIMPANI_CDC_SPARE_CTL_CDC_SPARE_M 0xFF
+
+
+/* -- For CDC_TESTMODE2 */
+#define TIMPANI_A_CDC_TESTMODE2 (0xB2)
+#define TIMPANI_CDC_TESTMODE2_RWC "RW"
+#define TIMPANI_CDC_TESTMODE2_POR 0
+#define TIMPANI_CDC_TESTMODE2_S 0
+#define TIMPANI_CDC_TESTMODE2_M 0x1F
+
+
+#define TIMPANI_CDC_TESTMODE2_RX2_TEST_EN_R_S 4
+#define TIMPANI_CDC_TESTMODE2_RX2_TEST_EN_R_M 0x10
+
+#define TIMPANI_CDC_TESTMODE2_RX2_TEST_EN_L_S 3
+#define TIMPANI_CDC_TESTMODE2_RX2_TEST_EN_L_M 0x8
+
+#define TIMPANI_CDC_TESTMODE2_TX2_TEST_EN_R_S 2
+#define TIMPANI_CDC_TESTMODE2_TX2_TEST_EN_R_M 0x4
+
+#define TIMPANI_CDC_TESTMODE2_TX2_TEST_EN_L_S 1
+#define TIMPANI_CDC_TESTMODE2_TX2_TEST_EN_L_M 0x2
+
+#define TIMPANI_CDC_TESTMODE2_A_LOOPBACK_EN2_S 0
+#define TIMPANI_CDC_TESTMODE2_A_LOOPBACK_EN2_M 0x1
+
+
+/* -- For CDC_PDM_OE */
+#define TIMPANI_A_CDC_PDM_OE (0xB3)
+#define TIMPANI_CDC_PDM_OE_RWC "RW"
+#define TIMPANI_CDC_PDM_OE_POR 0
+#define TIMPANI_CDC_PDM_OE_S 0
+#define TIMPANI_CDC_PDM_OE_M 0x3F
+
+
+#define TIMPANI_CDC_PDM_OE_PDM_23_20_OE_S 5
+#define TIMPANI_CDC_PDM_OE_PDM_23_20_OE_M 0x20
+
+#define TIMPANI_CDC_PDM_OE_PDM_19_16_OE_S 4
+#define TIMPANI_CDC_PDM_OE_PDM_19_16_OE_M 0x10
+
+#define TIMPANI_CDC_PDM_OE_PDM_15_12_OE_S 3
+#define TIMPANI_CDC_PDM_OE_PDM_15_12_OE_M 0x8
+
+#define TIMPANI_CDC_PDM_OE_PDM_11_8_OE_S 2
+#define TIMPANI_CDC_PDM_OE_PDM_11_8_OE_M 0x4
+
+#define TIMPANI_CDC_PDM_OE_PDM_7_4_OE_S 1
+#define TIMPANI_CDC_PDM_OE_PDM_7_4_OE_M 0x2
+
+#define TIMPANI_CDC_PDM_OE_PDM_3_0_OE_S 0
+#define TIMPANI_CDC_PDM_OE_PDM_3_0_OE_M 0x1
+
+
+/* -- For CDC_TX1R_STG */
+#define TIMPANI_A_CDC_TX1R_STG (0xB4)
+#define TIMPANI_CDC_TX1R_STG_RWC "RW"
+#define TIMPANI_CDC_TX1R_STG_POR 0xac
+#define TIMPANI_CDC_TX1R_STG_S 0
+#define TIMPANI_CDC_TX1R_STG_M 0xFF
+
+
+#define TIMPANI_CDC_TX1R_STG_GAIN_S 0
+#define TIMPANI_CDC_TX1R_STG_GAIN_M 0xFF
+
+
+/* -- For CDC_TX2L_STG */
+#define TIMPANI_A_CDC_TX2L_STG (0xB5)
+#define TIMPANI_CDC_TX2L_STG_RWC "RW"
+#define TIMPANI_CDC_TX2L_STG_POR 0xac
+#define TIMPANI_CDC_TX2L_STG_S 0
+#define TIMPANI_CDC_TX2L_STG_M 0xFF
+
+
+#define TIMPANI_CDC_TX2L_STG_GAIN_S 0
+#define TIMPANI_CDC_TX2L_STG_GAIN_M 0xFF
+
+
+/* -- For CDC_TX2R_STG */
+#define TIMPANI_A_CDC_TX2R_STG (0xB6)
+#define TIMPANI_CDC_TX2R_STG_RWC "RW"
+#define TIMPANI_CDC_TX2R_STG_POR 0xac
+#define TIMPANI_CDC_TX2R_STG_S 0
+#define TIMPANI_CDC_TX2R_STG_M 0xFF
+
+
+#define TIMPANI_CDC_TX2R_STG_GAIN_S 0
+#define TIMPANI_CDC_TX2R_STG_GAIN_M 0xFF
+
+
+/* -- For CDC_ARB_BYPASS_CTL */
+#define TIMPANI_A_CDC_ARB_BYPASS_CTL (0xB7)
+#define TIMPANI_CDC_ARB_BYPASS_CTL_RWC "RW"
+#define TIMPANI_CDC_ARB_BYPASS_CTL_POR 0
+#define TIMPANI_CDC_ARB_BYPASS_CTL_S 0
+#define TIMPANI_CDC_ARB_BYPASS_CTL_M 0x1
+
+
+#define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_S 0
+#define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_M 0x1
+#define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_BYPASS 0x1
+#define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_NO_BYPASS 0x0
+
+
+/* -- For CDC_ANC1_CTL1 */
+#define TIMPANI_A_CDC_ANC1_CTL1 (0xC0)
+#define TIMPANI_CDC_ANC1_CTL1_RWC "RW"
+#define TIMPANI_CDC_ANC1_CTL1_POR 0
+#define TIMPANI_CDC_ANC1_CTL1_S 0
+#define TIMPANI_CDC_ANC1_CTL1_M 0x3F
+
+
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_S 5
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_M 0x20
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_FF_OUT_DIS 0x1
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_FF_OUT_EN 0x0
+
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_ADC_DMIC_SEL_S 4
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_ADC_DMIC_SEL_M 0x10
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_ADC_DMIC_SEL_DMIC 0x1
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_ADC_DMIC_SEL_ADC 0x0
+
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_S 3
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_M 0x8
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_LR_MIX_EN 0x1
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_LR_MIX_DIS 0x0
+
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_S 2
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_M 0x4
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_FB_MIX_EN 0x1
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_FB_MIX_DIS 0x0
+
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_S 1
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_M 0x2
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_ANC_EN 0x1
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_ANC_DIS 0x0
+
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_S 0
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_M 0x1
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_ANC_RESET 0x1
+#define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_ANC_ACTIVE 0x0
+
+
+/* -- For CDC_ANC1_CTL2 */
+#define TIMPANI_A_CDC_ANC1_CTL2 (0xC1)
+#define TIMPANI_CDC_ANC1_CTL2_RWC "RW"
+#define TIMPANI_CDC_ANC1_CTL2_POR 0
+#define TIMPANI_CDC_ANC1_CTL2_S 0
+#define TIMPANI_CDC_ANC1_CTL2_M 0x1F
+
+
+#define TIMPANI_CDC_ANC1_CTL2_ANC1_FREQ_SEL_S 0
+#define TIMPANI_CDC_ANC1_CTL2_ANC1_FREQ_SEL_M 0x1F
+
+
+/* -- For CDC_ANC1_FF_FB_SHIFT */
+#define TIMPANI_A_CDC_ANC1_FF_FB_SHIFT (0xC2)
+#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_RWC "RW"
+#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_POR 0
+#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_S 0
+#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_M 0xFF
+
+
+#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_ANC1_FB_LPF_SHIFT_S 4
+#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_ANC1_FB_LPF_SHIFT_M 0xF0
+
+#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_ANC1_FF_LPF_SHIFT_S 0
+#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_ANC1_FF_LPF_SHIFT_M 0xF
+
+
+/* -- For CDC_ANC1_RX_NS */
+#define TIMPANI_A_CDC_ANC1_RX_NS (0xC3)
+#define TIMPANI_CDC_ANC1_RX_NS_RWC "RW"
+#define TIMPANI_CDC_ANC1_RX_NS_POR 0x1
+#define TIMPANI_CDC_ANC1_RX_NS_S 0
+#define TIMPANI_CDC_ANC1_RX_NS_M 0x7
+
+
+#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_BP_S 2
+#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_BP_M 0x4
+
+#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_SHAPE_SEL_S 1
+#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_SHAPE_SEL_M 0x2
+
+#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_DLY_SEL_S 0
+#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_DLY_SEL_M 0x1
+
+
+/* -- For CDC_ANC1_SPARE */
+#define TIMPANI_A_CDC_ANC1_SPARE (0xC4)
+#define TIMPANI_CDC_ANC1_SPARE_RWC "RW"
+#define TIMPANI_CDC_ANC1_SPARE_POR 0
+#define TIMPANI_CDC_ANC1_SPARE_S 0
+#define TIMPANI_CDC_ANC1_SPARE_M 0xFF
+
+
+#define TIMPANI_CDC_ANC1_SPARE_ANC1_SPARE_S 0
+#define TIMPANI_CDC_ANC1_SPARE_ANC1_SPARE_M 0xFF
+
+
+/* -- For CDC_ANC1_IIR_COEFF_PTR */
+#define TIMPANI_A_CDC_ANC1_IIR_COEFF_PTR (0xC5)
+#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_RWC "RW"
+#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_POR 0
+#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_S 0
+#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_M 0x1F
+
+
+#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_ANC1_IIR_COEFF_PTR_S 0
+#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_ANC1_IIR_COEFF_PTR_M 0x1F
+
+
+/* -- For CDC_ANC1_IIR_COEFF_MSB */
+#define TIMPANI_A_CDC_ANC1_IIR_COEFF_MSB (0xC6)
+#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_RWC "RW"
+#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_POR 0
+#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_S 0
+#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_M 0x1
+
+
+#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_ANC1_IIR_COEFF_MSB_S 0
+#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_ANC1_IIR_COEFF_MSB_M 0x1
+
+
+/* -- For CDC_ANC1_IIR_COEFF_LSB */
+#define TIMPANI_A_CDC_ANC1_IIR_COEFF_LSB (0xC7)
+#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_RWC "RW"
+#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_POR 0
+#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_S 0
+#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_M 0xFF
+
+
+#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_ANC1_IIR_COEFF_LSB_S 0
+#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_ANC1_IIR_COEFF_LSB_M 0xFF
+
+
+/* -- For CDC_ANC1_IIR_COEFF_CTL */
+#define TIMPANI_A_CDC_ANC1_IIR_COEFF_CTL (0xC8)
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_RWC "RW"
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_POR 0
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_S 0
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_M 0x3
+
+
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_S 1
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_M 0x2
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_ADAPTIVE 0x1
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_NON_ADAPTIVE 0x0
+
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_S 0
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_M 0x1
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_UPDATE 0x1
+#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_NO_UPDATE 0x0
+
+
+/* -- For CDC_ANC1_LPF_COEFF_PTR */
+#define TIMPANI_A_CDC_ANC1_LPF_COEFF_PTR (0xC9)
+#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_RWC "RW"
+#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_POR 0
+#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_S 0
+#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_M 0xF
+
+
+#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_ANC1_LPF_COEFF_PTR_S 0
+#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_ANC1_LPF_COEFF_PTR_M 0xF
+
+
+/* -- For CDC_ANC1_LPF_COEFF_MSB */
+#define TIMPANI_A_CDC_ANC1_LPF_COEFF_MSB (0xCA)
+#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_RWC "RW"
+#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_POR 0
+#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_S 0
+#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_M 0xF
+
+
+#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_ANC1_LPF_COEFF_MSB_S 0
+#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_ANC1_LPF_COEFF_MSB_M 0xF
+
+
+/* -- For CDC_ANC1_LPF_COEFF_LSB */
+#define TIMPANI_A_CDC_ANC1_LPF_COEFF_LSB (0xCB)
+#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_RWC "RW"
+#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_POR 0
+#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_S 0
+#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_M 0xFF
+
+
+#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_ANC1_LPF_COEFF_LSB_S 0
+#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_ANC1_LPF_COEFF_LSB_M 0xFF
+
+
+/* -- For CDC_ANC1_SCALE_PTR */
+#define TIMPANI_A_CDC_ANC1_SCALE_PTR (0xCC)
+#define TIMPANI_CDC_ANC1_SCALE_PTR_RWC "RW"
+#define TIMPANI_CDC_ANC1_SCALE_PTR_POR 0
+#define TIMPANI_CDC_ANC1_SCALE_PTR_S 0
+#define TIMPANI_CDC_ANC1_SCALE_PTR_M 0x7
+
+
+#define TIMPANI_CDC_ANC1_SCALE_PTR_ANC1_SCALE_PTR_S 0
+#define TIMPANI_CDC_ANC1_SCALE_PTR_ANC1_SCALE_PTR_M 0x7
+
+
+/* -- For CDC_ANC1_SCALE */
+#define TIMPANI_A_CDC_ANC1_SCALE (0xCD)
+#define TIMPANI_CDC_ANC1_SCALE_RWC "RW"
+#define TIMPANI_CDC_ANC1_SCALE_POR 0
+#define TIMPANI_CDC_ANC1_SCALE_S 0
+#define TIMPANI_CDC_ANC1_SCALE_M 0xFF
+
+
+#define TIMPANI_CDC_ANC1_SCALE_ANC1_SCALE_S 0
+#define TIMPANI_CDC_ANC1_SCALE_ANC1_SCALE_M 0xFF
+
+
+/* -- For CDC_ANC1_DEBUG */
+#define TIMPANI_A_CDC_ANC1_DEBUG (0xCE)
+#define TIMPANI_CDC_ANC1_DEBUG_RWC "RW"
+#define TIMPANI_CDC_ANC1_DEBUG_POR 0
+#define TIMPANI_CDC_ANC1_DEBUG_S 0
+#define TIMPANI_CDC_ANC1_DEBUG_M 0xF
+
+
+#define TIMPANI_CDC_ANC1_DEBUG_ANC1_DEBUG_SEL_S 0
+#define TIMPANI_CDC_ANC1_DEBUG_ANC1_DEBUG_SEL_M 0xF
+
+
+/* -- For CDC_ANC2_CTL1 */
+#define TIMPANI_A_CDC_ANC2_CTL1 (0xD0)
+#define TIMPANI_CDC_ANC2_CTL1_RWC "RW"
+#define TIMPANI_CDC_ANC2_CTL1_POR 0
+#define TIMPANI_CDC_ANC2_CTL1_S 0
+#define TIMPANI_CDC_ANC2_CTL1_M 0x3F
+
+
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_S 5
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_M 0x20
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_FF_OUT_DIS 0x1
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_FF_OUT_EN 0x0
+
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_ADC_DMIC_SEL_S 4
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_ADC_DMIC_SEL_M 0x10
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_ADC_DMIC_SEL_DMIC 0x1
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_ADC_DMIC_SEL_ADC 0x0
+
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_S 3
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_M 0x8
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_LR_MIX_EN 0x1
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_LR_MIX_DIS 0x0
+
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_S 2
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_M 0x4
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_FB_MIX_EN 0x1
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_FB_MIX_DIS 0x0
+
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_S 1
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_M 0x2
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_ANC_EN 0x1
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_ANC_DIS 0x0
+
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_S 0
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_M 0x1
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_ANC_RESET 0x1
+#define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_ANC_ACTIVE 0x0
+
+
+/* -- For CDC_ANC2_CTL2 */
+#define TIMPANI_A_CDC_ANC2_CTL2 (0xD1)
+#define TIMPANI_CDC_ANC2_CTL2_RWC "RW"
+#define TIMPANI_CDC_ANC2_CTL2_POR 0
+#define TIMPANI_CDC_ANC2_CTL2_S 0
+#define TIMPANI_CDC_ANC2_CTL2_M 0x1F
+
+
+#define TIMPANI_CDC_ANC2_CTL2_ANC2_FREQ_SEL_S 0
+#define TIMPANI_CDC_ANC2_CTL2_ANC2_FREQ_SEL_M 0x1F
+
+
+/* -- For CDC_ANC2_FF_FB_SHIFT */
+#define TIMPANI_A_CDC_ANC2_FF_FB_SHIFT (0xD2)
+#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_RWC "RW"
+#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_POR 0
+#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_S 0
+#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_M 0xFF
+
+
+#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_ANC2_FB_LPF_SHIFT_S 4
+#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_ANC2_FB_LPF_SHIFT_M 0xF0
+
+#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_ANC2_FF_LPF_SHIFT_S 0
+#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_ANC2_FF_LPF_SHIFT_M 0xF
+
+
+/* -- For CDC_ANC2_RX_NS */
+#define TIMPANI_A_CDC_ANC2_RX_NS (0xD3)
+#define TIMPANI_CDC_ANC2_RX_NS_RWC "RW"
+#define TIMPANI_CDC_ANC2_RX_NS_POR 0x1
+#define TIMPANI_CDC_ANC2_RX_NS_S 0
+#define TIMPANI_CDC_ANC2_RX_NS_M 0x7
+
+
+#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_BP_S 2
+#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_BP_M 0x4
+
+#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_SHAPE_SEL_S 1
+#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_SHAPE_SEL_M 0x2
+
+#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_DLY_SEL_S 0
+#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_DLY_SEL_M 0x1
+
+
+/* -- For CDC_ANC2_SPARE */
+#define TIMPANI_A_CDC_ANC2_SPARE (0xD4)
+#define TIMPANI_CDC_ANC2_SPARE_RWC "RW"
+#define TIMPANI_CDC_ANC2_SPARE_POR 0
+#define TIMPANI_CDC_ANC2_SPARE_S 0
+#define TIMPANI_CDC_ANC2_SPARE_M 0xFF
+
+
+#define TIMPANI_CDC_ANC2_SPARE_ANC2_SPARE_S 0
+#define TIMPANI_CDC_ANC2_SPARE_ANC2_SPARE_M 0xFF
+
+
+/* -- For CDC_ANC2_IIR_COEFF_PTR */
+#define TIMPANI_A_CDC_ANC2_IIR_COEFF_PTR (0xD5)
+#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_RWC "RW"
+#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_POR 0
+#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_S 0
+#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_M 0x1F
+
+
+#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_ANC2_IIR_COEFF_PTR_S 0
+#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_ANC2_IIR_COEFF_PTR_M 0x1F
+
+
+/* -- For CDC_ANC2_IIR_COEFF_MSB */
+#define TIMPANI_A_CDC_ANC2_IIR_COEFF_MSB (0xD6)
+#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_RWC "RW"
+#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_POR 0
+#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_S 0
+#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_M 0x1
+
+
+#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_ANC2_IIR_COEFF_MSB_S 0
+#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_ANC2_IIR_COEFF_MSB_M 0x1
+
+
+/* -- For CDC_ANC2_IIR_COEFF_LSB */
+#define TIMPANI_A_CDC_ANC2_IIR_COEFF_LSB (0xD7)
+#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_RWC "RW"
+#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_POR 0
+#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_S 0
+#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_M 0xFF
+
+
+#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_ANC2_IIR_COEFF_LSB_S 0
+#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_ANC2_IIR_COEFF_LSB_M 0xFF
+
+
+/* -- For CDC_ANC2_IIR_COEFF_CTL */
+#define TIMPANI_A_CDC_ANC2_IIR_COEFF_CTL (0xD8)
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_RWC "RW"
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_POR 0
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_S 0
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_M 0x3
+
+
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_S 1
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_M 0x2
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_ADAPTIVE 0x1
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_NON_ADAPTIVE 0x0
+
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_S 0
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_M 0x1
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_UPDATE 0x1
+#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_NO_UPDATE 0x0
+
+
+/* -- For CDC_ANC2_LPF_COEFF_PTR */
+#define TIMPANI_A_CDC_ANC2_LPF_COEFF_PTR (0xD9)
+#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_RWC "RW"
+#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_POR 0
+#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_S 0
+#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_M 0xF
+
+
+#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_ANC2_LPF_COEFF_PTR_S 0
+#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_ANC2_LPF_COEFF_PTR_M 0xF
+
+
+/* -- For CDC_ANC2_LPF_COEFF_MSB */
+#define TIMPANI_A_CDC_ANC2_LPF_COEFF_MSB (0xDA)
+#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_RWC "RW"
+#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_POR 0
+#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_S 0
+#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_M 0xF
+
+
+#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_ANC2_LPF_COEFF_MSB_S 0
+#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_ANC2_LPF_COEFF_MSB_M 0xF
+
+
+/* -- For CDC_ANC2_LPF_COEFF_LSB */
+#define TIMPANI_A_CDC_ANC2_LPF_COEFF_LSB (0xDB)
+#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_RWC "RW"
+#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_POR 0
+#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_S 0
+#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_M 0xFF
+
+
+#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_ANC2_LPF_COEFF_LSB_S 0
+#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_ANC2_LPF_COEFF_LSB_M 0xFF
+
+
+/* -- For CDC_ANC2_SCALE_PTR */
+#define TIMPANI_A_CDC_ANC2_SCALE_PTR (0xDC)
+#define TIMPANI_CDC_ANC2_SCALE_PTR_RWC "RW"
+#define TIMPANI_CDC_ANC2_SCALE_PTR_POR 0
+#define TIMPANI_CDC_ANC2_SCALE_PTR_S 0
+#define TIMPANI_CDC_ANC2_SCALE_PTR_M 0x7
+
+
+#define TIMPANI_CDC_ANC2_SCALE_PTR_ANC2_SCALE_PTR_S 0
+#define TIMPANI_CDC_ANC2_SCALE_PTR_ANC2_SCALE_PTR_M 0x7
+
+
+/* -- For CDC_ANC2_SCALE */
+#define TIMPANI_A_CDC_ANC2_SCALE (0xDD)
+#define TIMPANI_CDC_ANC2_SCALE_RWC "RW"
+#define TIMPANI_CDC_ANC2_SCALE_POR 0
+#define TIMPANI_CDC_ANC2_SCALE_S 0
+#define TIMPANI_CDC_ANC2_SCALE_M 0xFF
+
+
+#define TIMPANI_CDC_ANC2_SCALE_ANC2_SCALE_S 0
+#define TIMPANI_CDC_ANC2_SCALE_ANC2_SCALE_M 0xFF
+
+
+/* -- For CDC_ANC2_DEBUG */
+#define TIMPANI_A_CDC_ANC2_DEBUG (0xDE)
+#define TIMPANI_CDC_ANC2_DEBUG_RWC "RW"
+#define TIMPANI_CDC_ANC2_DEBUG_POR 0
+#define TIMPANI_CDC_ANC2_DEBUG_S 0
+#define TIMPANI_CDC_ANC2_DEBUG_M 0xF
+
+
+#define TIMPANI_CDC_ANC2_DEBUG_ANC2_DEBUG_SEL_S 0
+#define TIMPANI_CDC_ANC2_DEBUG_ANC2_DEBUG_SEL_M 0xF
+
+
+/* -- For CDC_LINE_L_AVOL */
+#define TIMPANI_A_CDC_LINE_L_AVOL (0xE0)
+#define TIMPANI_CDC_LINE_L_AVOL_RWC "RW"
+#define TIMPANI_CDC_LINE_L_AVOL_POR 0xac
+#define TIMPANI_CDC_LINE_L_AVOL_S 0
+#define TIMPANI_CDC_LINE_L_AVOL_M 0xFF
+
+
+#define TIMPANI_CDC_LINE_L_AVOL_USER_GAIN_S 2
+#define TIMPANI_CDC_LINE_L_AVOL_USER_GAIN_M 0xFC
+
+#define TIMPANI_CDC_LINE_L_AVOL_DUMMY_S 0
+#define TIMPANI_CDC_LINE_L_AVOL_DUMMY_M 0x3
+
+
+/* -- For CDC_LINE_R_AVOL */
+#define TIMPANI_A_CDC_LINE_R_AVOL (0xE1)
+#define TIMPANI_CDC_LINE_R_AVOL_RWC "RW"
+#define TIMPANI_CDC_LINE_R_AVOL_POR 0xac
+#define TIMPANI_CDC_LINE_R_AVOL_S 0
+#define TIMPANI_CDC_LINE_R_AVOL_M 0xFF
+
+
+#define TIMPANI_CDC_LINE_R_AVOL_USER_GAIN_S 2
+#define TIMPANI_CDC_LINE_R_AVOL_USER_GAIN_M 0xFC
+
+#define TIMPANI_CDC_LINE_R_AVOL_DUMMY_S 0
+#define TIMPANI_CDC_LINE_R_AVOL_DUMMY_M 0x3
+
+
+/* -- For CDC_HPH_L_AVOL */
+#define TIMPANI_A_CDC_HPH_L_AVOL (0xE2)
+#define TIMPANI_CDC_HPH_L_AVOL_RWC "RW"
+#define TIMPANI_CDC_HPH_L_AVOL_POR 0xae
+#define TIMPANI_CDC_HPH_L_AVOL_S 0
+#define TIMPANI_CDC_HPH_L_AVOL_M 0xFF
+
+
+#define TIMPANI_CDC_HPH_L_AVOL_USER_GAIN_S 2
+#define TIMPANI_CDC_HPH_L_AVOL_USER_GAIN_M 0xFC
+
+#define TIMPANI_CDC_HPH_L_AVOL_MUTE_S 1
+#define TIMPANI_CDC_HPH_L_AVOL_MUTE_M 0x2
+#define TIMPANI_CDC_HPH_L_AVOL_MUTE_MUTE 0x1
+#define TIMPANI_CDC_HPH_L_AVOL_MUTE_UNMUTE 0x0
+
+#define TIMPANI_CDC_HPH_L_AVOL_DUMMY_S 0
+#define TIMPANI_CDC_HPH_L_AVOL_DUMMY_M 0x1
+
+
+/* -- For CDC_HPH_R_AVOL */
+#define TIMPANI_A_CDC_HPH_R_AVOL (0xE3)
+#define TIMPANI_CDC_HPH_R_AVOL_RWC "RW"
+#define TIMPANI_CDC_HPH_R_AVOL_POR 0xae
+#define TIMPANI_CDC_HPH_R_AVOL_S 0
+#define TIMPANI_CDC_HPH_R_AVOL_M 0xFF
+
+
+#define TIMPANI_CDC_HPH_R_AVOL_USER_GAIN_S 2
+#define TIMPANI_CDC_HPH_R_AVOL_USER_GAIN_M 0xFC
+
+#define TIMPANI_CDC_HPH_R_AVOL_MUTE_S 1
+#define TIMPANI_CDC_HPH_R_AVOL_MUTE_M 0x2
+#define TIMPANI_CDC_HPH_R_AVOL_MUTE_MUTE 0x1
+#define TIMPANI_CDC_HPH_R_AVOL_MUTE_UNMUTE 0x0
+
+#define TIMPANI_CDC_HPH_R_AVOL_DUMMY_S 0
+#define TIMPANI_CDC_HPH_R_AVOL_DUMMY_M 0x1
+
+
+/* -- For CDC_COMP_CTL1 */
+#define TIMPANI_A_CDC_COMP_CTL1 (0xE4)
+#define TIMPANI_CDC_COMP_CTL1_RWC "RW"
+#define TIMPANI_CDC_COMP_CTL1_POR 0
+#define TIMPANI_CDC_COMP_CTL1_S 0
+#define TIMPANI_CDC_COMP_CTL1_M 0xFF
+
+
+#define TIMPANI_CDC_COMP_CTL1_LO_CLK_EN_S 7
+#define TIMPANI_CDC_COMP_CTL1_LO_CLK_EN_M 0x80
+
+#define TIMPANI_CDC_COMP_CTL1_HPH_CLK_EN_S 6
+#define TIMPANI_CDC_COMP_CTL1_HPH_CLK_EN_M 0x40
+
+#define TIMPANI_CDC_COMP_CTL1_LO_SOFT_RESET_S 5
+#define TIMPANI_CDC_COMP_CTL1_LO_SOFT_RESET_M 0x20
+
+#define TIMPANI_CDC_COMP_CTL1_HPH_SOFT_RESET_S 4
+#define TIMPANI_CDC_COMP_CTL1_HPH_SOFT_RESET_M 0x10
+
+#define TIMPANI_CDC_COMP_CTL1_LO_R_EN_S 3
+#define TIMPANI_CDC_COMP_CTL1_LO_R_EN_M 0x8
+
+#define TIMPANI_CDC_COMP_CTL1_LO_L_EN_S 2
+#define TIMPANI_CDC_COMP_CTL1_LO_L_EN_M 0x4
+
+#define TIMPANI_CDC_COMP_CTL1_HPH_R_EN_S 1
+#define TIMPANI_CDC_COMP_CTL1_HPH_R_EN_M 0x2
+
+#define TIMPANI_CDC_COMP_CTL1_HPH_L_EN_S 0
+#define TIMPANI_CDC_COMP_CTL1_HPH_L_EN_M 0x1
+
+
+/* -- For CDC_COMP_CTL2 */
+#define TIMPANI_A_CDC_COMP_CTL2 (0xE5)
+#define TIMPANI_CDC_COMP_CTL2_RWC "RW"
+#define TIMPANI_CDC_COMP_CTL2_POR 0xe
+#define TIMPANI_CDC_COMP_CTL2_S 0
+#define TIMPANI_CDC_COMP_CTL2_M 0xF
+
+
+#define TIMPANI_CDC_COMP_CTL2_LINEOUT_IN_MUX_S 2
+#define TIMPANI_CDC_COMP_CTL2_LINEOUT_IN_MUX_M 0xC
+
+#define TIMPANI_CDC_COMP_CTL2_HPH_IN_MUX_S 0
+#define TIMPANI_CDC_COMP_CTL2_HPH_IN_MUX_M 0x3
+
+
+/* -- For CDC_COMP_PEAK_METER */
+#define TIMPANI_A_CDC_COMP_PEAK_METER (0xE6)
+#define TIMPANI_CDC_COMP_PEAK_METER_RWC "RW"
+#define TIMPANI_CDC_COMP_PEAK_METER_POR 0x9
+#define TIMPANI_CDC_COMP_PEAK_METER_S 0
+#define TIMPANI_CDC_COMP_PEAK_METER_M 0xF
+
+
+#define TIMPANI_CDC_COMP_PEAK_METER_TIME_OUT_S 0
+#define TIMPANI_CDC_COMP_PEAK_METER_TIME_OUT_M 0xF
+
+
+/* -- For CDC_COMP_LEVEL_METER_CTL1 */
+#define TIMPANI_A_CDC_COMP_LEVEL_METER_CTL1 (0xE7)
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_RWC "RW"
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_POR 0x7
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_S 0
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_M 0xF
+
+
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_DIV_FACTOR_S 0
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_DIV_FACTOR_M 0xF
+
+
+/* -- For CDC_COMP_LEVEL_METER_CTL2 */
+#define TIMPANI_A_CDC_COMP_LEVEL_METER_CTL2 (0xE8)
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_RWC "RW"
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_POR 0x28
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_S 0
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_M 0xFF
+
+
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_RESAMPLE_RATE_S 0
+#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_RESAMPLE_RATE_M 0xFF
+
+
+/* -- For CDC_COMP_ZONE_SELECT */
+#define TIMPANI_A_CDC_COMP_ZONE_SELECT (0xE9)
+#define TIMPANI_CDC_COMP_ZONE_SELECT_RWC "RW"
+#define TIMPANI_CDC_COMP_ZONE_SELECT_POR 0x3b
+#define TIMPANI_CDC_COMP_ZONE_SELECT_S 0
+#define TIMPANI_CDC_COMP_ZONE_SELECT_M 0x7F
+
+
+#define TIMPANI_CDC_COMP_ZONE_SELECT_ENTRY_S 3
+#define TIMPANI_CDC_COMP_ZONE_SELECT_ENTRY_M 0x78
+
+#define TIMPANI_CDC_COMP_ZONE_SELECT_SHIFT_S 0
+#define TIMPANI_CDC_COMP_ZONE_SELECT_SHIFT_M 0x7
+
+
+/* -- For CDC_COMP_ZC_MSB */
+#define TIMPANI_A_CDC_COMP_ZC_MSB (0xEA)
+#define TIMPANI_CDC_COMP_ZC_MSB_RWC "RW"
+#define TIMPANI_CDC_COMP_ZC_MSB_POR 0
+#define TIMPANI_CDC_COMP_ZC_MSB_S 0
+#define TIMPANI_CDC_COMP_ZC_MSB_M 0x7
+
+
+#define TIMPANI_CDC_COMP_ZC_MSB_DET_WINDOW_S 0
+#define TIMPANI_CDC_COMP_ZC_MSB_DET_WINDOW_M 0x7
+
+
+/* -- For CDC_COMP_ZC_LSB */
+#define TIMPANI_A_CDC_COMP_ZC_LSB (0xEB)
+#define TIMPANI_CDC_COMP_ZC_LSB_RWC "RW"
+#define TIMPANI_CDC_COMP_ZC_LSB_POR 0x1f
+#define TIMPANI_CDC_COMP_ZC_LSB_S 0
+#define TIMPANI_CDC_COMP_ZC_LSB_M 0xFF
+
+
+#define TIMPANI_CDC_COMP_ZC_LSB_DET_WINDOW_S 0
+#define TIMPANI_CDC_COMP_ZC_LSB_DET_WINDOW_M 0xFF
+
+
+/* -- For CDC_COMP_SHUT_DOWN */
+#define TIMPANI_A_CDC_COMP_SHUT_DOWN (0xEC)
+#define TIMPANI_CDC_COMP_SHUT_DOWN_RWC "RW"
+#define TIMPANI_CDC_COMP_SHUT_DOWN_POR 0x1b
+#define TIMPANI_CDC_COMP_SHUT_DOWN_S 0
+#define TIMPANI_CDC_COMP_SHUT_DOWN_M 0x3F
+
+
+#define TIMPANI_CDC_COMP_SHUT_DOWN_HPH_TIMEOUT_S 3
+#define TIMPANI_CDC_COMP_SHUT_DOWN_HPH_TIMEOUT_M 0x38
+
+#define TIMPANI_CDC_COMP_SHUT_DOWN_LO_TIMEOUT_S 0
+#define TIMPANI_CDC_COMP_SHUT_DOWN_LO_TIMEOUT_M 0x7
+
+
+/* -- For CDC_COMP_SHUT_DOWN_STATUS */
+#define TIMPANI_A_CDC_COMP_SHUT_DOWN_STATUS (0xED)
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_RWC "RW"
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_POR 0
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_S 0
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_M 0xF
+
+
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_LO_R_S 3
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_LO_R_M 0x8
+
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_LO_L_S 2
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_LO_L_M 0x4
+
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_R_S 1
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_R_M 0x2
+
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_L_S 0
+#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_L_M 0x1
+
+
+/* -- For CDC_COMP_HALT */
+#define TIMPANI_A_CDC_COMP_HALT (0xEE)
+#define TIMPANI_CDC_COMP_HALT_RWC "RW"
+#define TIMPANI_CDC_COMP_HALT_POR 0
+#define TIMPANI_CDC_COMP_HALT_S 0
+#define TIMPANI_CDC_COMP_HALT_M 0x1
+
+
+#define TIMPANI_CDC_COMP_HALT_COMPANDER_HALT_S 0
+#define TIMPANI_CDC_COMP_HALT_COMPANDER_HALT_M 0x1
+
+
+#endif
diff --git a/original/linux/mfd/wcd9xxx/wcd9310_registers.h b/original/linux/mfd/wcd9xxx/wcd9310_registers.h
new file mode 100644
index 0000000..67c2a6b
--- /dev/null
+++ b/original/linux/mfd/wcd9xxx/wcd9310_registers.h
@@ -0,0 +1,1117 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef TABLA_CODEC_DIGITAL_H
+
+#define TABLA_CODEC_DIGITAL_H
+#include <linux/mfd/wcd9xxx/wcd9xxx_registers.h>
+
+#define TABLA_A_CHIP_CTL WCD9XXX_A_CHIP_CTL
+#define TABLA_A_CHIP_CTL__POR WCD9XXX_A_CHIP_CTL__POR
+#define TABLA_A_CHIP_STATUS WCD9XXX_A_CHIP_STATUS
+#define TABLA_A_CHIP_STATUS__POR WCD9XXX_A_CHIP_STATUS__POR
+#define TABLA_A_CHIP_ID_BYTE_0 WCD9XXX_A_CHIP_ID_BYTE_0
+#define TABLA_A_CHIP_ID_BYTE_0__POR WCD9XXX_A_CHIP_ID_BYTE_0__POR
+#define TABLA_A_CHIP_ID_BYTE_1 WCD9XXX_A_CHIP_ID_BYTE_1
+#define TABLA_A_CHIP_ID_BYTE_1__POR WCD9XXX_A_CHIP_ID_BYTE_1__POR
+#define TABLA_A_CHIP_ID_BYTE_2 WCD9XXX_A_CHIP_ID_BYTE_2
+#define TABLA_A_CHIP_ID_BYTE_2__POR WCD9XXX_A_CHIP_ID_BYTE_2__POR
+#define TABLA_A_CHIP_ID_BYTE_3 WCD9XXX_A_CHIP_ID_BYTE_3
+#define TABLA_A_CHIP_ID_BYTE_3__POR WCD9XXX_A_CHIP_ID_BYTE_3__POR
+#define TABLA_A_CHIP_VERSION WCD9XXX_A_CHIP_VERSION
+#define TABLA_A_CHIP_VERSION__POR WCD9XXX_A_CHIP_VERSION__POR
+#define TABLA_A_SB_VERSION WCD9XXX_A_SB_VERSION
+#define TABLA_A_SB_VERSION__POR WCD9XXX_A_SB_VERSION__POR
+#define TABLA_A_SLAVE_ID_1 WCD9XXX_A_SLAVE_ID_1
+#define TABLA_A_SLAVE_ID_1__POR WCD9XXX_A_SLAVE_ID_1__POR
+#define TABLA_A_SLAVE_ID_2 WCD9XXX_A_SLAVE_ID_2
+#define TABLA_A_SLAVE_ID_2__POR WCD9XXX_A_SLAVE_ID_2__POR
+#define TABLA_A_SLAVE_ID_3 WCD9XXX_A_SLAVE_ID_3
+#define TABLA_A_SLAVE_ID_3__POR WCD9XXX_A_SLAVE_ID_3__POR
+#define TABLA_A_PIN_CTL_OE0 (0x10)
+#define TABLA_A_PIN_CTL_OE0__POR (0x00000000)
+#define TABLA_A_PIN_CTL_OE1 (0x11)
+#define TABLA_A_PIN_CTL_OE1__POR (0x00000000)
+#define TABLA_A_PIN_CTL_DATA0 (0x12)
+#define TABLA_A_PIN_CTL_DATA0__POR (0x00000000)
+#define TABLA_A_PIN_CTL_DATA1 (0x13)
+#define TABLA_A_PIN_CTL_DATA1__POR (0x00000000)
+#define TABLA_A_HDRIVE_GENERIC (0x18)
+#define TABLA_A_HDRIVE_GENERIC__POR (0x00000000)
+#define TABLA_A_HDRIVE_OVERRIDE (0x19)
+#define TABLA_A_HDRIVE_OVERRIDE__POR (0x00000008)
+#define TABLA_A_ANA_CSR_WAIT_STATE (0x20)
+#define TABLA_A_ANA_CSR_WAIT_STATE__POR (0x00000044)
+#define TABLA_A_PROCESS_MONITOR_CTL0 (0x40)
+#define TABLA_A_PROCESS_MONITOR_CTL0__POR (0x00000080)
+#define TABLA_A_PROCESS_MONITOR_CTL1 (0x41)
+#define TABLA_A_PROCESS_MONITOR_CTL1__POR (0x00000000)
+#define TABLA_A_PROCESS_MONITOR_CTL2 (0x42)
+#define TABLA_A_PROCESS_MONITOR_CTL2__POR (0x00000000)
+#define TABLA_A_PROCESS_MONITOR_CTL3 (0x43)
+#define TABLA_A_PROCESS_MONITOR_CTL3__POR (0x00000001)
+#define TABLA_A_QFUSE_CTL (0x48)
+#define TABLA_A_QFUSE_CTL__POR (0x00000000)
+#define TABLA_A_QFUSE_STATUS (0x49)
+#define TABLA_A_QFUSE_STATUS__POR (0x00000000)
+#define TABLA_A_QFUSE_DATA_OUT0 (0x4A)
+#define TABLA_A_QFUSE_DATA_OUT0__POR (0x00000000)
+#define TABLA_A_QFUSE_DATA_OUT1 (0x4B)
+#define TABLA_A_QFUSE_DATA_OUT1__POR (0x00000000)
+#define TABLA_A_QFUSE_DATA_OUT2 (0x4C)
+#define TABLA_A_QFUSE_DATA_OUT2__POR (0x00000000)
+#define TABLA_A_QFUSE_DATA_OUT3 (0x4D)
+#define TABLA_A_QFUSE_DATA_OUT3__POR (0x00000000)
+#define TABLA_A_CDC_CTL WCD9XXX_A_CDC_CTL
+#define TABLA_A_CDC_CTL__POR WCD9XXX_A_CDC_CTL__POR
+#define TABLA_A_LEAKAGE_CTL WCD9XXX_A_LEAKAGE_CTL
+#define TABLA_A_LEAKAGE_CTL__POR WCD9XXX_A_LEAKAGE_CTL__POR
+#define TABLA_A_INTR_MODE (0x90)
+#define TABLA_A_INTR_MODE__POR (0x00000000)
+#define TABLA_A_INTR_MASK0 (0x94)
+#define TABLA_A_INTR_MASK0__POR (0x000000ff)
+#define TABLA_A_INTR_MASK1 (0x95)
+#define TABLA_A_INTR_MASK1__POR (0x000000ff)
+#define TABLA_A_INTR_MASK2 (0x96)
+#define TABLA_A_INTR_MASK2__POR (0x000000ff)
+#define TABLA_A_INTR_STATUS0 (0x98)
+#define TABLA_A_INTR_STATUS0__POR (0x00000000)
+#define TABLA_A_INTR_STATUS1 (0x99)
+#define TABLA_A_INTR_STATUS1__POR (0x00000000)
+#define TABLA_A_INTR_STATUS2 (0x9A)
+#define TABLA_A_INTR_STATUS2__POR (0x00000000)
+#define TABLA_A_INTR_CLEAR0 (0x9C)
+#define TABLA_A_INTR_CLEAR0__POR (0x00000000)
+#define TABLA_A_INTR_CLEAR1 (0x9D)
+#define TABLA_A_INTR_CLEAR1__POR (0x00000000)
+#define TABLA_A_INTR_CLEAR2 (0x9E)
+#define TABLA_A_INTR_CLEAR2__POR (0x00000000)
+#define TABLA_A_INTR_LEVEL0 (0xA0)
+#define TABLA_A_INTR_LEVEL0__POR (0x00000001)
+#define TABLA_A_INTR_LEVEL1 (0xA1)
+#define TABLA_A_INTR_LEVEL1__POR (0x00000000)
+#define TABLA_A_INTR_LEVEL2 (0xA2)
+#define TABLA_A_INTR_LEVEL2__POR (0x00000000)
+#define TABLA_A_INTR_TEST0 (0xA4)
+#define TABLA_A_INTR_TEST0__POR (0x00000000)
+#define TABLA_A_INTR_TEST1 (0xA5)
+#define TABLA_A_INTR_TEST1__POR (0x00000000)
+#define TABLA_A_INTR_TEST2 (0xA6)
+#define TABLA_A_INTR_TEST2__POR (0x00000000)
+#define TABLA_A_INTR_SET0 (0xA8)
+#define TABLA_A_INTR_SET0__POR (0x00000000)
+#define TABLA_A_INTR_SET1 (0xA9)
+#define TABLA_A_INTR_SET1__POR (0x00000000)
+#define TABLA_A_INTR_SET2 (0xAA)
+#define TABLA_A_INTR_SET2__POR (0x00000000)
+#define TABLA_A_CDC_TX_I2S_SCK_MODE (0xC0)
+#define TABLA_A_CDC_TX_I2S_SCK_MODE__POR (0x00000000)
+#define TABLA_A_CDC_TX_I2S_WS_MODE (0xC1)
+#define TABLA_A_CDC_TX_I2S_WS_MODE__POR (0x00000000)
+#define TABLA_A_CDC_DMIC_DATA0_MODE (0xC4)
+#define TABLA_A_CDC_DMIC_DATA0_MODE__POR (0x00000000)
+#define TABLA_A_CDC_DMIC_CLK0_MODE (0xC5)
+#define TABLA_A_CDC_DMIC_CLK0_MODE__POR (0x00000000)
+#define TABLA_A_CDC_DMIC_DATA1_MODE (0xC6)
+#define TABLA_A_CDC_DMIC_DATA1_MODE__POR (0x00000000)
+#define TABLA_A_CDC_DMIC_CLK1_MODE (0xC7)
+#define TABLA_A_CDC_DMIC_CLK1_MODE__POR (0x00000000)
+#define TABLA_A_CDC_RX_I2S_SCK_MODE (0xC8)
+#define TABLA_A_CDC_RX_I2S_SCK_MODE__POR (0x00000000)
+#define TABLA_A_CDC_RX_I2S_WS_MODE (0xC9)
+#define TABLA_A_CDC_RX_I2S_WS_MODE__POR (0x00000000)
+#define TABLA_A_CDC_DMIC_DATA2_MODE (0xCA)
+#define TABLA_A_CDC_DMIC_DATA2_MODE__POR (0x00000000)
+#define TABLA_A_CDC_DMIC_CLK2_MODE (0xCB)
+#define TABLA_A_CDC_DMIC_CLK2_MODE__POR (0x00000000)
+#define TABLA_A_CDC_INTR_MODE (0xCC)
+#define TABLA_A_CDC_INTR_MODE__POR (0x00000000)
+#define TABLA_A_BIAS_REF_CTL (0x0100)
+#define TABLA_A_BIAS_REF_CTL__POR (0x0000001C)
+#define TABLA_A_BIAS_CENTRAL_BG_CTL (0x0101)
+#define TABLA_A_BIAS_CENTRAL_BG_CTL__POR (0x00000050)
+#define TABLA_A_BIAS_PRECHRG_CTL (0x0102)
+#define TABLA_A_BIAS_PRECHRG_CTL__POR (0x00000007)
+#define TABLA_A_BIAS_CURR_CTL_1 (0x0103)
+#define TABLA_A_BIAS_CURR_CTL_1__POR (0x00000052)
+#define TABLA_A_BIAS_CURR_CTL_2 (0x0104)
+#define TABLA_A_BIAS_CURR_CTL_2__POR (0x00000000)
+#define TABLA_A_BIAS_CONFIG_MODE_BG_CTL (0x0105)
+#define TABLA_A_BIAS_CONFIG_MODE_BG_CTL__POR (0x00000016)
+#define TABLA_A_BIAS_BG_STATUS (0x0106)
+#define TABLA_A_BIAS_BG_STATUS__POR (0x00000000)
+#define TABLA_A_CLK_BUFF_EN1 (0x0108)
+#define TABLA_A_CLK_BUFF_EN1__POR (0x00000004)
+#define TABLA_A_CLK_BUFF_EN2 (0x0109)
+#define TABLA_A_CLK_BUFF_EN2__POR (0x00000002)
+#define TABLA_A_LDO_H_MODE_1 (0x0110)
+#define TABLA_A_LDO_H_MODE_1__POR (0x00000065)
+#define TABLA_A_LDO_H_MODE_2 (0x0111)
+#define TABLA_A_LDO_H_MODE_2__POR (0x000000A8)
+#define TABLA_A_LDO_H_LOOP_CTL (0x0112)
+#define TABLA_A_LDO_H_LOOP_CTL__POR (0x0000006B)
+#define TABLA_A_LDO_H_COMP_1 (0x0113)
+#define TABLA_A_LDO_H_COMP_1__POR (0x00000084)
+#define TABLA_A_LDO_H_COMP_2 (0x0114)
+#define TABLA_A_LDO_H_COMP_2__POR (0x000000E0)
+#define TABLA_A_LDO_H_BIAS_1 (0x0115)
+#define TABLA_A_LDO_H_BIAS_1__POR (0x0000006D)
+#define TABLA_A_LDO_H_BIAS_2 (0x0116)
+#define TABLA_A_LDO_H_BIAS_2__POR (0x000000A5)
+#define TABLA_A_LDO_H_BIAS_3 (0x0117)
+#define TABLA_A_LDO_H_BIAS_3__POR (0x00000060)
+#define TABLA_A_LDO_L_MODE_1 (0x0118)
+#define TABLA_A_LDO_L_MODE_1__POR (0x00000028)
+#define TABLA_A_LDO_L_MODE_2 (0x0119)
+#define TABLA_A_LDO_L_MODE_2__POR (0x000000A8)
+#define TABLA_A_LDO_L_LOOP_CTL (0x011A)
+#define TABLA_A_LDO_L_LOOP_CTL__POR (0x0000006D)
+#define TABLA_A_LDO_L_COMP_1 (0x011B)
+#define TABLA_A_LDO_L_COMP_1__POR (0x00000031)
+#define TABLA_A_LDO_L_COMP_2 (0x011C)
+#define TABLA_A_LDO_L_COMP_2__POR (0x000000A0)
+#define TABLA_A_LDO_L_BIAS_1 (0x011D)
+#define TABLA_A_LDO_L_BIAS_1__POR (0x0000006D)
+#define TABLA_A_LDO_L_BIAS_2 (0x011E)
+#define TABLA_A_LDO_L_BIAS_2__POR (0x00000065)
+#define TABLA_A_LDO_L_BIAS_3 (0x011F)
+#define TABLA_A_LDO_L_BIAS_3__POR (0x00000050)
+#define TABLA_A_MICB_CFILT_1_CTL (0x0128)
+#define TABLA_A_MICB_CFILT_1_CTL__POR (0x00000040)
+#define TABLA_A_MICB_CFILT_1_VAL (0x0129)
+#define TABLA_A_MICB_CFILT_1_VAL__POR (0x00000080)
+#define TABLA_A_MICB_CFILT_1_PRECHRG (0x012A)
+#define TABLA_A_MICB_CFILT_1_PRECHRG__POR (0x00000038)
+#define TABLA_A_MICB_1_CTL (0x012B)
+#define TABLA_A_MICB_1_CTL__POR (0x00000016)
+#define TABLA_A_MICB_1_INT_RBIAS (0x012C)
+#define TABLA_A_MICB_1_INT_RBIAS__POR (0x00000000)
+#define TABLA_A_MICB_1_MBHC (0x012D)
+#define TABLA_A_MICB_1_MBHC__POR (0x00000001)
+#define TABLA_A_MICB_CFILT_2_CTL (0x012E)
+#define TABLA_A_MICB_CFILT_2_CTL__POR (0x00000040)
+#define TABLA_A_MICB_CFILT_2_VAL (0x012F)
+#define TABLA_A_MICB_CFILT_2_VAL__POR (0x00000080)
+#define TABLA_A_MICB_CFILT_2_PRECHRG (0x0130)
+#define TABLA_A_MICB_CFILT_2_PRECHRG__POR (0x00000038)
+#define TABLA_A_MICB_2_CTL (0x0131)
+#define TABLA_A_MICB_2_CTL__POR (0x00000016)
+#define TABLA_A_MICB_2_INT_RBIAS (0x0132)
+#define TABLA_A_MICB_2_INT_RBIAS__POR (0x00000000)
+#define TABLA_A_MICB_2_MBHC (0x0133)
+#define TABLA_A_MICB_2_MBHC__POR (0x00000000)
+#define TABLA_A_MICB_CFILT_3_CTL (0x0134)
+#define TABLA_A_MICB_CFILT_3_CTL__POR (0x00000040)
+#define TABLA_A_MICB_CFILT_3_VAL (0x0135)
+#define TABLA_A_MICB_CFILT_3_VAL__POR (0x00000080)
+#define TABLA_A_MICB_CFILT_3_PRECHRG (0x0136)
+#define TABLA_A_MICB_CFILT_3_PRECHRG__POR (0x00000038)
+#define TABLA_A_MICB_3_CTL (0x0137)
+#define TABLA_A_MICB_3_CTL__POR (0x00000016)
+#define TABLA_A_MICB_3_INT_RBIAS (0x0138)
+#define TABLA_A_MICB_3_INT_RBIAS__POR (0x00000000)
+#define TABLA_A_MICB_3_MBHC (0x0139)
+#define TABLA_A_MICB_3_MBHC__POR (0x00000000)
+#define TABLA_1_A_MICB_4_CTL (0x013A)
+#define TABLA_2_A_MICB_4_CTL (0x013D)
+#define TABLA_A_MICB_4_CTL__POR (0x00000016)
+#define TABLA_1_A_MICB_4_INT_RBIAS (0x013B)
+#define TABLA_2_A_MICB_4_INT_RBIAS (0x013E)
+#define TABLA_A_MICB_4_INT_RBIAS__POR (0x00000000)
+#define TABLA_1_A_MICB_4_MBHC (0x013C)
+#define TABLA_2_A_MICB_4_MBHC (0x013F)
+#define TABLA_A_MICB_4_MBHC__POR (0x00000001)
+#define TABLA_A_TX_COM_BIAS (0x014C)
+#define TABLA_A_TX_COM_BIAS__POR (0x000000E0)
+#define TABLA_A_MBHC_SCALING_MUX_1 (0x014E)
+#define TABLA_A_MBHC_SCALING_MUX_1__POR (0x00000000)
+#define TABLA_A_MBHC_SCALING_MUX_2 (0x014F)
+#define TABLA_A_MBHC_SCALING_MUX_2__POR (0x00000080)
+#define TABLA_A_TX_SUP_SWITCH_CTRL_1 (0x0151)
+#define TABLA_A_TX_SUP_SWITCH_CTRL_1__POR (0x00000000)
+#define TABLA_A_TX_SUP_SWITCH_CTRL_2 (0x0152)
+#define TABLA_A_TX_SUP_SWITCH_CTRL_2__POR (0x00000080)
+#define TABLA_A_TX_1_2_EN (0x0153)
+#define TABLA_A_TX_1_2_EN__POR (0x00000000)
+#define TABLA_A_TX_1_2_TEST_EN (0x0154)
+#define TABLA_A_TX_1_2_TEST_EN__POR (0x000000CC)
+#define TABLA_A_TX_1_2_ADC_CH1 (0x0155)
+#define TABLA_A_TX_1_2_ADC_CH1__POR (0x00000044)
+#define TABLA_A_TX_1_2_ADC_CH2 (0x0156)
+#define TABLA_A_TX_1_2_ADC_CH2__POR (0x00000044)
+#define TABLA_A_TX_1_2_ATEST_REFCTRL (0x0157)
+#define TABLA_A_TX_1_2_ATEST_REFCTRL__POR (0x00000000)
+#define TABLA_A_TX_1_2_TEST_CTL (0x0158)
+#define TABLA_A_TX_1_2_TEST_CTL__POR (0x00000038)
+#define TABLA_A_TX_1_2_TEST_BLOCK_EN (0x0159)
+#define TABLA_A_TX_1_2_TEST_BLOCK_EN__POR (0x000000FF)
+#define TABLA_A_TX_1_2_TXFE_CLKDIV (0x015A)
+#define TABLA_A_TX_1_2_TXFE_CLKDIV__POR (0x000000EE)
+#define TABLA_A_TX_1_2_SAR_ERR_CH1 (0x015B)
+#define TABLA_A_TX_1_2_SAR_ERR_CH1__POR (0x00000000)
+#define TABLA_A_TX_1_2_SAR_ERR_CH2 (0x015C)
+#define TABLA_A_TX_1_2_SAR_ERR_CH2__POR (0x00000000)
+#define TABLA_A_TX_3_4_EN (0x015D)
+#define TABLA_A_TX_3_4_EN__POR (0x00000000)
+#define TABLA_A_TX_3_4_TEST_EN (0x015E)
+#define TABLA_A_TX_3_4_TEST_EN__POR (0x000000CC)
+#define TABLA_A_TX_3_4_ADC_CH3 (0x015F)
+#define TABLA_A_TX_3_4_ADC_CH3__POR (0x00000044)
+#define TABLA_A_TX_3_4_ADC_CH4 (0x0160)
+#define TABLA_A_TX_3_4_ADC_CH4__POR (0x00000044)
+#define TABLA_A_TX_3_4_ATEST_REFCTRL (0x0161)
+#define TABLA_A_TX_3_4_ATEST_REFCTRL__POR (0x00000000)
+#define TABLA_A_TX_3_4_TEST_CTL (0x0162)
+#define TABLA_A_TX_3_4_TEST_CTL__POR (0x00000038)
+#define TABLA_A_TX_3_4_TEST_BLOCK_EN (0x0163)
+#define TABLA_A_TX_3_4_TEST_BLOCK_EN__POR (0x000000FF)
+#define TABLA_A_TX_3_4_TXFE_CKDIV (0x0164)
+#define TABLA_A_TX_3_4_TXFE_CKDIV__POR (0x000000EE)
+#define TABLA_A_TX_3_4_SAR_ERR_CH3 (0x0165)
+#define TABLA_A_TX_3_4_SAR_ERR_CH3__POR (0x00000000)
+#define TABLA_A_TX_3_4_SAR_ERR_CH4 (0x0166)
+#define TABLA_A_TX_3_4_SAR_ERR_CH4__POR (0x00000000)
+#define TABLA_A_TX_5_6_EN (0x0167)
+#define TABLA_A_TX_5_6_EN__POR (0x00000011)
+#define TABLA_A_TX_5_6_TEST_EN (0x0168)
+#define TABLA_A_TX_5_6_TEST_EN__POR (0x000000CC)
+#define TABLA_A_TX_5_6_ADC_CH5 (0x0169)
+#define TABLA_A_TX_5_6_ADC_CH5__POR (0x00000044)
+#define TABLA_A_TX_5_6_ADC_CH6 (0x016A)
+#define TABLA_A_TX_5_6_ADC_CH6__POR (0x00000044)
+#define TABLA_A_TX_5_6_ATEST_REFCTRL (0x016B)
+#define TABLA_A_TX_5_6_ATEST_REFCTRL__POR (0x00000000)
+#define TABLA_A_TX_5_6_TEST_CTL (0x016C)
+#define TABLA_A_TX_5_6_TEST_CTL__POR (0x00000038)
+#define TABLA_A_TX_5_6_TEST_BLOCK_EN (0x016D)
+#define TABLA_A_TX_5_6_TEST_BLOCK_EN__POR (0x000000FF)
+#define TABLA_A_TX_5_6_TXFE_CKDIV (0x016E)
+#define TABLA_A_TX_5_6_TXFE_CKDIV__POR (0x000000EE)
+#define TABLA_A_TX_5_6_SAR_ERR_CH5 (0x016F)
+#define TABLA_A_TX_5_6_SAR_ERR_CH5__POR (0x00000000)
+#define TABLA_A_TX_5_6_SAR_ERR_CH6 (0x0170)
+#define TABLA_A_TX_5_6_SAR_ERR_CH6__POR (0x00000000)
+#define TABLA_A_TX_7_MBHC_EN (0x0171)
+#define TABLA_A_TX_7_MBHC_EN__POR (0x0000000C)
+#define TABLA_A_TX_7_MBHC_ATEST_REFCTRL (0x0172)
+#define TABLA_A_TX_7_MBHC_ATEST_REFCTRL__POR (0x00000000)
+#define TABLA_A_TX_7_MBHC_ADC (0x0173)
+#define TABLA_A_TX_7_MBHC_ADC__POR (0x00000044)
+#define TABLA_A_TX_7_MBHC_TEST_CTL (0x0174)
+#define TABLA_A_TX_7_MBHC_TEST_CTL__POR (0x00000038)
+#define TABLA_A_TX_7_MBHC_SAR_ERR (0x0175)
+#define TABLA_A_TX_7_MBHC_SAR_ERR__POR (0x00000000)
+#define TABLA_A_TX_7_TXFE_CLKDIV (0x0176)
+#define TABLA_A_TX_7_TXFE_CLKDIV__POR (0x0000001C)
+#define TABLA_A_AUX_COM_CTL (0x0180)
+#define TABLA_A_AUX_COM_CTL__POR (0x00000034)
+#define TABLA_A_AUX_COM_ATEST (0x0181)
+#define TABLA_A_AUX_COM_ATEST__POR (0x00000000)
+#define TABLA_A_AUX_L_EN (0x0182)
+#define TABLA_A_AUX_L_EN__POR (0x00000000)
+#define TABLA_A_AUX_L_GAIN (0x0183)
+#define TABLA_A_AUX_L_GAIN__POR (0x0000001F)
+#define TABLA_A_AUX_L_PA_CONN (0x0184)
+#define TABLA_A_AUX_L_PA_CONN__POR (0x00000000)
+#define TABLA_A_AUX_L_PA_CONN_INV (0x0185)
+#define TABLA_A_AUX_L_PA_CONN_INV__POR (0x00000000)
+#define TABLA_A_AUX_R_EN (0x0186)
+#define TABLA_A_AUX_R_EN__POR (0x00000000)
+#define TABLA_A_AUX_R_GAIN (0x0187)
+#define TABLA_A_AUX_R_GAIN__POR (0x0000001F)
+#define TABLA_A_AUX_R_PA_CONN (0x0188)
+#define TABLA_A_AUX_R_PA_CONN__POR (0x00000000)
+#define TABLA_A_AUX_R_PA_CONN_INV (0x0189)
+#define TABLA_A_AUX_R_PA_CONN_INV__POR (0x00000000)
+#define TABLA_A_CP_EN (0x0192)
+#define TABLA_A_CP_EN__POR (0x000000E6)
+#define TABLA_A_CP_CLK (0x0193)
+#define TABLA_A_CP_CLK__POR (0x00000029)
+#define TABLA_A_CP_STATIC (0x0194)
+#define TABLA_A_CP_STATIC__POR (0x00000010)
+#define TABLA_A_CP_DCC1 (0x0195)
+#define TABLA_A_CP_DCC1__POR (0x00000052)
+#define TABLA_A_CP_DCC3 (0x0196)
+#define TABLA_A_CP_DCC3__POR (0x00000001)
+#define TABLA_A_CP_ATEST (0x0197)
+#define TABLA_A_CP_ATEST__POR (0x00000000)
+#define TABLA_A_CP_DTEST (0x0198)
+#define TABLA_A_CP_DTEST__POR (0x00000000)
+#define TABLA_A_RX_COM_TIMER_DIV (0x019E)
+#define TABLA_A_RX_COM_TIMER_DIV__POR (0x000000E8)
+#define TABLA_A_RX_COM_OCP_CTL (0x019F)
+#define TABLA_A_RX_COM_OCP_CTL__POR (0x0000001F)
+#define TABLA_A_RX_COM_OCP_COUNT (0x01A0)
+#define TABLA_A_RX_COM_OCP_COUNT__POR (0x00000077)
+#define TABLA_A_RX_COM_DAC_CTL (0x01A1)
+#define TABLA_A_RX_COM_DAC_CTL__POR (0x00000000)
+#define TABLA_A_RX_COM_BIAS (0x01A2)
+#define TABLA_A_RX_COM_BIAS__POR (0x00000000)
+#define TABLA_A_RX_HPH_BIAS_PA (0x01A6)
+#define TABLA_A_RX_HPH_BIAS_PA__POR (0x000000AA)
+#define TABLA_A_RX_HPH_BIAS_LDO (0x01A7)
+#define TABLA_A_RX_HPH_BIAS_LDO__POR (0x00000086)
+#define TABLA_A_RX_HPH_BIAS_CNP (0x01A8)
+#define TABLA_A_RX_HPH_BIAS_CNP__POR (0x0000008A)
+#define TABLA_A_RX_HPH_BIAS_WG (0x01A9)
+#define TABLA_A_RX_HPH_BIAS_WG__POR (0x00000060)
+#define TABLA_A_RX_HPH_OCP_CTL (0x01AA)
+#define TABLA_A_RX_HPH_OCP_CTL__POR (0x000000E8)
+#define TABLA_A_RX_HPH_CNP_EN (0x01AB)
+#define TABLA_A_RX_HPH_CNP_EN__POR (0x00000080)
+#define TABLA_A_RX_HPH_CNP_WG_CTL (0x01AC)
+#define TABLA_A_RX_HPH_CNP_WG_CTL__POR (0x000000DC)
+#define TABLA_A_RX_HPH_CNP_WG_TIME (0x01AD)
+#define TABLA_A_RX_HPH_CNP_WG_TIME__POR (0x00000028)
+#define TABLA_A_RX_HPH_L_GAIN (0x01AE)
+#define TABLA_A_RX_HPH_L_GAIN__POR (0x00000000)
+#define TABLA_A_RX_HPH_L_TEST (0x01AF)
+#define TABLA_A_RX_HPH_L_TEST__POR (0x00000001)
+#define TABLA_A_RX_HPH_L_PA_CTL (0x01B0)
+#define TABLA_A_RX_HPH_L_PA_CTL__POR (0x00000040)
+#define TABLA_A_RX_HPH_L_DAC_CTL (0x01B1)
+#define TABLA_A_RX_HPH_L_DAC_CTL__POR (0x00000000)
+#define TABLA_A_RX_HPH_L_ATEST (0x01B2)
+#define TABLA_A_RX_HPH_L_ATEST__POR (0x00000000)
+#define TABLA_A_RX_HPH_L_STATUS (0x01B3)
+#define TABLA_A_RX_HPH_L_STATUS__POR (0x00000004)
+#define TABLA_A_RX_HPH_R_GAIN (0x01B4)
+#define TABLA_A_RX_HPH_R_GAIN__POR (0x00000000)
+#define TABLA_A_RX_HPH_R_TEST (0x01B5)
+#define TABLA_A_RX_HPH_R_TEST__POR (0x00000001)
+#define TABLA_A_RX_HPH_R_PA_CTL (0x01B6)
+#define TABLA_A_RX_HPH_R_PA_CTL__POR (0x00000040)
+#define TABLA_A_RX_HPH_R_DAC_CTL (0x01B7)
+#define TABLA_A_RX_HPH_R_DAC_CTL__POR (0x00000000)
+#define TABLA_A_RX_HPH_R_ATEST (0x01B8)
+#define TABLA_A_RX_HPH_R_ATEST__POR (0x00000000)
+#define TABLA_A_RX_HPH_R_STATUS (0x01B9)
+#define TABLA_A_RX_HPH_R_STATUS__POR (0x00000004)
+#define TABLA_A_RX_EAR_BIAS_PA (0x01BA)
+#define TABLA_A_RX_EAR_BIAS_PA__POR (0x000000AA)
+#define TABLA_A_RX_EAR_BIAS_CMBUFF (0x01BB)
+#define TABLA_A_RX_EAR_BIAS_CMBUFF__POR (0x000000A0)
+#define TABLA_A_RX_EAR_EN (0x01BC)
+#define TABLA_A_RX_EAR_EN__POR (0x00000000)
+#define TABLA_A_RX_EAR_GAIN (0x01BD)
+#define TABLA_A_RX_EAR_GAIN__POR (0x00000008)
+#define TABLA_A_RX_EAR_CMBUFF (0x01BE)
+#define TABLA_A_RX_EAR_CMBUFF__POR (0x00000000)
+#define TABLA_A_RX_EAR_ICTL (0x01BF)
+#define TABLA_A_RX_EAR_ICTL__POR (0x00000040)
+#define TABLA_A_RX_EAR_CCOMP (0x01C0)
+#define TABLA_A_RX_EAR_CCOMP__POR (0x00000008)
+#define TABLA_A_RX_EAR_VCM (0x01C1)
+#define TABLA_A_RX_EAR_VCM__POR (0x00000000)
+#define TABLA_A_RX_EAR_CNP (0x01C2)
+#define TABLA_A_RX_EAR_CNP__POR (0x00000080)
+#define TABLA_A_RX_EAR_ATEST (0x01C3)
+#define TABLA_A_RX_EAR_ATEST__POR (0x00000000)
+#define TABLA_A_RX_EAR_STATUS (0x01C5)
+#define TABLA_A_RX_EAR_STATUS__POR (0x00000004)
+#define TABLA_A_RX_LINE_BIAS_PA (0x01C6)
+#define TABLA_A_RX_LINE_BIAS_PA__POR (0x000000AA)
+#define TABLA_A_RX_LINE_BIAS_DAC (0x01C7)
+#define TABLA_A_RX_LINE_BIAS_DAC__POR (0x000000A0)
+#define TABLA_A_RX_LINE_BIAS_CNP (0x01C8)
+#define TABLA_A_RX_LINE_BIAS_CNP__POR (0x0000003A)
+#define TABLA_A_RX_LINE_COM (0x01C9)
+#define TABLA_A_RX_LINE_COM__POR (0x00000000)
+#define TABLA_A_RX_LINE_CNP_EN (0x01CA)
+#define TABLA_A_RX_LINE_CNP_EN__POR (0x00000080)
+#define TABLA_A_RX_LINE_CNP_WG_CTL (0x01CB)
+#define TABLA_A_RX_LINE_CNP_WG_CTL__POR (0x0000001C)
+#define TABLA_A_RX_LINE_CNP_WG_TIME (0x01CC)
+#define TABLA_A_RX_LINE_CNP_WG_TIME__POR (0x00000064)
+#define TABLA_A_RX_LINE_1_GAIN (0x01CD)
+#define TABLA_A_RX_LINE_1_GAIN__POR (0x00000000)
+#define TABLA_A_RX_LINE_1_TEST (0x01CE)
+#define TABLA_A_RX_LINE_1_TEST__POR (0x00000000)
+#define TABLA_A_RX_LINE_1_DAC_CTL (0x01CF)
+#define TABLA_A_RX_LINE_1_DAC_CTL__POR (0x0000000C)
+#define TABLA_A_RX_LINE_1_STATUS (0x01D0)
+#define TABLA_A_RX_LINE_1_STATUS__POR (0x00000000)
+#define TABLA_A_RX_LINE_2_GAIN (0x01D1)
+#define TABLA_A_RX_LINE_2_GAIN__POR (0x00000000)
+#define TABLA_A_RX_LINE_2_TEST (0x01D2)
+#define TABLA_A_RX_LINE_2_TEST__POR (0x00000000)
+#define TABLA_A_RX_LINE_2_DAC_CTL (0x01D3)
+#define TABLA_A_RX_LINE_2_DAC_CTL__POR (0x0000000C)
+#define TABLA_A_RX_LINE_2_STATUS (0x01D4)
+#define TABLA_A_RX_LINE_2_STATUS__POR (0x00000000)
+#define TABLA_A_RX_LINE_3_GAIN (0x01D5)
+#define TABLA_A_RX_LINE_3_GAIN__POR (0x00000000)
+#define TABLA_A_RX_LINE_3_TEST (0x01D6)
+#define TABLA_A_RX_LINE_3_TEST__POR (0x00000000)
+#define TABLA_A_RX_LINE_3_DAC_CTL (0x01D7)
+#define TABLA_A_RX_LINE_3_DAC_CTL__POR (0x0000000C)
+#define TABLA_A_RX_LINE_3_STATUS (0x01D8)
+#define TABLA_A_RX_LINE_3_STATUS__POR (0x00000000)
+#define TABLA_A_RX_LINE_4_GAIN (0x01D9)
+#define TABLA_A_RX_LINE_4_GAIN__POR (0x00000000)
+#define TABLA_A_RX_LINE_4_TEST (0x01DA)
+#define TABLA_A_RX_LINE_4_TEST__POR (0x00000000)
+#define TABLA_A_RX_LINE_4_DAC_CTL (0x01DB)
+#define TABLA_A_RX_LINE_4_DAC_CTL__POR (0x0000000C)
+#define TABLA_A_RX_LINE_4_STATUS (0x01DC)
+#define TABLA_A_RX_LINE_4_STATUS__POR (0x00000000)
+#define TABLA_A_RX_LINE_5_GAIN (0x01DD)
+#define TABLA_A_RX_LINE_5_GAIN__POR (0x00000000)
+#define TABLA_A_RX_LINE_5_TEST (0x01DE)
+#define TABLA_A_RX_LINE_5_TEST__POR (0x00000000)
+#define TABLA_A_RX_LINE_5_DAC_CTL (0x01DF)
+#define TABLA_A_RX_LINE_5_DAC_CTL__POR (0x0000000C)
+#define TABLA_A_RX_LINE_5_STATUS (0x01E0)
+#define TABLA_A_RX_LINE_5_STATUS__POR (0x00000000)
+#define TABLA_A_RX_LINE_CNP_DBG (0x01EC)
+#define TABLA_A_RX_LINE_CNP_DBG__POR (0x00000000)
+#define TABLA_A_MBHC_HPH (0x01ED)
+#define TABLA_A_MBHC_HPH__POR (0x00000048)
+#define TABLA_A_CONFIG_MODE_FREQ (0x01F7)
+#define TABLA_A_CONFIG_MODE_FREQ__POR (0x00000047)
+#define TABLA_A_CONFIG_MODE_TEST (0x01F8)
+#define TABLA_A_CONFIG_MODE_TEST__POR (0x0000000A)
+#define TABLA_A_CONFIG_MODE_STATUS (0x01F9)
+#define TABLA_A_CONFIG_MODE_STATUS__POR (0x0000001C)
+#define TABLA_A_CONFIG_MODE_TUNER (0x01FA)
+#define TABLA_A_CONFIG_MODE_TUNER__POR (0x00000000)
+#define TABLA_A_CDC_ANC1_CTL (0x00000200)
+#define TABLA_A_CDC_ANC1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_ANC2_CTL (0x00000280)
+#define TABLA_A_CDC_ANC2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_ANC1_SHIFT (0x00000201)
+#define TABLA_A_CDC_ANC1_SHIFT__POR (0x00000000)
+#define TABLA_A_CDC_ANC2_SHIFT (0x00000281)
+#define TABLA_A_CDC_ANC2_SHIFT__POR (0x00000000)
+#define TABLA_A_CDC_ANC1_FILT1_B1_CTL (0x00000202)
+#define TABLA_A_CDC_ANC1_FILT1_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_ANC2_FILT1_B1_CTL (0x00000282)
+#define TABLA_A_CDC_ANC2_FILT1_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_ANC1_FILT1_B2_CTL (0x00000203)
+#define TABLA_A_CDC_ANC1_FILT1_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_ANC2_FILT1_B2_CTL (0x00000283)
+#define TABLA_A_CDC_ANC2_FILT1_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_ANC1_FILT1_B3_CTL (0x00000204)
+#define TABLA_A_CDC_ANC1_FILT1_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_ANC2_FILT1_B3_CTL (0x00000284)
+#define TABLA_A_CDC_ANC2_FILT1_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_ANC1_FILT1_B4_CTL (0x00000205)
+#define TABLA_A_CDC_ANC1_FILT1_B4_CTL__POR (0x00000000)
+#define TABLA_A_CDC_ANC2_FILT1_B4_CTL (0x00000285)
+#define TABLA_A_CDC_ANC2_FILT1_B4_CTL__POR (0x00000000)
+#define TABLA_A_CDC_ANC1_FILT2_B1_CTL (0x00000206)
+#define TABLA_A_CDC_ANC1_FILT2_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_ANC2_FILT2_B1_CTL (0x00000286)
+#define TABLA_A_CDC_ANC2_FILT2_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_ANC1_FILT2_B2_CTL (0x00000207)
+#define TABLA_A_CDC_ANC1_FILT2_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_ANC2_FILT2_B2_CTL (0x00000287)
+#define TABLA_A_CDC_ANC2_FILT2_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_ANC1_FILT2_B3_CTL (0x00000208)
+#define TABLA_A_CDC_ANC1_FILT2_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_ANC2_FILT2_B3_CTL (0x00000288)
+#define TABLA_A_CDC_ANC2_FILT2_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_ANC1_SPARE (0x00000209)
+#define TABLA_A_CDC_ANC1_SPARE__POR (0x00000000)
+#define TABLA_A_CDC_ANC2_SPARE (0x00000289)
+#define TABLA_A_CDC_ANC2_SPARE__POR (0x00000000)
+#define TABLA_A_CDC_ANC1_FILT3_CTL (0x0000020A)
+#define TABLA_A_CDC_ANC1_FILT3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_ANC2_FILT3_CTL (0x0000028A)
+#define TABLA_A_CDC_ANC2_FILT3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_ANC1_FILT4_CTL (0x0000020B)
+#define TABLA_A_CDC_ANC1_FILT4_CTL__POR (0x00000000)
+#define TABLA_A_CDC_ANC2_FILT4_CTL (0x0000028B)
+#define TABLA_A_CDC_ANC2_FILT4_CTL__POR (0x00000000)
+#define TABLA_A_CDC_TX1_VOL_CTL_TIMER (0x00000220)
+#define TABLA_A_CDC_TX1_VOL_CTL_TIMER__POR (0x00000000)
+#define TABLA_A_CDC_TX2_VOL_CTL_TIMER (0x00000228)
+#define TABLA_A_CDC_TX2_VOL_CTL_TIMER__POR (0x00000000)
+#define TABLA_A_CDC_TX3_VOL_CTL_TIMER (0x00000230)
+#define TABLA_A_CDC_TX3_VOL_CTL_TIMER__POR (0x00000000)
+#define TABLA_A_CDC_TX4_VOL_CTL_TIMER (0x00000238)
+#define TABLA_A_CDC_TX4_VOL_CTL_TIMER__POR (0x00000000)
+#define TABLA_A_CDC_TX5_VOL_CTL_TIMER (0x00000240)
+#define TABLA_A_CDC_TX5_VOL_CTL_TIMER__POR (0x00000000)
+#define TABLA_A_CDC_TX6_VOL_CTL_TIMER (0x00000248)
+#define TABLA_A_CDC_TX6_VOL_CTL_TIMER__POR (0x00000000)
+#define TABLA_A_CDC_TX7_VOL_CTL_TIMER (0x00000250)
+#define TABLA_A_CDC_TX7_VOL_CTL_TIMER__POR (0x00000000)
+#define TABLA_A_CDC_TX8_VOL_CTL_TIMER (0x00000258)
+#define TABLA_A_CDC_TX8_VOL_CTL_TIMER__POR (0x00000000)
+#define TABLA_A_CDC_TX9_VOL_CTL_TIMER (0x00000260)
+#define TABLA_A_CDC_TX9_VOL_CTL_TIMER__POR (0x00000000)
+#define TABLA_A_CDC_TX10_VOL_CTL_TIMER (0x00000268)
+#define TABLA_A_CDC_TX10_VOL_CTL_TIMER__POR (0x00000000)
+#define TABLA_A_CDC_TX1_VOL_CTL_GAIN (0x00000221)
+#define TABLA_A_CDC_TX1_VOL_CTL_GAIN__POR (0x00000000)
+#define TABLA_A_CDC_TX2_VOL_CTL_GAIN (0x00000229)
+#define TABLA_A_CDC_TX2_VOL_CTL_GAIN__POR (0x00000000)
+#define TABLA_A_CDC_TX3_VOL_CTL_GAIN (0x00000231)
+#define TABLA_A_CDC_TX3_VOL_CTL_GAIN__POR (0x00000000)
+#define TABLA_A_CDC_TX4_VOL_CTL_GAIN (0x00000239)
+#define TABLA_A_CDC_TX4_VOL_CTL_GAIN__POR (0x00000000)
+#define TABLA_A_CDC_TX5_VOL_CTL_GAIN (0x00000241)
+#define TABLA_A_CDC_TX5_VOL_CTL_GAIN__POR (0x00000000)
+#define TABLA_A_CDC_TX6_VOL_CTL_GAIN (0x00000249)
+#define TABLA_A_CDC_TX6_VOL_CTL_GAIN__POR (0x00000000)
+#define TABLA_A_CDC_TX7_VOL_CTL_GAIN (0x00000251)
+#define TABLA_A_CDC_TX7_VOL_CTL_GAIN__POR (0x00000000)
+#define TABLA_A_CDC_TX8_VOL_CTL_GAIN (0x00000259)
+#define TABLA_A_CDC_TX8_VOL_CTL_GAIN__POR (0x00000000)
+#define TABLA_A_CDC_TX9_VOL_CTL_GAIN (0x00000261)
+#define TABLA_A_CDC_TX9_VOL_CTL_GAIN__POR (0x00000000)
+#define TABLA_A_CDC_TX10_VOL_CTL_GAIN (0x00000269)
+#define TABLA_A_CDC_TX10_VOL_CTL_GAIN__POR (0x00000000)
+#define TABLA_A_CDC_TX1_VOL_CTL_CFG (0x00000222)
+#define TABLA_A_CDC_TX1_VOL_CTL_CFG__POR (0x00000000)
+#define TABLA_A_CDC_TX2_VOL_CTL_CFG (0x0000022A)
+#define TABLA_A_CDC_TX2_VOL_CTL_CFG__POR (0x00000000)
+#define TABLA_A_CDC_TX3_VOL_CTL_CFG (0x00000232)
+#define TABLA_A_CDC_TX3_VOL_CTL_CFG__POR (0x00000000)
+#define TABLA_A_CDC_TX4_VOL_CTL_CFG (0x0000023A)
+#define TABLA_A_CDC_TX4_VOL_CTL_CFG__POR (0x00000000)
+#define TABLA_A_CDC_TX5_VOL_CTL_CFG (0x00000242)
+#define TABLA_A_CDC_TX5_VOL_CTL_CFG__POR (0x00000000)
+#define TABLA_A_CDC_TX6_VOL_CTL_CFG (0x0000024A)
+#define TABLA_A_CDC_TX6_VOL_CTL_CFG__POR (0x00000000)
+#define TABLA_A_CDC_TX7_VOL_CTL_CFG (0x00000252)
+#define TABLA_A_CDC_TX7_VOL_CTL_CFG__POR (0x00000000)
+#define TABLA_A_CDC_TX8_VOL_CTL_CFG (0x0000025A)
+#define TABLA_A_CDC_TX8_VOL_CTL_CFG__POR (0x00000000)
+#define TABLA_A_CDC_TX9_VOL_CTL_CFG (0x00000262)
+#define TABLA_A_CDC_TX9_VOL_CTL_CFG__POR (0x00000000)
+#define TABLA_A_CDC_TX10_VOL_CTL_CFG (0x0000026A)
+#define TABLA_A_CDC_TX10_VOL_CTL_CFG__POR (0x00000000)
+#define TABLA_A_CDC_TX1_MUX_CTL (0x00000223)
+#define TABLA_A_CDC_TX1_MUX_CTL__POR (0x00000008)
+#define TABLA_A_CDC_TX2_MUX_CTL (0x0000022B)
+#define TABLA_A_CDC_TX2_MUX_CTL__POR (0x00000008)
+#define TABLA_A_CDC_TX3_MUX_CTL (0x00000233)
+#define TABLA_A_CDC_TX3_MUX_CTL__POR (0x00000008)
+#define TABLA_A_CDC_TX4_MUX_CTL (0x0000023B)
+#define TABLA_A_CDC_TX4_MUX_CTL__POR (0x00000008)
+#define TABLA_A_CDC_TX5_MUX_CTL (0x00000243)
+#define TABLA_A_CDC_TX5_MUX_CTL__POR (0x00000008)
+#define TABLA_A_CDC_TX6_MUX_CTL (0x0000024B)
+#define TABLA_A_CDC_TX6_MUX_CTL__POR (0x00000008)
+#define TABLA_A_CDC_TX7_MUX_CTL (0x00000253)
+#define TABLA_A_CDC_TX7_MUX_CTL__POR (0x00000008)
+#define TABLA_A_CDC_TX8_MUX_CTL (0x0000025B)
+#define TABLA_A_CDC_TX8_MUX_CTL__POR (0x00000008)
+#define TABLA_A_CDC_TX9_MUX_CTL (0x00000263)
+#define TABLA_A_CDC_TX9_MUX_CTL__POR (0x00000008)
+#define TABLA_A_CDC_TX10_MUX_CTL (0x0000026B)
+#define TABLA_A_CDC_TX10_MUX_CTL__POR (0x00000008)
+#define TABLA_A_CDC_TX1_CLK_FS_CTL (0x00000224)
+#define TABLA_A_CDC_TX1_CLK_FS_CTL__POR (0x00000003)
+#define TABLA_A_CDC_TX2_CLK_FS_CTL (0x0000022C)
+#define TABLA_A_CDC_TX2_CLK_FS_CTL__POR (0x00000003)
+#define TABLA_A_CDC_TX3_CLK_FS_CTL (0x00000234)
+#define TABLA_A_CDC_TX3_CLK_FS_CTL__POR (0x00000003)
+#define TABLA_A_CDC_TX4_CLK_FS_CTL (0x0000023C)
+#define TABLA_A_CDC_TX4_CLK_FS_CTL__POR (0x00000003)
+#define TABLA_A_CDC_TX5_CLK_FS_CTL (0x00000244)
+#define TABLA_A_CDC_TX5_CLK_FS_CTL__POR (0x00000003)
+#define TABLA_A_CDC_TX6_CLK_FS_CTL (0x0000024C)
+#define TABLA_A_CDC_TX6_CLK_FS_CTL__POR (0x00000003)
+#define TABLA_A_CDC_TX7_CLK_FS_CTL (0x00000254)
+#define TABLA_A_CDC_TX7_CLK_FS_CTL__POR (0x00000003)
+#define TABLA_A_CDC_TX8_CLK_FS_CTL (0x0000025C)
+#define TABLA_A_CDC_TX8_CLK_FS_CTL__POR (0x00000003)
+#define TABLA_A_CDC_TX9_CLK_FS_CTL (0x00000264)
+#define TABLA_A_CDC_TX9_CLK_FS_CTL__POR (0x00000003)
+#define TABLA_A_CDC_TX10_CLK_FS_CTL (0x0000026C)
+#define TABLA_A_CDC_TX10_CLK_FS_CTL__POR (0x00000003)
+#define TABLA_A_CDC_TX1_DMIC_CTL (0x00000225)
+#define TABLA_A_CDC_TX1_DMIC_CTL__POR (0x00000000)
+#define TABLA_A_CDC_TX2_DMIC_CTL (0x0000022D)
+#define TABLA_A_CDC_TX2_DMIC_CTL__POR (0x00000000)
+#define TABLA_A_CDC_TX3_DMIC_CTL (0x00000235)
+#define TABLA_A_CDC_TX3_DMIC_CTL__POR (0x00000000)
+#define TABLA_A_CDC_TX4_DMIC_CTL (0x0000023D)
+#define TABLA_A_CDC_TX4_DMIC_CTL__POR (0x00000000)
+#define TABLA_A_CDC_TX5_DMIC_CTL (0x00000245)
+#define TABLA_A_CDC_TX5_DMIC_CTL__POR (0x00000000)
+#define TABLA_A_CDC_TX6_DMIC_CTL (0x0000024D)
+#define TABLA_A_CDC_TX6_DMIC_CTL__POR (0x00000000)
+#define TABLA_A_CDC_TX7_DMIC_CTL (0x00000255)
+#define TABLA_A_CDC_TX7_DMIC_CTL__POR (0x00000000)
+#define TABLA_A_CDC_TX8_DMIC_CTL (0x0000025D)
+#define TABLA_A_CDC_TX8_DMIC_CTL__POR (0x00000000)
+#define TABLA_A_CDC_TX9_DMIC_CTL (0x00000265)
+#define TABLA_A_CDC_TX9_DMIC_CTL__POR (0x00000000)
+#define TABLA_A_CDC_TX10_DMIC_CTL (0x0000026D)
+#define TABLA_A_CDC_TX10_DMIC_CTL__POR (0x00000000)
+#define TABLA_A_CDC_SRC1_PDA_CFG (0x000002A0)
+#define TABLA_A_CDC_SRC1_PDA_CFG__POR (0x00000000)
+#define TABLA_A_CDC_SRC2_PDA_CFG (0x000002A8)
+#define TABLA_A_CDC_SRC2_PDA_CFG__POR (0x00000000)
+#define TABLA_A_CDC_SRC1_FS_CTL (0x000002A1)
+#define TABLA_A_CDC_SRC1_FS_CTL__POR (0x0000001b)
+#define TABLA_A_CDC_SRC2_FS_CTL (0x000002A9)
+#define TABLA_A_CDC_SRC2_FS_CTL__POR (0x0000001b)
+#define TABLA_A_CDC_RX1_B1_CTL (0x000002B0)
+#define TABLA_A_CDC_RX1_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX2_B1_CTL (0x000002B8)
+#define TABLA_A_CDC_RX2_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX3_B1_CTL (0x000002C0)
+#define TABLA_A_CDC_RX3_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX4_B1_CTL (0x000002C8)
+#define TABLA_A_CDC_RX4_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX5_B1_CTL (0x000002D0)
+#define TABLA_A_CDC_RX5_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX6_B1_CTL (0x000002D8)
+#define TABLA_A_CDC_RX6_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX7_B1_CTL (0x000002E0)
+#define TABLA_A_CDC_RX7_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX1_B2_CTL (0x000002B1)
+#define TABLA_A_CDC_RX1_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX2_B2_CTL (0x000002B9)
+#define TABLA_A_CDC_RX2_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX3_B2_CTL (0x000002C1)
+#define TABLA_A_CDC_RX3_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX4_B2_CTL (0x000002C9)
+#define TABLA_A_CDC_RX4_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX5_B2_CTL (0x000002D1)
+#define TABLA_A_CDC_RX5_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX6_B2_CTL (0x000002D9)
+#define TABLA_A_CDC_RX6_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX7_B2_CTL (0x000002E1)
+#define TABLA_A_CDC_RX7_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX1_B3_CTL (0x000002B2)
+#define TABLA_A_CDC_RX1_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX2_B3_CTL (0x000002BA)
+#define TABLA_A_CDC_RX2_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX3_B3_CTL (0x000002C2)
+#define TABLA_A_CDC_RX3_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX4_B3_CTL (0x000002CA)
+#define TABLA_A_CDC_RX4_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX5_B3_CTL (0x000002D2)
+#define TABLA_A_CDC_RX5_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX6_B3_CTL (0x000002DA)
+#define TABLA_A_CDC_RX6_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX7_B3_CTL (0x000002E2)
+#define TABLA_A_CDC_RX7_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX1_B4_CTL (0x000002B3)
+#define TABLA_A_CDC_RX1_B4_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX2_B4_CTL (0x000002BB)
+#define TABLA_A_CDC_RX2_B4_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX3_B4_CTL (0x000002C3)
+#define TABLA_A_CDC_RX3_B4_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX4_B4_CTL (0x000002CB)
+#define TABLA_A_CDC_RX4_B4_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX5_B4_CTL (0x000002D3)
+#define TABLA_A_CDC_RX5_B4_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX6_B4_CTL (0x000002DB)
+#define TABLA_A_CDC_RX6_B4_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX7_B4_CTL (0x000002E3)
+#define TABLA_A_CDC_RX7_B4_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX1_B5_CTL (0x000002B4)
+#define TABLA_A_CDC_RX1_B5_CTL__POR (0x00000060)
+#define TABLA_A_CDC_RX2_B5_CTL (0x000002BC)
+#define TABLA_A_CDC_RX2_B5_CTL__POR (0x00000060)
+#define TABLA_A_CDC_RX3_B5_CTL (0x000002C4)
+#define TABLA_A_CDC_RX3_B5_CTL__POR (0x00000060)
+#define TABLA_A_CDC_RX4_B5_CTL (0x000002CC)
+#define TABLA_A_CDC_RX4_B5_CTL__POR (0x00000060)
+#define TABLA_A_CDC_RX5_B5_CTL (0x000002D4)
+#define TABLA_A_CDC_RX5_B5_CTL__POR (0x00000060)
+#define TABLA_A_CDC_RX6_B5_CTL (0x000002DC)
+#define TABLA_A_CDC_RX6_B5_CTL__POR (0x00000060)
+#define TABLA_A_CDC_RX7_B5_CTL (0x000002E4)
+#define TABLA_A_CDC_RX7_B5_CTL__POR (0x00000060)
+#define TABLA_A_CDC_RX1_B6_CTL (0x000002B5)
+#define TABLA_A_CDC_RX1_B6_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX2_B6_CTL (0x000002BD)
+#define TABLA_A_CDC_RX2_B6_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX3_B6_CTL (0x000002C5)
+#define TABLA_A_CDC_RX3_B6_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX4_B6_CTL (0x000002CD)
+#define TABLA_A_CDC_RX4_B6_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX5_B6_CTL (0x000002D5)
+#define TABLA_A_CDC_RX5_B6_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX6_B6_CTL (0x000002DD)
+#define TABLA_A_CDC_RX6_B6_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX7_B6_CTL (0x000002E5)
+#define TABLA_A_CDC_RX7_B6_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX1_VOL_CTL_B1_CTL (0x000002B6)
+#define TABLA_A_CDC_RX1_VOL_CTL_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX2_VOL_CTL_B1_CTL (0x000002BE)
+#define TABLA_A_CDC_RX2_VOL_CTL_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX3_VOL_CTL_B1_CTL (0x000002C6)
+#define TABLA_A_CDC_RX3_VOL_CTL_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX4_VOL_CTL_B1_CTL (0x000002CE)
+#define TABLA_A_CDC_RX4_VOL_CTL_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX5_VOL_CTL_B1_CTL (0x000002D6)
+#define TABLA_A_CDC_RX5_VOL_CTL_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX6_VOL_CTL_B1_CTL (0x000002DE)
+#define TABLA_A_CDC_RX6_VOL_CTL_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX7_VOL_CTL_B1_CTL (0x000002E6)
+#define TABLA_A_CDC_RX7_VOL_CTL_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX1_VOL_CTL_B2_CTL (0x000002B7)
+#define TABLA_A_CDC_RX1_VOL_CTL_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX2_VOL_CTL_B2_CTL (0x000002BF)
+#define TABLA_A_CDC_RX2_VOL_CTL_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX3_VOL_CTL_B2_CTL (0x000002C7)
+#define TABLA_A_CDC_RX3_VOL_CTL_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX4_VOL_CTL_B2_CTL (0x000002CF)
+#define TABLA_A_CDC_RX4_VOL_CTL_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX5_VOL_CTL_B2_CTL (0x000002D7)
+#define TABLA_A_CDC_RX5_VOL_CTL_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX6_VOL_CTL_B2_CTL (0x000002DF)
+#define TABLA_A_CDC_RX6_VOL_CTL_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_RX7_VOL_CTL_B2_CTL (0x000002E7)
+#define TABLA_A_CDC_RX7_VOL_CTL_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CLK_ANC_RESET_CTL (0x00000300)
+#define TABLA_A_CDC_CLK_ANC_RESET_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CLK_RX_RESET_CTL (0x00000301)
+#define TABLA_A_CDC_CLK_RX_RESET_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CLK_TX_RESET_B1_CTL (0x00000302)
+#define TABLA_A_CDC_CLK_TX_RESET_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CLK_TX_RESET_B2_CTL (0x00000303)
+#define TABLA_A_CDC_CLK_TX_RESET_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CLK_DMIC_CTL (0x00000304)
+#define TABLA_A_CDC_CLK_DMIC_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CLK_RX_I2S_CTL (0x00000305)
+#define TABLA_A_CDC_CLK_RX_I2S_CTL__POR (0x00000003)
+#define TABLA_A_CDC_CLK_TX_I2S_CTL (0x00000306)
+#define TABLA_A_CDC_CLK_TX_I2S_CTL__POR (0x00000003)
+#define TABLA_A_CDC_CLK_OTHR_RESET_CTL (0x00000307)
+#define TABLA_A_CDC_CLK_OTHR_RESET_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CLK_TX_CLK_EN_B1_CTL (0x00000308)
+#define TABLA_A_CDC_CLK_TX_CLK_EN_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CLK_TX_CLK_EN_B2_CTL (0x00000309)
+#define TABLA_A_CDC_CLK_TX_CLK_EN_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CLK_OTHR_CTL (0x0000030A)
+#define TABLA_A_CDC_CLK_OTHR_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CLK_RDAC_CLK_EN_CTL (0x0000030B)
+#define TABLA_A_CDC_CLK_RDAC_CLK_EN_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CLK_ANC_CLK_EN_CTL (0x0000030C)
+#define TABLA_A_CDC_CLK_ANC_CLK_EN_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CLK_RX_B1_CTL (0x0000030D)
+#define TABLA_A_CDC_CLK_RX_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CLK_RX_B2_CTL (0x0000030E)
+#define TABLA_A_CDC_CLK_RX_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CLK_MCLK_CTL (0x0000030F)
+#define TABLA_A_CDC_CLK_MCLK_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CLK_PDM_CTL (0x00000310)
+#define TABLA_A_CDC_CLK_PDM_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CLK_SD_CTL (0x00000311)
+#define TABLA_A_CDC_CLK_SD_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CLSG_FREQ_THRESH_B1_CTL (0x00000320)
+#define TABLA_A_CDC_CLSG_FREQ_THRESH_B1_CTL__POR (0x00000007)
+#define TABLA_A_CDC_CLSG_FREQ_THRESH_B2_CTL (0x00000321)
+#define TABLA_A_CDC_CLSG_FREQ_THRESH_B2_CTL__POR (0x00000013)
+#define TABLA_A_CDC_CLSG_FREQ_THRESH_B3_CTL (0x00000322)
+#define TABLA_A_CDC_CLSG_FREQ_THRESH_B3_CTL__POR (0x00000053)
+#define TABLA_A_CDC_CLSG_FREQ_THRESH_B4_CTL (0x00000323)
+#define TABLA_A_CDC_CLSG_FREQ_THRESH_B4_CTL__POR (0x0000007f)
+#define TABLA_A_CDC_CLSG_GAIN_THRESH_CTL (0x00000324)
+#define TABLA_A_CDC_CLSG_GAIN_THRESH_CTL__POR (0x00000026)
+#define TABLA_A_CDC_CLSG_TIMER_B1_CFG (0x00000325)
+#define TABLA_A_CDC_CLSG_TIMER_B1_CFG__POR (0x0000000a)
+#define TABLA_A_CDC_CLSG_TIMER_B2_CFG (0x00000326)
+#define TABLA_A_CDC_CLSG_TIMER_B2_CFG__POR (0x00000000)
+#define TABLA_A_CDC_CLSG_CTL (0x00000327)
+#define TABLA_A_CDC_CLSG_CTL__POR (0x00000013)
+#define TABLA_A_CDC_IIR1_GAIN_B1_CTL (0x00000340)
+#define TABLA_A_CDC_IIR1_GAIN_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR2_GAIN_B1_CTL (0x00000350)
+#define TABLA_A_CDC_IIR2_GAIN_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR1_GAIN_B2_CTL (0x00000341)
+#define TABLA_A_CDC_IIR1_GAIN_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR2_GAIN_B2_CTL (0x00000351)
+#define TABLA_A_CDC_IIR2_GAIN_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR1_GAIN_B3_CTL (0x00000342)
+#define TABLA_A_CDC_IIR1_GAIN_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR2_GAIN_B3_CTL (0x00000352)
+#define TABLA_A_CDC_IIR2_GAIN_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR1_GAIN_B4_CTL (0x00000343)
+#define TABLA_A_CDC_IIR1_GAIN_B4_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR2_GAIN_B4_CTL (0x00000353)
+#define TABLA_A_CDC_IIR2_GAIN_B4_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR1_GAIN_B5_CTL (0x00000344)
+#define TABLA_A_CDC_IIR1_GAIN_B5_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR2_GAIN_B5_CTL (0x00000354)
+#define TABLA_A_CDC_IIR2_GAIN_B5_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR1_GAIN_B6_CTL (0x00000345)
+#define TABLA_A_CDC_IIR1_GAIN_B6_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR2_GAIN_B6_CTL (0x00000355)
+#define TABLA_A_CDC_IIR2_GAIN_B6_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR1_GAIN_B7_CTL (0x00000346)
+#define TABLA_A_CDC_IIR1_GAIN_B7_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR2_GAIN_B7_CTL (0x00000356)
+#define TABLA_A_CDC_IIR2_GAIN_B7_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR1_GAIN_B8_CTL (0x00000347)
+#define TABLA_A_CDC_IIR1_GAIN_B8_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR2_GAIN_B8_CTL (0x00000357)
+#define TABLA_A_CDC_IIR2_GAIN_B8_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR1_CTL (0x00000348)
+#define TABLA_A_CDC_IIR1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR2_CTL (0x00000358)
+#define TABLA_A_CDC_IIR2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR1_GAIN_TIMER_CTL (0x00000349)
+#define TABLA_A_CDC_IIR1_GAIN_TIMER_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR2_GAIN_TIMER_CTL (0x00000359)
+#define TABLA_A_CDC_IIR2_GAIN_TIMER_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR1_COEF_B1_CTL (0x0000034A)
+#define TABLA_A_CDC_IIR1_COEF_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR2_COEF_B1_CTL (0x0000035A)
+#define TABLA_A_CDC_IIR2_COEF_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR1_COEF_B2_CTL (0x0000034B)
+#define TABLA_A_CDC_IIR1_COEF_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR2_COEF_B2_CTL (0x0000035B)
+#define TABLA_A_CDC_IIR2_COEF_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR1_COEF_B3_CTL (0x0000034C)
+#define TABLA_A_CDC_IIR1_COEF_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR2_COEF_B3_CTL (0x0000035C)
+#define TABLA_A_CDC_IIR2_COEF_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR1_COEF_B4_CTL (0x0000034D)
+#define TABLA_A_CDC_IIR1_COEF_B4_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR2_COEF_B4_CTL (0x0000035D)
+#define TABLA_A_CDC_IIR2_COEF_B4_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR1_COEF_B5_CTL (0x0000034E)
+#define TABLA_A_CDC_IIR1_COEF_B5_CTL__POR (0x00000000)
+#define TABLA_A_CDC_IIR2_COEF_B5_CTL (0x0000035E)
+#define TABLA_A_CDC_IIR2_COEF_B5_CTL__POR (0x00000000)
+#define TABLA_A_CDC_TOP_GAIN_UPDATE (0x00000360)
+#define TABLA_A_CDC_TOP_GAIN_UPDATE__POR (0x00000000)
+#define TABLA_A_CDC_DEBUG_B1_CTL (0x00000368)
+#define TABLA_A_CDC_DEBUG_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_DEBUG_B2_CTL (0x00000369)
+#define TABLA_A_CDC_DEBUG_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_DEBUG_B3_CTL (0x0000036A)
+#define TABLA_A_CDC_DEBUG_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_DEBUG_B4_CTL (0x0000036B)
+#define TABLA_A_CDC_DEBUG_B4_CTL__POR (0x00000000)
+#define TABLA_A_CDC_DEBUG_B5_CTL (0x0000036C)
+#define TABLA_A_CDC_DEBUG_B5_CTL__POR (0x00000000)
+#define TABLA_A_CDC_DEBUG_B6_CTL (0x0000036D)
+#define TABLA_A_CDC_DEBUG_B6_CTL__POR (0x00000000)
+#define TABLA_A_CDC_COMP1_B1_CTL (0x00000370)
+#define TABLA_A_CDC_COMP1_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_COMP1_B2_CTL (0x00000371)
+#define TABLA_A_CDC_COMP1_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_COMP1_B3_CTL (0x00000372)
+#define TABLA_A_CDC_COMP1_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_COMP1_B4_CTL (0x00000373)
+#define TABLA_A_CDC_COMP1_B4_CTL__POR (0x00000000)
+#define TABLA_A_CDC_COMP1_B5_CTL (0x00000374)
+#define TABLA_A_CDC_COMP1_B5_CTL__POR (0x00000000)
+#define TABLA_A_CDC_COMP1_B6_CTL (0x00000375)
+#define TABLA_A_CDC_COMP1_B6_CTL__POR (0x00000000)
+#define TABLA_A_CDC_COMP1_SHUT_DOWN_STATUS (0x00000376)
+#define TABLA_A_CDC_COMP1_SHUT_DOWN_STATUS__POR (0x00000000)
+#define TABLA_A_CDC_COMP1_FS_CFG (0x00000377)
+#define TABLA_A_CDC_COMP1_FS_CFG__POR (0x00000000)
+#define TABLA_A_CDC_COMP2_B1_CTL (0x00000378)
+#define TABLA_A_CDC_COMP2_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_COMP2_B2_CTL (0x00000379)
+#define TABLA_A_CDC_COMP2_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_COMP2_B3_CTL (0x0000037A)
+#define TABLA_A_CDC_COMP2_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_COMP2_B4_CTL (0x0000037B)
+#define TABLA_A_CDC_COMP2_B4_CTL__POR (0x00000000)
+#define TABLA_A_CDC_COMP2_B5_CTL (0x0000037C)
+#define TABLA_A_CDC_COMP2_B5_CTL__POR (0x00000000)
+#define TABLA_A_CDC_COMP2_B6_CTL (0x0000037D)
+#define TABLA_A_CDC_COMP2_B6_CTL__POR (0x00000000)
+#define TABLA_A_CDC_COMP2_SHUT_DOWN_STATUS (0x0000037E)
+#define TABLA_A_CDC_COMP2_SHUT_DOWN_STATUS__POR (0x00000000)
+#define TABLA_A_CDC_COMP2_FS_CFG (0x0000037F)
+#define TABLA_A_CDC_COMP2_FS_CFG__POR (0x00000000)
+#define TABLA_A_CDC_CONN_RX1_B1_CTL (0x00000380)
+#define TABLA_A_CDC_CONN_RX1_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_RX1_B2_CTL (0x00000381)
+#define TABLA_A_CDC_CONN_RX1_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_RX1_B3_CTL (0x00000382)
+#define TABLA_A_CDC_CONN_RX1_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_RX2_B1_CTL (0x00000383)
+#define TABLA_A_CDC_CONN_RX2_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_RX2_B2_CTL (0x00000384)
+#define TABLA_A_CDC_CONN_RX2_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_RX2_B3_CTL (0x00000385)
+#define TABLA_A_CDC_CONN_RX2_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_RX3_B1_CTL (0x00000386)
+#define TABLA_A_CDC_CONN_RX3_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_RX3_B2_CTL (0x00000387)
+#define TABLA_A_CDC_CONN_RX3_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_RX3_B3_CTL (0x00000388)
+#define TABLA_A_CDC_CONN_RX3_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_RX4_B1_CTL (0x00000389)
+#define TABLA_A_CDC_CONN_RX4_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_RX4_B2_CTL (0x0000038A)
+#define TABLA_A_CDC_CONN_RX4_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_RX5_B1_CTL (0x0000038B)
+#define TABLA_A_CDC_CONN_RX5_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_RX5_B2_CTL (0x0000038C)
+#define TABLA_A_CDC_CONN_RX5_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_RX6_B1_CTL (0x0000038D)
+#define TABLA_A_CDC_CONN_RX6_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_RX6_B2_CTL (0x0000038E)
+#define TABLA_A_CDC_CONN_RX6_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_RX7_B1_CTL (0x0000038F)
+#define TABLA_A_CDC_CONN_RX7_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_RX7_B2_CTL (0x00000390)
+#define TABLA_A_CDC_CONN_RX7_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_ANC_B1_CTL (0x00000391)
+#define TABLA_A_CDC_CONN_ANC_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_ANC_B2_CTL (0x00000392)
+#define TABLA_A_CDC_CONN_ANC_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_TX_B1_CTL (0x00000393)
+#define TABLA_A_CDC_CONN_TX_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_TX_B2_CTL (0x00000394)
+#define TABLA_A_CDC_CONN_TX_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_TX_B3_CTL (0x00000395)
+#define TABLA_A_CDC_CONN_TX_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_TX_B4_CTL (0x00000396)
+#define TABLA_A_CDC_CONN_TX_B4_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_EQ1_B1_CTL (0x00000397)
+#define TABLA_A_CDC_CONN_EQ1_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_EQ1_B2_CTL (0x00000398)
+#define TABLA_A_CDC_CONN_EQ1_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_EQ1_B3_CTL (0x00000399)
+#define TABLA_A_CDC_CONN_EQ1_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_EQ1_B4_CTL (0x0000039A)
+#define TABLA_A_CDC_CONN_EQ1_B4_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_EQ2_B1_CTL (0x0000039B)
+#define TABLA_A_CDC_CONN_EQ2_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_EQ2_B2_CTL (0x0000039C)
+#define TABLA_A_CDC_CONN_EQ2_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_EQ2_B3_CTL (0x0000039D)
+#define TABLA_A_CDC_CONN_EQ2_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_EQ2_B4_CTL (0x0000039E)
+#define TABLA_A_CDC_CONN_EQ2_B4_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_SRC1_B1_CTL (0x0000039F)
+#define TABLA_A_CDC_CONN_SRC1_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_SRC1_B2_CTL (0x000003A0)
+#define TABLA_A_CDC_CONN_SRC1_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_SRC2_B1_CTL (0x000003A1)
+#define TABLA_A_CDC_CONN_SRC2_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_SRC2_B2_CTL (0x000003A2)
+#define TABLA_A_CDC_CONN_SRC2_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_TX_SB_B1_CTL (0x000003A3)
+#define TABLA_A_CDC_CONN_TX_SB_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_TX_SB_B2_CTL (0x000003A4)
+#define TABLA_A_CDC_CONN_TX_SB_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_TX_SB_B3_CTL (0x000003A5)
+#define TABLA_A_CDC_CONN_TX_SB_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_TX_SB_B4_CTL (0x000003A6)
+#define TABLA_A_CDC_CONN_TX_SB_B4_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_TX_SB_B5_CTL (0x000003A7)
+#define TABLA_A_CDC_CONN_TX_SB_B5_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_TX_SB_B6_CTL (0x000003A8)
+#define TABLA_A_CDC_CONN_TX_SB_B6_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_TX_SB_B7_CTL (0x000003A9)
+#define TABLA_A_CDC_CONN_TX_SB_B7_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_TX_SB_B8_CTL (0x000003AA)
+#define TABLA_A_CDC_CONN_TX_SB_B8_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_TX_SB_B9_CTL (0x000003AB)
+#define TABLA_A_CDC_CONN_TX_SB_B9_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_TX_SB_B10_CTL (0x000003AC)
+#define TABLA_A_CDC_CONN_TX_SB_B10_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_TX_SB_B11_CTL (0x000003AD)
+#define TABLA_A_CDC_CONN_TX_SB_B11_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_RX_SB_B1_CTL (0x000003AE)
+#define TABLA_A_CDC_CONN_RX_SB_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_RX_SB_B2_CTL (0x000003AF)
+#define TABLA_A_CDC_CONN_RX_SB_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_CLSG_CTL (0x000003B0)
+#define TABLA_A_CDC_CONN_CLSG_CTL__POR (0x00000000)
+#define TABLA_A_CDC_CONN_SPARE (0x000003B1)
+#define TABLA_A_CDC_CONN_SPARE__POR (0x00000000)
+#define TABLA_A_CDC_MBHC_EN_CTL (0x000003C0)
+#define TABLA_A_CDC_MBHC_EN_CTL__POR (0x00000000)
+#define TABLA_A_CDC_MBHC_FEATURE_B1_CFG (0x000003C1)
+#define TABLA_A_CDC_MBHC_FEATURE_B1_CFG__POR (0x00000000)
+#define TABLA_A_CDC_MBHC_FEATURE_B2_CFG (0x000003C2)
+#define TABLA_A_CDC_MBHC_FEATURE_B2_CFG__POR (0x00000006)
+#define TABLA_A_CDC_MBHC_TIMER_B1_CTL (0x000003C3)
+#define TABLA_A_CDC_MBHC_TIMER_B1_CTL__POR (0x00000003)
+#define TABLA_A_CDC_MBHC_TIMER_B2_CTL (0x000003C4)
+#define TABLA_A_CDC_MBHC_TIMER_B2_CTL__POR (0x00000009)
+#define TABLA_A_CDC_MBHC_TIMER_B3_CTL (0x000003C5)
+#define TABLA_A_CDC_MBHC_TIMER_B3_CTL__POR (0x0000001e)
+#define TABLA_A_CDC_MBHC_TIMER_B4_CTL (0x000003C6)
+#define TABLA_A_CDC_MBHC_TIMER_B4_CTL__POR (0x00000045)
+#define TABLA_A_CDC_MBHC_TIMER_B5_CTL (0x000003C7)
+#define TABLA_A_CDC_MBHC_TIMER_B5_CTL__POR (0x00000004)
+#define TABLA_A_CDC_MBHC_TIMER_B6_CTL (0x000003C8)
+#define TABLA_A_CDC_MBHC_TIMER_B6_CTL__POR (0x00000078)
+#define TABLA_A_CDC_MBHC_B1_STATUS (0x000003C9)
+#define TABLA_A_CDC_MBHC_B1_STATUS__POR (0x00000000)
+#define TABLA_A_CDC_MBHC_B2_STATUS (0x000003CA)
+#define TABLA_A_CDC_MBHC_B2_STATUS__POR (0x00000000)
+#define TABLA_A_CDC_MBHC_B3_STATUS (0x000003CB)
+#define TABLA_A_CDC_MBHC_B3_STATUS__POR (0x00000000)
+#define TABLA_A_CDC_MBHC_B4_STATUS (0x000003CC)
+#define TABLA_A_CDC_MBHC_B4_STATUS__POR (0x00000000)
+#define TABLA_A_CDC_MBHC_B5_STATUS (0x000003CD)
+#define TABLA_A_CDC_MBHC_B5_STATUS__POR (0x00000000)
+#define TABLA_A_CDC_MBHC_B1_CTL (0x000003CE)
+#define TABLA_A_CDC_MBHC_B1_CTL__POR (0x000000c0)
+#define TABLA_A_CDC_MBHC_B2_CTL (0x000003CF)
+#define TABLA_A_CDC_MBHC_B2_CTL__POR (0x0000005d)
+#define TABLA_A_CDC_MBHC_VOLT_B1_CTL (0x000003D0)
+#define TABLA_A_CDC_MBHC_VOLT_B1_CTL__POR (0x00000000)
+#define TABLA_A_CDC_MBHC_VOLT_B2_CTL (0x000003D1)
+#define TABLA_A_CDC_MBHC_VOLT_B2_CTL__POR (0x00000000)
+#define TABLA_A_CDC_MBHC_VOLT_B3_CTL (0x000003D2)
+#define TABLA_A_CDC_MBHC_VOLT_B3_CTL__POR (0x00000000)
+#define TABLA_A_CDC_MBHC_VOLT_B4_CTL (0x000003D3)
+#define TABLA_A_CDC_MBHC_VOLT_B4_CTL__POR (0x00000000)
+#define TABLA_A_CDC_MBHC_VOLT_B5_CTL (0x000003D4)
+#define TABLA_A_CDC_MBHC_VOLT_B5_CTL__POR (0x00000000)
+#define TABLA_A_CDC_MBHC_VOLT_B6_CTL (0x000003D5)
+#define TABLA_A_CDC_MBHC_VOLT_B6_CTL__POR (0x00000000)
+#define TABLA_A_CDC_MBHC_VOLT_B7_CTL (0x000003D6)
+#define TABLA_A_CDC_MBHC_VOLT_B7_CTL__POR (0x000000ff)
+#define TABLA_A_CDC_MBHC_VOLT_B8_CTL (0x000003D7)
+#define TABLA_A_CDC_MBHC_VOLT_B8_CTL__POR (0x00000007)
+#define TABLA_A_CDC_MBHC_VOLT_B9_CTL (0x000003D8)
+#define TABLA_A_CDC_MBHC_VOLT_B9_CTL__POR (0x000000ff)
+#define TABLA_A_CDC_MBHC_VOLT_B10_CTL (0x000003D9)
+#define TABLA_A_CDC_MBHC_VOLT_B10_CTL__POR (0x0000007f)
+#define TABLA_A_CDC_MBHC_VOLT_B11_CTL (0x000003DA)
+#define TABLA_A_CDC_MBHC_VOLT_B11_CTL__POR (0x00000000)
+#define TABLA_A_CDC_MBHC_VOLT_B12_CTL (0x000003DB)
+#define TABLA_A_CDC_MBHC_VOLT_B12_CTL__POR (0x00000080)
+#define TABLA_A_CDC_MBHC_CLK_CTL (0x000003DC)
+#define TABLA_A_CDC_MBHC_CLK_CTL__POR (0x00000000)
+#define TABLA_A_CDC_MBHC_INT_CTL (0x000003DD)
+#define TABLA_A_CDC_MBHC_INT_CTL__POR (0x00000000)
+#define TABLA_A_CDC_MBHC_DEBUG_CTL (0x000003DE)
+#define TABLA_A_CDC_MBHC_DEBUG_CTL__POR (0x00000000)
+#define TABLA_A_CDC_MBHC_SPARE (0x000003DF)
+#define TABLA_A_CDC_MBHC_SPARE__POR (0x00000000)
+
+
+/* SLIMBUS Slave Registers */
+#define TABLA_SLIM_PGD_PORT_INT_EN0 (0x30)
+#define TABLA_SLIM_PGD_PORT_INT_STATUS0 (0x34)
+#define TABLA_SLIM_PGD_PORT_INT_CLR0 (0x38)
+#define TABLA_SLIM_PGD_PORT_INT_SOURCE0 (0x60)
+
+/* Macros for Packing Register Writes into a U32 */
+#define TABLA_PACKED_REG_SIZE sizeof(u32)
+
+#define TABLA_CODEC_PACK_ENTRY(reg, mask, val) ((val & 0xff)|\
+ ((mask & 0xff) << 8)|((reg & 0xffff) << 16))
+
+#define TABLA_CODEC_UNPACK_ENTRY(packed, reg, mask, val) \
+ do { \
+ ((reg) = ((packed >> 16) & (0xffff))); \
+ ((mask) = ((packed >> 8) & (0xff))); \
+ ((val) = ((packed) & (0xff))); \
+ } while (0);
+
+#endif
diff --git a/original/linux/mfd/wcd9xxx/wcd9xxx_registers.h b/original/linux/mfd/wcd9xxx/wcd9xxx_registers.h
new file mode 100644
index 0000000..c66e953
--- /dev/null
+++ b/original/linux/mfd/wcd9xxx/wcd9xxx_registers.h
@@ -0,0 +1,42 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef WCD9XXX_CODEC_DIGITAL_H
+
+#define WCD9XXX_CODEC_DIGITAL_H
+
+#define WCD9XXX_A_CHIP_CTL (0x00)
+#define WCD9XXX_A_CHIP_CTL__POR (0x00000000)
+#define WCD9XXX_A_CHIP_STATUS (0x01)
+#define WCD9XXX_A_CHIP_STATUS__POR (0x00000000)
+#define WCD9XXX_A_CHIP_ID_BYTE_0 (0x04)
+#define WCD9XXX_A_CHIP_ID_BYTE_0__POR (0x00000000)
+#define WCD9XXX_A_CHIP_ID_BYTE_1 (0x05)
+#define WCD9XXX_A_CHIP_ID_BYTE_1__POR (0x00000000)
+#define WCD9XXX_A_CHIP_ID_BYTE_2 (0x06)
+#define WCD9XXX_A_CHIP_ID_BYTE_2__POR (0x00000000)
+#define WCD9XXX_A_CHIP_ID_BYTE_3 (0x07)
+#define WCD9XXX_A_CHIP_ID_BYTE_3__POR (0x00000001)
+#define WCD9XXX_A_CHIP_VERSION (0x08)
+#define WCD9XXX_A_CHIP_VERSION__POR (0x00000020)
+#define WCD9XXX_A_SB_VERSION (0x09)
+#define WCD9XXX_A_SB_VERSION__POR (0x00000010)
+#define WCD9XXX_A_SLAVE_ID_1 (0x0C)
+#define WCD9XXX_A_SLAVE_ID_1__POR (0x00000077)
+#define WCD9XXX_A_SLAVE_ID_2 (0x0D)
+#define WCD9XXX_A_SLAVE_ID_2__POR (0x00000066)
+#define WCD9XXX_A_SLAVE_ID_3 (0x0E)
+#define WCD9XXX_A_SLAVE_ID_3__POR (0x00000055)
+#define WCD9XXX_A_CDC_CTL (0x80)
+#define WCD9XXX_A_CDC_CTL__POR (0x00000000)
+#define WCD9XXX_A_LEAKAGE_CTL (0x88)
+#define WCD9XXX_A_LEAKAGE_CTL__POR (0x00000004)
+#endif
diff --git a/original/linux/msm_audio.h b/original/linux/msm_audio.h
index 9da6ccc..f2a39e4 100644
--- a/original/linux/msm_audio.h
+++ b/original/linux/msm_audio.h
@@ -1,6 +1,7 @@
/* include/linux/msm_audio.h
*
* Copyright (C) 2008 Google, Inc.
+ * Copyright (c) 2012 Code Aurora Forum. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -18,7 +19,6 @@
#include <linux/types.h>
#include <linux/ioctl.h>
-#include <asm/sizes.h>
/* PCM Audio */
@@ -35,10 +35,118 @@
#define AUDIO_SET_EQ _IOW(AUDIO_IOCTL_MAGIC, 8, unsigned)
#define AUDIO_SET_RX_IIR _IOW(AUDIO_IOCTL_MAGIC, 9, unsigned)
#define AUDIO_SET_VOLUME _IOW(AUDIO_IOCTL_MAGIC, 10, unsigned)
-#define AUDIO_ENABLE_AUDPRE _IOW(AUDIO_IOCTL_MAGIC, 11, unsigned)
-#define AUDIO_SET_AGC _IOW(AUDIO_IOCTL_MAGIC, 12, unsigned)
-#define AUDIO_SET_NS _IOW(AUDIO_IOCTL_MAGIC, 13, unsigned)
-#define AUDIO_SET_TX_IIR _IOW(AUDIO_IOCTL_MAGIC, 14, unsigned)
+#define AUDIO_PAUSE _IOW(AUDIO_IOCTL_MAGIC, 11, unsigned)
+#define AUDIO_PLAY_DTMF _IOW(AUDIO_IOCTL_MAGIC, 12, unsigned)
+#define AUDIO_GET_EVENT _IOR(AUDIO_IOCTL_MAGIC, 13, unsigned)
+#define AUDIO_ABORT_GET_EVENT _IOW(AUDIO_IOCTL_MAGIC, 14, unsigned)
+#define AUDIO_REGISTER_PMEM _IOW(AUDIO_IOCTL_MAGIC, 15, unsigned)
+#define AUDIO_DEREGISTER_PMEM _IOW(AUDIO_IOCTL_MAGIC, 16, unsigned)
+#define AUDIO_ASYNC_WRITE _IOW(AUDIO_IOCTL_MAGIC, 17, unsigned)
+#define AUDIO_ASYNC_READ _IOW(AUDIO_IOCTL_MAGIC, 18, unsigned)
+#define AUDIO_SET_INCALL _IOW(AUDIO_IOCTL_MAGIC, 19, struct msm_voicerec_mode)
+#define AUDIO_GET_NUM_SND_DEVICE _IOR(AUDIO_IOCTL_MAGIC, 20, unsigned)
+#define AUDIO_GET_SND_DEVICES _IOWR(AUDIO_IOCTL_MAGIC, 21, \
+ struct msm_snd_device_list)
+#define AUDIO_ENABLE_SND_DEVICE _IOW(AUDIO_IOCTL_MAGIC, 22, unsigned)
+#define AUDIO_DISABLE_SND_DEVICE _IOW(AUDIO_IOCTL_MAGIC, 23, unsigned)
+#define AUDIO_ROUTE_STREAM _IOW(AUDIO_IOCTL_MAGIC, 24, \
+ struct msm_audio_route_config)
+#define AUDIO_GET_PCM_CONFIG _IOR(AUDIO_IOCTL_MAGIC, 30, unsigned)
+#define AUDIO_SET_PCM_CONFIG _IOW(AUDIO_IOCTL_MAGIC, 31, unsigned)
+#define AUDIO_SWITCH_DEVICE _IOW(AUDIO_IOCTL_MAGIC, 32, unsigned)
+#define AUDIO_SET_MUTE _IOW(AUDIO_IOCTL_MAGIC, 33, unsigned)
+#define AUDIO_UPDATE_ACDB _IOW(AUDIO_IOCTL_MAGIC, 34, unsigned)
+#define AUDIO_START_VOICE _IOW(AUDIO_IOCTL_MAGIC, 35, unsigned)
+#define AUDIO_STOP_VOICE _IOW(AUDIO_IOCTL_MAGIC, 36, unsigned)
+#define AUDIO_REINIT_ACDB _IOW(AUDIO_IOCTL_MAGIC, 39, unsigned)
+#define AUDIO_OUTPORT_FLUSH _IOW(AUDIO_IOCTL_MAGIC, 40, unsigned short)
+#define AUDIO_SET_ERR_THRESHOLD_VALUE _IOW(AUDIO_IOCTL_MAGIC, 41, \
+ unsigned short)
+#define AUDIO_GET_BITSTREAM_ERROR_INFO _IOR(AUDIO_IOCTL_MAGIC, 42, \
+ struct msm_audio_bitstream_error_info)
+
+#define AUDIO_SET_SRS_TRUMEDIA_PARAM _IOW(AUDIO_IOCTL_MAGIC, 43, unsigned)
+
+/* Qualcomm extensions */
+#define AUDIO_SET_STREAM_CONFIG _IOW(AUDIO_IOCTL_MAGIC, 80, \
+ struct msm_audio_stream_config)
+#define AUDIO_GET_STREAM_CONFIG _IOR(AUDIO_IOCTL_MAGIC, 81, \
+ struct msm_audio_stream_config)
+#define AUDIO_GET_SESSION_ID _IOR(AUDIO_IOCTL_MAGIC, 82, unsigned short)
+#define AUDIO_GET_STREAM_INFO _IOR(AUDIO_IOCTL_MAGIC, 83, \
+ struct msm_audio_bitstream_info)
+#define AUDIO_SET_PAN _IOW(AUDIO_IOCTL_MAGIC, 84, unsigned)
+#define AUDIO_SET_QCONCERT_PLUS _IOW(AUDIO_IOCTL_MAGIC, 85, unsigned)
+#define AUDIO_SET_MBADRC _IOW(AUDIO_IOCTL_MAGIC, 86, unsigned)
+#define AUDIO_SET_VOLUME_PATH _IOW(AUDIO_IOCTL_MAGIC, 87, \
+ struct msm_vol_info)
+#define AUDIO_SET_MAX_VOL_ALL _IOW(AUDIO_IOCTL_MAGIC, 88, unsigned)
+#define AUDIO_ENABLE_AUDPRE _IOW(AUDIO_IOCTL_MAGIC, 89, unsigned)
+#define AUDIO_SET_AGC _IOW(AUDIO_IOCTL_MAGIC, 90, unsigned)
+#define AUDIO_SET_NS _IOW(AUDIO_IOCTL_MAGIC, 91, unsigned)
+#define AUDIO_SET_TX_IIR _IOW(AUDIO_IOCTL_MAGIC, 92, unsigned)
+#define AUDIO_GET_BUF_CFG _IOW(AUDIO_IOCTL_MAGIC, 93, \
+ struct msm_audio_buf_cfg)
+#define AUDIO_SET_BUF_CFG _IOW(AUDIO_IOCTL_MAGIC, 94, \
+ struct msm_audio_buf_cfg)
+#define AUDIO_SET_ACDB_BLK _IOW(AUDIO_IOCTL_MAGIC, 95, \
+ struct msm_acdb_cmd_device)
+#define AUDIO_GET_ACDB_BLK _IOW(AUDIO_IOCTL_MAGIC, 96, \
+ struct msm_acdb_cmd_device)
+
+#define AUDIO_REGISTER_ION _IOW(AUDIO_IOCTL_MAGIC, 97, unsigned)
+#define AUDIO_DEREGISTER_ION _IOW(AUDIO_IOCTL_MAGIC, 98, unsigned)
+
+#define AUDIO_MAX_COMMON_IOCTL_NUM 100
+
+
+#define HANDSET_MIC 0x01
+#define HANDSET_SPKR 0x02
+#define HEADSET_MIC 0x03
+#define HEADSET_SPKR_MONO 0x04
+#define HEADSET_SPKR_STEREO 0x05
+#define SPKR_PHONE_MIC 0x06
+#define SPKR_PHONE_MONO 0x07
+#define SPKR_PHONE_STEREO 0x08
+#define BT_SCO_MIC 0x09
+#define BT_SCO_SPKR 0x0A
+#define BT_A2DP_SPKR 0x0B
+#define TTY_HEADSET_MIC 0x0C
+#define TTY_HEADSET_SPKR 0x0D
+
+/* Default devices are not supported in a */
+/* device switching context. Only supported */
+/* for stream devices. */
+/* DO NOT USE */
+#define DEFAULT_TX 0x0E
+#define DEFAULT_RX 0x0F
+
+#define BT_A2DP_TX 0x10
+
+#define HEADSET_MONO_PLUS_SPKR_MONO_RX 0x11
+#define HEADSET_MONO_PLUS_SPKR_STEREO_RX 0x12
+#define HEADSET_STEREO_PLUS_SPKR_MONO_RX 0x13
+#define HEADSET_STEREO_PLUS_SPKR_STEREO_RX 0x14
+
+#define I2S_RX 0x20
+#define I2S_TX 0x21
+
+#define ADRC_ENABLE 0x0001
+#define EQ_ENABLE 0x0002
+#define IIR_ENABLE 0x0004
+#define QCONCERT_PLUS_ENABLE 0x0008
+#define MBADRC_ENABLE 0x0010
+#define SRS_ENABLE 0x0020
+#define SRS_DISABLE 0x0040
+
+#define AGC_ENABLE 0x0001
+#define NS_ENABLE 0x0002
+#define TX_IIR_ENABLE 0x0004
+#define FLUENCE_ENABLE 0x0008
+
+#define VOC_REC_UPLINK 0x00
+#define VOC_REC_DOWNLINK 0x01
+#define VOC_REC_BOTH 0x02
struct msm_audio_config {
uint32_t buffer_size;
@@ -46,15 +154,45 @@
uint32_t channel_count;
uint32_t sample_rate;
uint32_t type;
+ uint32_t meta_field;
+ uint32_t bits;
uint32_t unused[3];
};
+struct msm_audio_stream_config {
+ uint32_t buffer_size;
+ uint32_t buffer_count;
+};
+
+struct msm_audio_buf_cfg{
+ uint32_t meta_info_enable;
+ uint32_t frames_per_buf;
+};
+
struct msm_audio_stats {
uint32_t byte_count;
uint32_t sample_count;
uint32_t unused[2];
};
+struct msm_audio_ion_info {
+ int fd;
+ void *vaddr;
+};
+
+struct msm_audio_pmem_info {
+ int fd;
+ void *vaddr;
+};
+
+struct msm_audio_aio_buf {
+ void *buf_addr;
+ uint32_t buf_len;
+ uint32_t data_len;
+ void *private_data;
+ unsigned short mfield_sz; /*only useful for data has meta field */
+};
+
/* Audio routing */
#define SND_IOCTL_MAGIC 's'
@@ -62,6 +200,20 @@
#define SND_MUTE_UNMUTED 0
#define SND_MUTE_MUTED 1
+struct msm_mute_info {
+ uint32_t mute;
+ uint32_t path;
+};
+
+struct msm_vol_info {
+ uint32_t vol;
+ uint32_t path;
+};
+
+struct msm_voicerec_mode {
+ uint32_t rec_mode;
+};
+
struct msm_snd_device_config {
uint32_t device;
uint32_t ear_mute;
@@ -98,4 +250,118 @@
#define SND_GET_ENDPOINT _IOWR(SND_IOCTL_MAGIC, 5, struct msm_snd_endpoint *)
-#endif /* __LINUX_MSM_AUDIO_H */
+
+#define SND_AVC_CTL _IOW(SND_IOCTL_MAGIC, 6, unsigned *)
+#define SND_AGC_CTL _IOW(SND_IOCTL_MAGIC, 7, unsigned *)
+
+struct msm_audio_pcm_config {
+ uint32_t pcm_feedback; /* 0 - disable > 0 - enable */
+ uint32_t buffer_count; /* Number of buffers to allocate */
+ uint32_t buffer_size; /* Size of buffer for capturing of
+ PCM samples */
+};
+
+#define AUDIO_EVENT_SUSPEND 0
+#define AUDIO_EVENT_RESUME 1
+#define AUDIO_EVENT_WRITE_DONE 2
+#define AUDIO_EVENT_READ_DONE 3
+#define AUDIO_EVENT_STREAM_INFO 4
+#define AUDIO_EVENT_BITSTREAM_ERROR_INFO 5
+
+#define AUDIO_CODEC_TYPE_MP3 0
+#define AUDIO_CODEC_TYPE_AAC 1
+
+struct msm_audio_bitstream_info {
+ uint32_t codec_type;
+ uint32_t chan_info;
+ uint32_t sample_rate;
+ uint32_t bit_stream_info;
+ uint32_t bit_rate;
+ uint32_t unused[3];
+};
+
+struct msm_audio_bitstream_error_info {
+ uint32_t dec_id;
+ uint32_t err_msg_indicator;
+ uint32_t err_type;
+};
+
+union msm_audio_event_payload {
+ struct msm_audio_aio_buf aio_buf;
+ struct msm_audio_bitstream_info stream_info;
+ struct msm_audio_bitstream_error_info error_info;
+ int reserved;
+};
+
+struct msm_audio_event {
+ int event_type;
+ int timeout_ms;
+ union msm_audio_event_payload event_payload;
+};
+
+#define MSM_SNDDEV_CAP_RX 0x1
+#define MSM_SNDDEV_CAP_TX 0x2
+#define MSM_SNDDEV_CAP_VOICE 0x4
+
+struct msm_snd_device_info {
+ uint32_t dev_id;
+ uint32_t dev_cap; /* bitmask describe capability of device */
+ char dev_name[64];
+};
+
+struct msm_snd_device_list {
+ uint32_t num_dev; /* Indicate number of device info to be retrieved */
+ struct msm_snd_device_info *list;
+};
+
+struct msm_dtmf_config {
+ uint16_t path;
+ uint16_t dtmf_hi;
+ uint16_t dtmf_low;
+ uint16_t duration;
+ uint16_t tx_gain;
+ uint16_t rx_gain;
+ uint16_t mixing;
+};
+
+#define AUDIO_ROUTE_STREAM_VOICE_RX 0
+#define AUDIO_ROUTE_STREAM_VOICE_TX 1
+#define AUDIO_ROUTE_STREAM_PLAYBACK 2
+#define AUDIO_ROUTE_STREAM_REC 3
+
+struct msm_audio_route_config {
+ uint32_t stream_type;
+ uint32_t stream_id;
+ uint32_t dev_id;
+};
+
+#define AUDIO_MAX_EQ_BANDS 12
+
+struct msm_audio_eq_band {
+ uint16_t band_idx; /* The band index, 0 .. 11 */
+ uint32_t filter_type; /* Filter band type */
+ uint32_t center_freq_hz; /* Filter band center frequency */
+ uint32_t filter_gain; /* Filter band initial gain (dB) */
+ /* Range is +12 dB to -12 dB with 1dB increments. */
+ uint32_t q_factor;
+} __attribute__ ((packed));
+
+struct msm_audio_eq_stream_config {
+ uint32_t enable; /* Number of consequtive bands specified */
+ uint32_t num_bands;
+ struct msm_audio_eq_band eq_bands[AUDIO_MAX_EQ_BANDS];
+} __attribute__ ((packed));
+
+struct msm_acdb_cmd_device {
+ uint32_t command_id;
+ uint32_t device_id;
+ uint32_t network_id;
+ uint32_t sample_rate_id; /* Actual sample rate value */
+ uint32_t interface_id; /* See interface id's above */
+ uint32_t algorithm_block_id; /* See enumerations above */
+ uint32_t total_bytes; /* Length in bytes used by buffer */
+ uint32_t *phys_buf; /* Physical Address of data */
+};
+
+
+#endif
diff --git a/original/linux/msm_audio_aac.h b/original/linux/msm_audio_aac.h
new file mode 100644
index 0000000..620e5ab
--- /dev/null
+++ b/original/linux/msm_audio_aac.h
@@ -0,0 +1,72 @@
+#ifndef __MSM_AUDIO_AAC_H
+#define __MSM_AUDIO_AAC_H
+
+#include <linux/msm_audio.h>
+
+#define AUDIO_SET_AAC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_COMMON_IOCTL_NUM+0), unsigned)
+#define AUDIO_GET_AAC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_COMMON_IOCTL_NUM+1), unsigned)
+
+#define AUDIO_SET_AAC_ENC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_COMMON_IOCTL_NUM+3), struct msm_audio_aac_enc_config)
+
+#define AUDIO_GET_AAC_ENC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_COMMON_IOCTL_NUM+4), struct msm_audio_aac_enc_config)
+
+#define AUDIO_AAC_FORMAT_ADTS -1
+#define AUDIO_AAC_FORMAT_RAW 0x0000
+#define AUDIO_AAC_FORMAT_PSUEDO_RAW 0x0001
+#define AUDIO_AAC_FORMAT_LOAS 0x0002
+#define AUDIO_AAC_FORMAT_ADIF 0x0003
+
+#define AUDIO_AAC_OBJECT_LC 0x0002
+#define AUDIO_AAC_OBJECT_LTP 0x0004
+#define AUDIO_AAC_OBJECT_ERLC 0x0011
+#define AUDIO_AAC_OBJECT_BSAC 0x0016
+
+#define AUDIO_AAC_SEC_DATA_RES_ON 0x0001
+#define AUDIO_AAC_SEC_DATA_RES_OFF 0x0000
+
+#define AUDIO_AAC_SCA_DATA_RES_ON 0x0001
+#define AUDIO_AAC_SCA_DATA_RES_OFF 0x0000
+
+#define AUDIO_AAC_SPEC_DATA_RES_ON 0x0001
+#define AUDIO_AAC_SPEC_DATA_RES_OFF 0x0000
+
+#define AUDIO_AAC_SBR_ON_FLAG_ON 0x0001
+#define AUDIO_AAC_SBR_ON_FLAG_OFF 0x0000
+
+#define AUDIO_AAC_SBR_PS_ON_FLAG_ON 0x0001
+#define AUDIO_AAC_SBR_PS_ON_FLAG_OFF 0x0000
+
+/* Primary channel on both left and right channels */
+#define AUDIO_AAC_DUAL_MONO_PL_PR 0
+/* Secondary channel on both left and right channels */
+#define AUDIO_AAC_DUAL_MONO_SL_SR 1
+/* Primary channel on right channel and 2nd on left channel */
+#define AUDIO_AAC_DUAL_MONO_SL_PR 2
+/* 2nd channel on right channel and primary on left channel */
+#define AUDIO_AAC_DUAL_MONO_PL_SR 3
+
+struct msm_audio_aac_config {
+ signed short format;
+ unsigned short audio_object;
+ unsigned short ep_config; /* 0 ~ 3 useful only obj = ERLC */
+ unsigned short aac_section_data_resilience_flag;
+ unsigned short aac_scalefactor_data_resilience_flag;
+ unsigned short aac_spectral_data_resilience_flag;
+ unsigned short sbr_on_flag;
+ unsigned short sbr_ps_on_flag;
+ unsigned short dual_mono_mode;
+ unsigned short channel_configuration;
+};
+
+struct msm_audio_aac_enc_config {
+ uint32_t channels;
+ uint32_t sample_rate;
+ uint32_t bit_rate;
+ uint32_t stream_format;
+};
+
+#endif /* __MSM_AUDIO_AAC_H */
diff --git a/original/linux/msm_audio_acdb.h b/original/linux/msm_audio_acdb.h
new file mode 100644
index 0000000..e7f06b5
--- /dev/null
+++ b/original/linux/msm_audio_acdb.h
@@ -0,0 +1,81 @@
+#ifndef __MSM_AUDIO_ACDB_H
+#define __MSM_AUDIO_ACDB_H
+
+#include <linux/msm_audio.h>
+
+#define AUDIO_SET_VOCPROC_CAL _IOW(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_COMMON_IOCTL_NUM+0), unsigned)
+#define AUDIO_SET_VOCPROC_STREAM_CAL _IOW(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_COMMON_IOCTL_NUM+1), unsigned)
+#define AUDIO_SET_VOCPROC_VOL_CAL _IOW(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_COMMON_IOCTL_NUM+2), unsigned)
+#define AUDIO_SET_AUDPROC_RX_CAL _IOW(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_COMMON_IOCTL_NUM+3), unsigned)
+#define AUDIO_SET_AUDPROC_RX_STREAM_CAL _IOW(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_COMMON_IOCTL_NUM+4), unsigned)
+#define AUDIO_SET_AUDPROC_RX_VOL_CAL _IOW(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_COMMON_IOCTL_NUM+5), unsigned)
+#define AUDIO_SET_AUDPROC_TX_CAL _IOW(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_COMMON_IOCTL_NUM+6), unsigned)
+#define AUDIO_SET_AUDPROC_TX_STREAM_CAL _IOW(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_COMMON_IOCTL_NUM+7), unsigned)
+#define AUDIO_SET_AUDPROC_TX_VOL_CAL _IOW(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_COMMON_IOCTL_NUM+8), unsigned)
+#define AUDIO_SET_SIDETONE_CAL _IOW(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_COMMON_IOCTL_NUM+9), unsigned)
+#define AUDIO_SET_ANC_CAL _IOW(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_COMMON_IOCTL_NUM+10), unsigned)
+#define AUDIO_SET_VOICE_RX_TOPOLOGY _IOW(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_COMMON_IOCTL_NUM+11), unsigned)
+#define AUDIO_SET_VOICE_TX_TOPOLOGY _IOW(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_COMMON_IOCTL_NUM+12), unsigned)
+#define AUDIO_SET_ADM_RX_TOPOLOGY _IOW(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_COMMON_IOCTL_NUM+13), unsigned)
+#define AUDIO_SET_ADM_TX_TOPOLOGY _IOW(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_COMMON_IOCTL_NUM+14), unsigned)
+#define AUDIO_SET_ASM_TOPOLOGY _IOW(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_COMMON_IOCTL_NUM+15), unsigned)
+#define AUDIO_SET_AFE_TX_CAL _IOW(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_COMMON_IOCTL_NUM+16), unsigned)
+#define AUDIO_SET_AFE_RX_CAL _IOW(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_COMMON_IOCTL_NUM+17), unsigned)
+
+
+#define AUDIO_MAX_ACDB_IOCTL (AUDIO_MAX_COMMON_IOCTL_NUM+30)
+
+/* ACDB structures */
+struct cal_block {
+ uint32_t cal_size; /* Size of Cal Data */
+ uint32_t cal_offset; /* offset pointer to Cal Data */
+};
+
+struct sidetone_cal {
+ uint16_t enable;
+ uint16_t gain;
+};
+
+/* For Real-Time Audio Calibration */
+#define AUDIO_GET_RTAC_ADM_INFO _IOR(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_ACDB_IOCTL+1), unsigned)
+#define AUDIO_GET_RTAC_VOICE_INFO _IOR(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_ACDB_IOCTL+2), unsigned)
+#define AUDIO_GET_RTAC_ADM_CAL _IOWR(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_ACDB_IOCTL+3), unsigned)
+#define AUDIO_SET_RTAC_ADM_CAL _IOWR(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_ACDB_IOCTL+4), unsigned)
+#define AUDIO_GET_RTAC_ASM_CAL _IOWR(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_ACDB_IOCTL+5), unsigned)
+#define AUDIO_SET_RTAC_ASM_CAL _IOWR(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_ACDB_IOCTL+6), unsigned)
+#define AUDIO_GET_RTAC_CVS_CAL _IOWR(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_ACDB_IOCTL+7), unsigned)
+#define AUDIO_SET_RTAC_CVS_CAL _IOWR(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_ACDB_IOCTL+8), unsigned)
+#define AUDIO_GET_RTAC_CVP_CAL _IOWR(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_ACDB_IOCTL+9), unsigned)
+#define AUDIO_SET_RTAC_CVP_CAL _IOWR(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_ACDB_IOCTL+10), unsigned)
+
+#define AUDIO_MAX_RTAC_IOCTL (AUDIO_MAX_ACDB_IOCTL+20)
+
+#endif /* __MSM_AUDIO_ACDB_H */
diff --git a/original/linux/msm_audio_wma.h b/original/linux/msm_audio_wma.h
new file mode 100644
index 0000000..24ff264
--- /dev/null
+++ b/original/linux/msm_audio_wma.h
@@ -0,0 +1,33 @@
+#ifndef __MSM_AUDIO_WMA_H
+#define __MSM_AUDIO_WMA_H
+
+#define AUDIO_GET_WMA_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_COMMON_IOCTL_NUM+0), unsigned)
+#define AUDIO_SET_WMA_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_COMMON_IOCTL_NUM+1), unsigned)
+
+#define AUDIO_GET_WMA_CONFIG_V2 _IOR(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_COMMON_IOCTL_NUM+2), struct msm_audio_wma_config_v2)
+#define AUDIO_SET_WMA_CONFIG_V2 _IOW(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_COMMON_IOCTL_NUM+3), struct msm_audio_wma_config_v2)
+
+struct msm_audio_wma_config {
+ unsigned short armdatareqthr;
+ unsigned short channelsdecoded;
+ unsigned short wmabytespersec;
+ unsigned short wmasamplingfreq;
+ unsigned short wmaencoderopts;
+};
+
+struct msm_audio_wma_config_v2 {
+ unsigned short format_tag;
+ unsigned short numchannels;
+ uint32_t samplingrate;
+ uint32_t avgbytespersecond;
+ unsigned short block_align;
+ unsigned short validbitspersample;
+ uint32_t channelmask;
+ unsigned short encodeopt;
+};
+
+#endif /* __MSM_AUDIO_WMA_H */
diff --git a/original/linux/msm_audio_wmapro.h b/original/linux/msm_audio_wmapro.h
new file mode 100644
index 0000000..b680f41
--- /dev/null
+++ b/original/linux/msm_audio_wmapro.h
@@ -0,0 +1,22 @@
+#ifndef __MSM_AUDIO_WMAPRO_H
+#define __MSM_AUDIO_WMAPRO_H
+
+#define AUDIO_GET_WMAPRO_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_COMMON_IOCTL_NUM+0), unsigned)
+#define AUDIO_SET_WMAPRO_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_COMMON_IOCTL_NUM+1), unsigned)
+
+struct msm_audio_wmapro_config {
+ unsigned short armdatareqthr;
+ uint8_t validbitspersample;
+ uint8_t numchannels;
+ unsigned short formattag;
+ unsigned short samplingrate;
+ unsigned short avgbytespersecond;
+ unsigned short asfpacketlength;
+ unsigned short channelmask;
+ unsigned short encodeopt;
+ unsigned short advancedencodeopt;
+ uint32_t advancedencodeopt2;
+};
+#endif /* __MSM_AUDIO_WMAPRO_H */
diff --git a/original/linux/msm_charm.h b/original/linux/msm_charm.h
new file mode 100644
index 0000000..c31e493
--- /dev/null
+++ b/original/linux/msm_charm.h
@@ -0,0 +1,20 @@
+#ifndef _ARCH_ARM_MACH_MSM_MDM_IOCTLS_H
+#define _ARXH_ARM_MACH_MSM_MDM_IOCTLS_H
+
+
+#define CHARM_CODE 0xCC
+#define WAKE_CHARM _IO(CHARM_CODE, 1)
+#define RESET_CHARM _IO(CHARM_CODE, 2)
+#define CHECK_FOR_BOOT _IOR(CHARM_CODE, 3, int)
+#define WAIT_FOR_BOOT _IO(CHARM_CODE, 4)
+#define NORMAL_BOOT_DONE _IOW(CHARM_CODE, 5, int)
+#define RAM_DUMP_DONE _IOW(CHARM_CODE, 6, int)
+#define WAIT_FOR_RESTART _IOR(CHARM_CODE, 7, int)
+#define GET_DLOAD_STATUS _IOR(CHARM_CODE, 8, int)
+
+enum charm_boot_type {
+ CHARM_NORMAL_BOOT = 0,
+ CHARM_RAM_DUMPS,
+};
+
+#endif
diff --git a/original/linux/msm_dsps.h b/original/linux/msm_dsps.h
new file mode 100644
index 0000000..a5ac256
--- /dev/null
+++ b/original/linux/msm_dsps.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DSPS_H_
+#define _DSPS_H_
+
+#include <linux/ioctl.h>
+
+#define DSPS_IOCTL_MAGIC 'd'
+
+#define DSPS_IOCTL_ON _IO(DSPS_IOCTL_MAGIC, 1)
+#define DSPS_IOCTL_OFF _IO(DSPS_IOCTL_MAGIC, 2)
+
+#define DSPS_IOCTL_READ_SLOW_TIMER _IOR(DSPS_IOCTL_MAGIC, 3, unsigned int*)
+#define DSPS_IOCTL_READ_FAST_TIMER _IOR(DSPS_IOCTL_MAGIC, 4, unsigned int*)
+
+#define DSPS_IOCTL_RESET _IO(DSPS_IOCTL_MAGIC, 5)
+
+#endif /* _DSPS_H_ */
diff --git a/original/linux/msm_kgsl.h b/original/linux/msm_kgsl.h
index 28a1e1e..e67190f 100644
--- a/original/linux/msm_kgsl.h
+++ b/original/linux/msm_kgsl.h
@@ -1,27 +1,22 @@
-/*
- * (C) Copyright Advanced Micro Devices, Inc. 2002, 2007
- * Copyright (c) 2008-2009 QUALCOMM USA, INC.
- *
- * All source code in this file is licensed under the following license
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, you can find it at http://www.fsf.org
- */
#ifndef _MSM_KGSL_H
#define _MSM_KGSL_H
+#define KGSL_VERSION_MAJOR 3
+#define KGSL_VERSION_MINOR 11
+
/*context flags */
-#define KGSL_CONTEXT_SAVE_GMEM 1
-#define KGSL_CONTEXT_NO_GMEM_ALLOC 2
+#define KGSL_CONTEXT_SAVE_GMEM 0x00000001
+#define KGSL_CONTEXT_NO_GMEM_ALLOC 0x00000002
+#define KGSL_CONTEXT_SUBMIT_IB_LIST 0x00000004
+#define KGSL_CONTEXT_CTX_SWITCH 0x00000008
+#define KGSL_CONTEXT_PREAMBLE 0x00000010
+#define KGSL_CONTEXT_TRASH_STATE 0x00000020
+#define KGSL_CONTEXT_PER_CONTEXT_TS 0x00000040
+
+#define KGSL_CONTEXT_INVALID 0xffffffff
+
+/* Memory allocayion flags */
+#define KGSL_MEMFLAGS_GPUREADONLY 0x01000000
/* generic flag values */
#define KGSL_FLAGS_NORMALMODE 0x00000000
@@ -33,13 +28,46 @@
#define KGSL_FLAGS_RESERVED0 0x00000020
#define KGSL_FLAGS_RESERVED1 0x00000040
#define KGSL_FLAGS_RESERVED2 0x00000080
+#define KGSL_FLAGS_SOFT_RESET 0x00000100
+#define KGSL_FLAGS_PER_CONTEXT_TIMESTAMPS 0x00000200
+
+/* Clock flags to show which clocks should be controled by a given platform */
+#define KGSL_CLK_SRC 0x00000001
+#define KGSL_CLK_CORE 0x00000002
+#define KGSL_CLK_IFACE 0x00000004
+#define KGSL_CLK_MEM 0x00000008
+#define KGSL_CLK_MEM_IFACE 0x00000010
+#define KGSL_CLK_AXI 0x00000020
+
+/*
+ * Reset status values for context
+ */
+enum kgsl_ctx_reset_stat {
+ KGSL_CTX_STAT_NO_ERROR = 0x00000000,
+ KGSL_CTX_STAT_GUILTY_CONTEXT_RESET_EXT = 0x00000001,
+ KGSL_CTX_STAT_INNOCENT_CONTEXT_RESET_EXT = 0x00000002,
+ KGSL_CTX_STAT_UNKNOWN_CONTEXT_RESET_EXT = 0x00000003
+};
+
+#define KGSL_MAX_PWRLEVELS 5
+
+#define KGSL_CONVERT_TO_MBPS(val) \
+ (val*1000*1000U)
/* device id */
enum kgsl_deviceid {
- KGSL_DEVICE_ANY = 0x00000000,
- KGSL_DEVICE_YAMATO = 0x00000001,
- KGSL_DEVICE_G12 = 0x00000002,
- KGSL_DEVICE_MAX = 0x00000002
+ KGSL_DEVICE_3D0 = 0x00000000,
+ KGSL_DEVICE_2D0 = 0x00000001,
+ KGSL_DEVICE_2D1 = 0x00000002,
+ KGSL_DEVICE_MAX = 0x00000003
+};
+
+enum kgsl_user_mem_type {
+ KGSL_USER_MEM_TYPE_PMEM = 0x00000000,
+ KGSL_USER_MEM_TYPE_ASHMEM = 0x00000001,
+ KGSL_USER_MEM_TYPE_ADDR = 0x00000002,
+ KGSL_USER_MEM_TYPE_ION = 0x00000003,
+ KGSL_USER_MEM_TYPE_MAX = 0x00000004,
};
struct kgsl_devinfo {
@@ -51,9 +79,11 @@
unsigned int chip_id;
unsigned int mmu_enabled;
unsigned int gmem_gpubaseaddr;
- /* if gmem_hostbaseaddr is NULL, we would know its not mapped into
- * mmio space */
- unsigned int gmem_hostbaseaddr;
+ /*
+ * This field contains the adreno revision
+ * number 200, 205, 220, etc...
+ */
+ unsigned int gpu_id;
unsigned int gmem_sizebytes;
};
@@ -70,17 +100,19 @@
unsigned int sbz3;
volatile unsigned int ref_wait_ts;
unsigned int sbz4;
+ unsigned int current_context;
+ unsigned int sbz5;
};
-#define KGSL_DEVICE_MEMSTORE_OFFSET(field) \
- offsetof(struct kgsl_devmemstore, field)
-
+#define KGSL_MEMSTORE_OFFSET(ctxt_id, field) \
+ ((ctxt_id)*sizeof(struct kgsl_devmemstore) + \
+ offsetof(struct kgsl_devmemstore, field))
/* timestamp id*/
enum kgsl_timestamp_type {
KGSL_TIMESTAMP_CONSUMED = 0x00000001, /* start-of-pipeline timestamp */
KGSL_TIMESTAMP_RETIRED = 0x00000002, /* end-of-pipeline timestamp*/
- KGSL_TIMESTAMP_MAX = 0x00000002,
+ KGSL_TIMESTAMP_QUEUED = 0x00000003,
};
/* property types - used with kgsl_device_getproperty */
@@ -92,6 +124,9 @@
KGSL_PROP_SHMEM_APERTURES = 0x00000005,
KGSL_PROP_MMU_ENABLE = 0x00000006,
KGSL_PROP_INTERRUPT_WAITS = 0x00000007,
+ KGSL_PROP_VERSION = 0x00000008,
+ KGSL_PROP_GPU_RESET_STAT = 0x00000009,
+ KGSL_PROP_PWRCTRL = 0x0000000E,
};
struct kgsl_shadowprop {
@@ -100,6 +135,71 @@
unsigned int flags; /* contains KGSL_FLAGS_ values */
};
+struct kgsl_pwrlevel {
+ unsigned int gpu_freq;
+ unsigned int bus_freq;
+ unsigned int io_fraction;
+};
+
+struct kgsl_version {
+ unsigned int drv_major;
+ unsigned int drv_minor;
+ unsigned int dev_major;
+ unsigned int dev_minor;
+};
+
+#ifdef __KERNEL__
+
+#define KGSL_3D0_REG_MEMORY "kgsl_3d0_reg_memory"
+#define KGSL_3D0_IRQ "kgsl_3d0_irq"
+#define KGSL_2D0_REG_MEMORY "kgsl_2d0_reg_memory"
+#define KGSL_2D0_IRQ "kgsl_2d0_irq"
+#define KGSL_2D1_REG_MEMORY "kgsl_2d1_reg_memory"
+#define KGSL_2D1_IRQ "kgsl_2d1_irq"
+
+enum kgsl_iommu_context_id {
+ KGSL_IOMMU_CONTEXT_USER = 0,
+ KGSL_IOMMU_CONTEXT_PRIV = 1,
+};
+
+struct kgsl_iommu_ctx {
+ const char *iommu_ctx_name;
+ enum kgsl_iommu_context_id ctx_id;
+};
+
+struct kgsl_device_iommu_data {
+ const struct kgsl_iommu_ctx *iommu_ctxs;
+ int iommu_ctx_count;
+ unsigned int physstart;
+ unsigned int physend;
+};
+
+struct kgsl_device_platform_data {
+ struct kgsl_pwrlevel pwrlevel[KGSL_MAX_PWRLEVELS];
+ int init_level;
+ int num_levels;
+ int (*set_grp_async)(void);
+ unsigned int idle_timeout;
+ bool strtstp_sleepwake;
+ unsigned int nap_allowed;
+ unsigned int clk_map;
+ unsigned int idle_needed;
+ struct msm_bus_scale_pdata *bus_scale_table;
+ struct kgsl_device_iommu_data *iommu_data;
+ int iommu_count;
+ struct msm_dcvs_core_info *core_info;
+};
+
+#endif
+
+/* structure holds list of ibs */
+struct kgsl_ibdesc {
+ unsigned int gpuaddr;
+ void *hostptr;
+ unsigned int sizedwords;
+ unsigned int ctrl;
+};
+
/* ioctls */
#define KGSL_IOC_TYPE 0x09
@@ -122,19 +222,8 @@
#define IOCTL_KGSL_DEVICE_GETPROPERTY \
_IOWR(KGSL_IOC_TYPE, 0x2, struct kgsl_device_getproperty)
-
-/* read a GPU register.
- offsetwords it the 32 bit word offset from the beginning of the
- GPU register space.
+/* IOCTL_KGSL_DEVICE_READ (0x3) - removed 03/2012
*/
-struct kgsl_device_regread {
- unsigned int offsetwords;
- unsigned int value; /* output param */
-};
-
-#define IOCTL_KGSL_DEVICE_REGREAD \
- _IOWR(KGSL_IOC_TYPE, 0x3, struct kgsl_device_regread)
-
/* block until the GPU has executed past a given timestamp
* timeout is in milliseconds.
@@ -147,6 +236,14 @@
#define IOCTL_KGSL_DEVICE_WAITTIMESTAMP \
_IOW(KGSL_IOC_TYPE, 0x6, struct kgsl_device_waittimestamp)
+struct kgsl_device_waittimestamp_ctxtid {
+ unsigned int context_id;
+ unsigned int timestamp;
+ unsigned int timeout;
+};
+
+#define IOCTL_KGSL_DEVICE_WAITTIMESTAMP_CTXTID \
+ _IOW(KGSL_IOC_TYPE, 0x7, struct kgsl_device_waittimestamp_ctxtid)
/* issue indirect commands to the GPU.
* drawctxt_id must have been created with IOCTL_KGSL_DRAWCTXT_CREATE
@@ -159,8 +256,8 @@
*/
struct kgsl_ringbuffer_issueibcmds {
unsigned int drawctxt_id;
- unsigned int ibaddr;
- unsigned int sizedwords;
+ unsigned int ibdesc_addr;
+ unsigned int numibs;
unsigned int timestamp; /*output param */
unsigned int flags;
};
@@ -176,9 +273,12 @@
unsigned int timestamp; /*output param */
};
-#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP \
+#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP_OLD \
_IOR(KGSL_IOC_TYPE, 0x11, struct kgsl_cmdstream_readtimestamp)
+#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP \
+ _IOWR(KGSL_IOC_TYPE, 0x11, struct kgsl_cmdstream_readtimestamp)
+
/* free memory when the GPU reaches a given timestamp.
* gpuaddr specify a memory region created by a
* IOCTL_KGSL_SHAREDMEM_FROM_PMEM call
@@ -191,6 +291,15 @@
};
#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP \
+ _IOW(KGSL_IOC_TYPE, 0x12, struct kgsl_cmdstream_freememontimestamp)
+
+/* Previous versions of this header had incorrectly defined
+ IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP as a read-only ioctl instead
+ of a write only ioctl. To ensure binary compatability, the following
+ #define will be used to intercept the incorrect ioctl
+*/
+
+#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_OLD \
_IOR(KGSL_IOC_TYPE, 0x12, struct kgsl_cmdstream_freememontimestamp)
/* create a draw context, which is used to preserve GPU state.
@@ -212,6 +321,42 @@
#define IOCTL_KGSL_DRAWCTXT_DESTROY \
_IOW(KGSL_IOC_TYPE, 0x14, struct kgsl_drawctxt_destroy)
+/* add a block of pmem, fb, ashmem or user allocated address
+ * into the GPU address space */
+struct kgsl_map_user_mem {
+ int fd;
+ unsigned int gpuaddr; /*output param */
+ unsigned int len;
+ unsigned int offset;
+ unsigned int hostptr; /*input param */
+ enum kgsl_user_mem_type memtype;
+ unsigned int reserved; /* May be required to add
+ params for another mem type */
+};
+
+#define IOCTL_KGSL_MAP_USER_MEM \
+ _IOWR(KGSL_IOC_TYPE, 0x15, struct kgsl_map_user_mem)
+
+struct kgsl_cmdstream_readtimestamp_ctxtid {
+ unsigned int context_id;
+ unsigned int type;
+ unsigned int timestamp; /*output param */
+};
+
+#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP_CTXTID \
+ _IOWR(KGSL_IOC_TYPE, 0x16, struct kgsl_cmdstream_readtimestamp_ctxtid)
+
+struct kgsl_cmdstream_freememontimestamp_ctxtid {
+ unsigned int context_id;
+ unsigned int gpuaddr;
+ unsigned int type;
+ unsigned int timestamp;
+};
+
+#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_CTXTID \
+ _IOW(KGSL_IOC_TYPE, 0x17, \
+ struct kgsl_cmdstream_freememontimestamp_ctxtid)
+
/* add a block of pmem or fb into the GPU address space */
struct kgsl_sharedmem_from_pmem {
int pmem_fd;
@@ -231,6 +376,19 @@
#define IOCTL_KGSL_SHAREDMEM_FREE \
_IOW(KGSL_IOC_TYPE, 0x21, struct kgsl_sharedmem_free)
+struct kgsl_cff_user_event {
+ unsigned char cff_opcode;
+ unsigned int op1;
+ unsigned int op2;
+ unsigned int op3;
+ unsigned int op4;
+ unsigned int op5;
+ unsigned int __pad[2];
+};
+
+#define IOCTL_KGSL_CFF_USER_EVENT \
+ _IOW(KGSL_IOC_TYPE, 0x31, struct kgsl_cff_user_event)
+
struct kgsl_gmem_desc {
unsigned int x;
unsigned int y;
@@ -240,9 +398,9 @@
};
struct kgsl_buffer_desc {
- void *hostptr;
+ void *hostptr;
unsigned int gpuaddr;
- int size;
+ int size;
unsigned int format;
unsigned int pitch;
unsigned int enabled;
@@ -264,9 +422,7 @@
struct kgsl_sharedmem_from_vmalloc {
unsigned int gpuaddr; /*output param */
unsigned int hostptr;
- /* If set from user space then will attempt to
- * allocate even if low watermark is crossed */
- int force_no_low_watermark;
+ unsigned int flags;
};
#define IOCTL_KGSL_SHAREDMEM_FROM_VMALLOC \
@@ -283,4 +439,81 @@
#define IOCTL_KGSL_DRAWCTXT_SET_BIN_BASE_OFFSET \
_IOW(KGSL_IOC_TYPE, 0x25, struct kgsl_drawctxt_set_bin_base_offset)
+enum kgsl_cmdwindow_type {
+ KGSL_CMDWINDOW_MIN = 0x00000000,
+ KGSL_CMDWINDOW_2D = 0x00000000,
+ KGSL_CMDWINDOW_3D = 0x00000001, /* legacy */
+ KGSL_CMDWINDOW_MMU = 0x00000002,
+ KGSL_CMDWINDOW_ARBITER = 0x000000FF,
+ KGSL_CMDWINDOW_MAX = 0x000000FF,
+};
+
+/* write to the command window */
+struct kgsl_cmdwindow_write {
+ enum kgsl_cmdwindow_type target;
+ unsigned int addr;
+ unsigned int data;
+};
+
+#define IOCTL_KGSL_CMDWINDOW_WRITE \
+ _IOW(KGSL_IOC_TYPE, 0x2e, struct kgsl_cmdwindow_write)
+
+struct kgsl_gpumem_alloc {
+ unsigned long gpuaddr;
+ size_t size;
+ unsigned int flags;
+};
+
+#define IOCTL_KGSL_GPUMEM_ALLOC \
+ _IOWR(KGSL_IOC_TYPE, 0x2f, struct kgsl_gpumem_alloc)
+
+struct kgsl_cff_syncmem {
+ unsigned int gpuaddr;
+ unsigned int len;
+ unsigned int __pad[2]; /* For future binary compatibility */
+};
+
+#define IOCTL_KGSL_CFF_SYNCMEM \
+ _IOW(KGSL_IOC_TYPE, 0x30, struct kgsl_cff_syncmem)
+
+/*
+ * A timestamp event allows the user space to register an action following an
+ * expired timestamp.
+ */
+
+struct kgsl_timestamp_event {
+ int type; /* Type of event (see list below) */
+ unsigned int timestamp; /* Timestamp to trigger event on */
+ unsigned int context_id; /* Context for the timestamp */
+ void *priv; /* Pointer to the event specific blob */
+ size_t len; /* Size of the event specific blob */
+};
+
+#define IOCTL_KGSL_TIMESTAMP_EVENT \
+ _IOW(KGSL_IOC_TYPE, 0x31, struct kgsl_timestamp_event)
+
+/* A genlock timestamp event releases an existing lock on timestamp expire */
+
+#define KGSL_TIMESTAMP_EVENT_GENLOCK 1
+
+struct kgsl_timestamp_event_genlock {
+ int handle; /* Handle of the genlock lock to release */
+};
+
+/*
+ * Set a property within the kernel. Uses the same structure as
+ * IOCTL_KGSL_GETPROPERTY
+ */
+
+#define IOCTL_KGSL_SETPROPERTY \
+ _IOW(KGSL_IOC_TYPE, 0x32, struct kgsl_device_getproperty)
+
+#ifdef __KERNEL__
+#ifdef CONFIG_MSM_KGSL_DRM
+int kgsl_gem_obj_addr(int drm_fd, int handle, unsigned long *start,
+ unsigned long *len);
+#else
+#define kgsl_gem_obj_addr(...) 0
+#endif
+#endif
#endif /* _MSM_KGSL_H */
diff --git a/original/linux/msm_mdp.h b/original/linux/msm_mdp.h
index 5cffbca..2519a6e 100755
--- a/original/linux/msm_mdp.h
+++ b/original/linux/msm_mdp.h
@@ -1,6 +1,7 @@
/* include/linux/msm_mdp.h
*
* Copyright (C) 2007 Google Incorporated
+ * Copyright (c) 2012 Code Aurora Forum. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -15,25 +16,99 @@
#define _MSM_MDP_H_
#include <linux/types.h>
+#include <linux/fb.h>
#define MSMFB_IOCTL_MAGIC 'm'
#define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int)
#define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int)
+#define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int)
+#define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int)
+#define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor)
+#define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap)
+#define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data)
+/* new ioctls's for set/get ccs matrix */
+#define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs)
+#define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs)
+#define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, \
+ struct mdp_overlay)
+#define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int)
+
+#define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, \
+ struct msmfb_overlay_data)
+#define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY
+
+#define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, \
+ struct mdp_page_protection)
+#define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, \
+ struct mdp_page_protection)
+#define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, \
+ struct mdp_overlay)
+#define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int)
+#define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, \
+ struct msmfb_overlay_blt)
+#define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int)
+#define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, \
+ struct mdp_histogram_start_req)
+#define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int)
+#define MSMFB_NOTIFY_UPDATE _IOW(MSMFB_IOCTL_MAGIC, 146, unsigned int)
+
+#define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, \
+ struct msmfb_overlay_3d)
+
+#define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, \
+ struct msmfb_mixer_info_req)
+#define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, \
+ struct msmfb_overlay_data)
+#define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150)
+#define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151)
+#define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152)
+#define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, \
+ struct msmfb_data)
+#define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, \
+ struct msmfb_data)
+#define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155)
+#define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp)
+#define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int)
+#define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int)
+#define FB_TYPE_3D_PANEL 0x10101010
+#define MDP_IMGTYPE2_START 0x10000
+#define MSMFB_DRIVER_VERSION 0xF9E8D701
enum {
- MDP_RGB_565, // RGB 565 planer
- MDP_XRGB_8888, // RGB 888 padded
- MDP_Y_CBCR_H2V2, // Y and CbCr, pseudo planer w/ Cb is in MSB
- MDP_ARGB_8888, // ARGB 888
- MDP_RGB_888, // RGB 888 planer
- MDP_Y_CRCB_H2V2, // Y and CrCb, pseudo planer w/ Cr is in MSB
- MDP_YCRYCB_H2V1, // YCrYCb interleave
- MDP_Y_CRCB_H2V1, // Y and CrCb, pseduo planer w/ Cr is in MSB
- MDP_Y_CBCR_H2V1, // Y and CrCb, pseduo planer w/ Cr is in MSB
- MDP_RGBA_8888, // ARGB 888
- MDP_BGRA_8888, // ARGB 888
- MDP_RGBX_8888, // RGBX 888
- MDP_IMGTYPE_LIMIT // Non valid image type after this enum
+ NOTIFY_UPDATE_START,
+ NOTIFY_UPDATE_STOP,
+};
+
+enum {
+ MDP_RGB_565, /* RGB 565 planer */
+ MDP_XRGB_8888, /* RGB 888 padded */
+ MDP_Y_CBCR_H2V2, /* Y and CbCr, pseudo planer w/ Cb is in MSB */
+ MDP_Y_CBCR_H2V2_ADRENO,
+ MDP_ARGB_8888, /* ARGB 888 */
+ MDP_RGB_888, /* RGB 888 planer */
+ MDP_Y_CRCB_H2V2, /* Y and CrCb, pseudo planer w/ Cr is in MSB */
+ MDP_YCRYCB_H2V1, /* YCrYCb interleave */
+ MDP_Y_CRCB_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */
+ MDP_Y_CBCR_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */
+ MDP_Y_CRCB_H1V2,
+ MDP_Y_CBCR_H1V2,
+ MDP_RGBA_8888, /* ARGB 888 */
+ MDP_BGRA_8888, /* ABGR 888 */
+ MDP_RGBX_8888, /* RGBX 888 */
+ MDP_Y_CRCB_H2V2_TILE, /* Y and CrCb, pseudo planer tile */
+ MDP_Y_CBCR_H2V2_TILE, /* Y and CbCr, pseudo planer tile */
+ MDP_Y_CR_CB_H2V2, /* Y, Cr and Cb, planar */
+ MDP_Y_CR_CB_GH2V2, /* Y, Cr and Cb, planar aligned to Android YV12 */
+ MDP_Y_CB_CR_H2V2, /* Y, Cb and Cr, planar */
+ MDP_Y_CRCB_H1V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */
+ MDP_Y_CBCR_H1V1, /* Y and CbCr, pseduo planer w/ Cb is in MSB */
+ MDP_YCRCB_H1V1, /* YCrCb interleave */
+ MDP_YCBCR_H1V1, /* YCbCr interleave */
+ MDP_BGR_565, /* BGR 565 planer */
+ MDP_IMGTYPE_LIMIT,
+ MDP_RGB_BORDERFILL, /* border fill pipe */
+ MDP_FB_FORMAT = MDP_IMGTYPE2_START, /* framebuffer format */
+ MDP_IMGTYPE_LIMIT2 /* Non valid image type after this enum */
};
enum {
@@ -41,7 +116,18 @@
FB_IMG,
};
-/* flag values */
+enum {
+ HSIC_HUE = 0,
+ HSIC_SAT,
+ HSIC_INT,
+ HSIC_CON,
+ NUM_HSIC_PARAM,
+};
+
+#define MDSS_MDP_ROT_ONLY 0x80
+#define MDSS_MDP_RIGHT_MIXER 0x100
+
+/* mdp_blit_req flag values */
#define MDP_ROT_NOP 0
#define MDP_FLIP_LR 0x1
#define MDP_FLIP_UD 0x2
@@ -51,10 +137,40 @@
#define MDP_DITHER 0x8
#define MDP_BLUR 0x10
#define MDP_BLEND_FG_PREMULT 0x20000
+#define MDP_DEINTERLACE 0x80000000
+#define MDP_SHARPENING 0x40000000
+#define MDP_NO_DMA_BARRIER_START 0x20000000
+#define MDP_NO_DMA_BARRIER_END 0x10000000
+#define MDP_NO_BLIT 0x08000000
+#define MDP_BLIT_WITH_DMA_BARRIERS 0x000
+#define MDP_BLIT_WITH_NO_DMA_BARRIERS \
+ (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END)
+#define MDP_BLIT_SRC_GEM 0x04000000
+#define MDP_BLIT_DST_GEM 0x02000000
+#define MDP_BLIT_NON_CACHED 0x01000000
+#define MDP_OV_PIPE_SHARE 0x00800000
+#define MDP_DEINTERLACE_ODD 0x00400000
+#define MDP_OV_PLAY_NOWAIT 0x00200000
+#define MDP_SOURCE_ROTATED_90 0x00100000
+#define MDP_OVERLAY_PP_CFG_EN 0x00080000
+#define MDP_BACKEND_COMPOSITION 0x00040000
+#define MDP_BORDERFILL_SUPPORTED 0x00010000
+#define MDP_SECURE_OVERLAY_SESSION 0x00008000
+#define MDP_MEMORY_ID_TYPE_FB 0x00001000
#define MDP_TRANSP_NOP 0xffffffff
#define MDP_ALPHA_NOP 0xff
+#define MDP_FB_PAGE_PROTECTION_NONCACHED (0)
+#define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1)
+#define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2)
+#define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3)
+#define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4)
+/* Sentinel: Don't use! */
+#define MDP_FB_PAGE_PROTECTION_INVALID (5)
+/* Count of the number of MDP_FB_PAGE_PROTECTION_... values. */
+#define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5)
+
struct mdp_rect {
uint32_t x;
uint32_t y;
@@ -68,8 +184,41 @@
uint32_t format;
uint32_t offset;
int memory_id; /* the file descriptor */
+ uint32_t priv;
};
+/*
+ * {3x3} + {3} ccs matrix
+ */
+
+#define MDP_CCS_RGB2YUV 0
+#define MDP_CCS_YUV2RGB 1
+
+#define MDP_CCS_SIZE 9
+#define MDP_BV_SIZE 3
+
+struct mdp_ccs {
+ int direction; /* MDP_CCS_RGB2YUV or YUV2RGB */
+ uint16_t ccs[MDP_CCS_SIZE]; /* 3x3 color coefficients */
+ uint16_t bv[MDP_BV_SIZE]; /* 1x3 bias vector */
+};
+
+struct mdp_csc {
+ int id;
+ uint32_t csc_mv[9];
+ uint32_t csc_pre_bv[3];
+ uint32_t csc_post_bv[3];
+ uint32_t csc_pre_lv[6];
+ uint32_t csc_post_lv[6];
+};
+
+/* The version of the mdp_blit_req structure so that
+ * user applications can selectively decide which functionality
+ * to include
+ */
+
+#define MDP_BLIT_REQ_VERSION 2
+
struct mdp_blit_req {
struct mdp_img src;
struct mdp_img dst;
@@ -78,6 +227,7 @@
uint32_t alpha;
uint32_t transp_mask;
uint32_t flags;
+ int sharpening_strength; /* -127 <--> 127, default 64 */
};
struct mdp_blit_req_list {
@@ -85,4 +235,296 @@
struct mdp_blit_req req[];
};
-#endif //_MSM_MDP_H_
+#define MSMFB_DATA_VERSION 2
+
+struct msmfb_data {
+ uint32_t offset;
+ int memory_id;
+ int id;
+ uint32_t flags;
+ uint32_t priv;
+ uint32_t iova;
+};
+
+#define MSMFB_NEW_REQUEST -1
+
+struct msmfb_overlay_data {
+ uint32_t id;
+ struct msmfb_data data;
+ uint32_t version_key;
+ struct msmfb_data plane1_data;
+ struct msmfb_data plane2_data;
+ struct msmfb_data dst_data;
+};
+
+struct msmfb_img {
+ uint32_t width;
+ uint32_t height;
+ uint32_t format;
+};
+
+#define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1
+struct msmfb_writeback_data {
+ struct msmfb_data buf_info;
+ struct msmfb_img img;
+};
+
+#define MDP_PP_OPS_READ 0x2
+#define MDP_PP_OPS_WRITE 0x4
+
+struct mdp_qseed_cfg {
+ uint32_t table_num;
+ uint32_t ops;
+ uint32_t len;
+ uint32_t *data;
+};
+
+struct mdp_qseed_cfg_data {
+ uint32_t block;
+ struct mdp_qseed_cfg qseed_data;
+};
+
+#define MDP_OVERLAY_PP_CSC_CFG 0x1
+#define MDP_OVERLAY_PP_QSEED_CFG 0x2
+
+#define MDP_CSC_FLAG_ENABLE 0x1
+#define MDP_CSC_FLAG_YUV_IN 0x2
+#define MDP_CSC_FLAG_YUV_OUT 0x4
+
+struct mdp_csc_cfg {
+ /* flags for enable CSC, toggling RGB,YUV input/output */
+ uint32_t flags;
+ uint32_t csc_mv[9];
+ uint32_t csc_pre_bv[3];
+ uint32_t csc_post_bv[3];
+ uint32_t csc_pre_lv[6];
+ uint32_t csc_post_lv[6];
+};
+
+struct mdp_csc_cfg_data {
+ uint32_t block;
+ struct mdp_csc_cfg csc_data;
+};
+
+struct mdp_overlay_pp_params {
+ uint32_t config_ops;
+ struct mdp_csc_cfg csc_cfg;
+ struct mdp_qseed_cfg qseed_cfg[2];
+};
+
+struct mdp_overlay {
+ struct msmfb_img src;
+ struct mdp_rect src_rect;
+ struct mdp_rect dst_rect;
+ uint32_t z_order; /* stage number */
+ uint32_t is_fg; /* control alpha & transp */
+ uint32_t alpha;
+ uint32_t transp_mask;
+ uint32_t flags;
+ uint32_t id;
+ uint32_t user_data[8];
+ struct mdp_overlay_pp_params overlay_pp_cfg;
+};
+
+struct msmfb_overlay_3d {
+ uint32_t is_3d;
+ uint32_t width;
+ uint32_t height;
+};
+
+
+struct msmfb_overlay_blt {
+ uint32_t enable;
+ uint32_t offset;
+ uint32_t width;
+ uint32_t height;
+ uint32_t bpp;
+};
+
+struct mdp_histogram {
+ uint32_t frame_cnt;
+ uint32_t bin_cnt;
+ uint32_t *r;
+ uint32_t *g;
+ uint32_t *b;
+};
+
+
+/*
+
+ mdp_block_type defines the identifiers for each of pipes in MDP 4.3
+
+ MDP_BLOCK_RESERVED is provided for backward compatibility and is
+ deprecated. It corresponds to DMA_P. So MDP_BLOCK_DMA_P should be used
+ instead.
+
+*/
+
+enum {
+ MDP_BLOCK_RESERVED = 0,
+ MDP_BLOCK_OVERLAY_0,
+ MDP_BLOCK_OVERLAY_1,
+ MDP_BLOCK_VG_1,
+ MDP_BLOCK_VG_2,
+ MDP_BLOCK_RGB_1,
+ MDP_BLOCK_RGB_2,
+ MDP_BLOCK_DMA_P,
+ MDP_BLOCK_DMA_S,
+ MDP_BLOCK_DMA_E,
+ MDP_BLOCK_OVERLAY_2,
+ MDP_BLOCK_MAX,
+};
+
+/*
+ * mdp_histogram_start_req is used to provide the parameters for
+ * histogram start request
+ */
+
+struct mdp_histogram_start_req {
+ uint32_t block;
+ uint8_t frame_cnt;
+ uint8_t bit_mask;
+ uint8_t num_bins;
+};
+
+/*
+ * mdp_histogram_data is used to return the histogram data, once
+ * the histogram is done/stopped/cance
+ */
+
+struct mdp_histogram_data {
+ uint32_t block;
+ uint8_t bin_cnt;
+ uint32_t *c0;
+ uint32_t *c1;
+ uint32_t *c2;
+ uint32_t *extra_info;
+};
+
+struct mdp_pcc_coeff {
+ uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1;
+};
+
+struct mdp_pcc_cfg_data {
+ uint32_t block;
+ uint32_t ops;
+ struct mdp_pcc_coeff r, g, b;
+};
+
+enum {
+ mdp_lut_igc,
+ mdp_lut_pgc,
+ mdp_lut_hist,
+ mdp_lut_max,
+};
+
+struct mdp_igc_lut_data {
+ uint32_t block;
+ uint32_t len, ops;
+ uint32_t *c0_c1_data;
+ uint32_t *c2_data;
+};
+
+struct mdp_ar_gc_lut_data {
+ uint32_t x_start;
+ uint32_t slope;
+ uint32_t offset;
+};
+
+struct mdp_pgc_lut_data {
+ uint32_t block;
+ uint32_t flags;
+ uint8_t num_r_stages;
+ uint8_t num_g_stages;
+ uint8_t num_b_stages;
+ struct mdp_ar_gc_lut_data *r_data;
+ struct mdp_ar_gc_lut_data *g_data;
+ struct mdp_ar_gc_lut_data *b_data;
+};
+
+
+struct mdp_hist_lut_data {
+ uint32_t block;
+ uint32_t ops;
+ uint32_t len;
+ uint32_t *data;
+};
+
+struct mdp_lut_cfg_data {
+ uint32_t lut_type;
+ union {
+ struct mdp_igc_lut_data igc_lut_data;
+ struct mdp_pgc_lut_data pgc_lut_data;
+ struct mdp_hist_lut_data hist_lut_data;
+ } data;
+};
+
+struct mdp_bl_scale_data {
+ uint32_t min_lvl;
+ uint32_t scale;
+};
+
+enum {
+ mdp_op_pcc_cfg,
+ mdp_op_csc_cfg,
+ mdp_op_lut_cfg,
+ mdp_op_qseed_cfg,
+ mdp_bl_scale_cfg,
+ mdp_op_max,
+};
+
+struct msmfb_mdp_pp {
+ uint32_t op;
+ union {
+ struct mdp_pcc_cfg_data pcc_cfg_data;
+ struct mdp_csc_cfg_data csc_cfg_data;
+ struct mdp_lut_cfg_data lut_cfg_data;
+ struct mdp_qseed_cfg_data qseed_cfg_data;
+ struct mdp_bl_scale_data bl_scale_data;
+ } data;
+};
+
+
+struct mdp_page_protection {
+ uint32_t page_protection;
+};
+
+
+struct mdp_mixer_info {
+ int pndx;
+ int pnum;
+ int ptype;
+ int mixer_num;
+ int z_order;
+};
+
+#define MAX_PIPE_PER_MIXER 4
+
+struct msmfb_mixer_info_req {
+ int mixer_num;
+ int cnt;
+ struct mdp_mixer_info info[MAX_PIPE_PER_MIXER];
+};
+
+enum {
+ DISPLAY_SUBSYSTEM_ID,
+ ROTATOR_SUBSYSTEM_ID,
+};
+
+#ifdef __KERNEL__
+
+/* get the framebuffer physical address information */
+int get_fb_phys_info(unsigned long *start, unsigned long *len, int fb_num,
+ int subsys_id);
+struct fb_info *msm_fb_get_writeback_fb(void);
+int msm_fb_writeback_init(struct fb_info *info);
+int msm_fb_writeback_start(struct fb_info *info);
+int msm_fb_writeback_queue_buffer(struct fb_info *info,
+ struct msmfb_data *data);
+int msm_fb_writeback_dequeue_buffer(struct fb_info *info,
+ struct msmfb_data *data);
+int msm_fb_writeback_stop(struct fb_info *info);
+int msm_fb_writeback_terminate(struct fb_info *info);
+#endif
+
+#endif /*_MSM_MDP_H_*/
diff --git a/original/linux/msm_rmnet.h b/original/linux/msm_rmnet.h
new file mode 100644
index 0000000..9f52464
--- /dev/null
+++ b/original/linux/msm_rmnet.h
@@ -0,0 +1,54 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _MSM_RMNET_H_
+#define _MSM_RMNET_H_
+
+/* Bitmap macros for RmNET driver operation mode. */
+#define RMNET_MODE_NONE (0x00)
+#define RMNET_MODE_LLP_ETH (0x01)
+#define RMNET_MODE_LLP_IP (0x02)
+#define RMNET_MODE_QOS (0x04)
+#define RMNET_MODE_MASK (RMNET_MODE_LLP_ETH | \
+ RMNET_MODE_LLP_IP | \
+ RMNET_MODE_QOS)
+
+#define RMNET_IS_MODE_QOS(mode) \
+ ((mode & RMNET_MODE_QOS) == RMNET_MODE_QOS)
+#define RMNET_IS_MODE_IP(mode) \
+ ((mode & RMNET_MODE_LLP_IP) == RMNET_MODE_LLP_IP)
+
+/* IOCTL command enum
+ * Values chosen to not conflict with other drivers in the ecosystem */
+enum rmnet_ioctl_cmds_e {
+ RMNET_IOCTL_SET_LLP_ETHERNET = 0x000089F1, /* Set Ethernet protocol */
+ RMNET_IOCTL_SET_LLP_IP = 0x000089F2, /* Set RAWIP protocol */
+ RMNET_IOCTL_GET_LLP = 0x000089F3, /* Get link protocol */
+ RMNET_IOCTL_SET_QOS_ENABLE = 0x000089F4, /* Set QoS header enabled */
+ RMNET_IOCTL_SET_QOS_DISABLE = 0x000089F5, /* Set QoS header disabled*/
+ RMNET_IOCTL_GET_QOS = 0x000089F6, /* Get QoS header state */
+ RMNET_IOCTL_GET_OPMODE = 0x000089F7, /* Get operation mode */
+ RMNET_IOCTL_OPEN = 0x000089F8, /* Open transport port */
+ RMNET_IOCTL_CLOSE = 0x000089F9, /* Close transport port */
+ RMNET_IOCTL_MAX
+};
+
+/* QMI QoS header definition */
+#define QMI_QOS_HDR_S __attribute((__packed__)) qmi_qos_hdr_s
+struct QMI_QOS_HDR_S {
+ unsigned char version;
+ unsigned char flags;
+ unsigned long flow_id;
+};
+
+#endif /* _MSM_RMNET_H_ */
diff --git a/original/linux/msm_rotator.h b/original/linux/msm_rotator.h
new file mode 100644
index 0000000..17ae867
--- /dev/null
+++ b/original/linux/msm_rotator.h
@@ -0,0 +1,62 @@
+#ifndef __MSM_ROTATOR_H__
+#define __MSM_ROTATOR_H__
+
+#include <linux/types.h>
+#include <linux/msm_mdp.h>
+
+#define MSM_ROTATOR_IOCTL_MAGIC 'R'
+
+#define MSM_ROTATOR_IOCTL_START \
+ _IOWR(MSM_ROTATOR_IOCTL_MAGIC, 1, struct msm_rotator_img_info)
+#define MSM_ROTATOR_IOCTL_ROTATE \
+ _IOW(MSM_ROTATOR_IOCTL_MAGIC, 2, struct msm_rotator_data_info)
+#define MSM_ROTATOR_IOCTL_FINISH \
+ _IOW(MSM_ROTATOR_IOCTL_MAGIC, 3, int)
+
+#define ROTATOR_VERSION_01 0xA5B4C301
+
+enum rotator_clk_type {
+ ROTATOR_CORE_CLK,
+ ROTATOR_PCLK,
+ ROTATOR_IMEM_CLK
+};
+
+struct msm_rotator_img_info {
+ unsigned int session_id;
+ struct msmfb_img src;
+ struct msmfb_img dst;
+ struct mdp_rect src_rect;
+ unsigned int dst_x;
+ unsigned int dst_y;
+ unsigned char rotations;
+ int enable;
+ unsigned int downscale_ratio;
+ unsigned int secure;
+};
+
+struct msm_rotator_data_info {
+ int session_id;
+ struct msmfb_data src;
+ struct msmfb_data dst;
+ unsigned int version_key;
+ struct msmfb_data src_chroma;
+ struct msmfb_data dst_chroma;
+};
+
+struct msm_rot_clocks {
+ const char *clk_name;
+ enum rotator_clk_type clk_type;
+ unsigned int clk_rate;
+};
+
+struct msm_rotator_platform_data {
+ unsigned int number_of_clocks;
+ unsigned int hardware_version_number;
+ struct msm_rot_clocks *rotator_clks;
+#ifdef CONFIG_MSM_BUS_SCALING
+ struct msm_bus_scale_pdata *bus_scale_table;
+#endif
+ char rot_iommu_split_domain;
+};
+#endif
+
diff --git a/original/linux/msm_vidc_dec.h b/original/linux/msm_vidc_dec.h
index 2846603..0c03e13 100644
--- a/original/linux/msm_vidc_dec.h
+++ b/original/linux/msm_vidc_dec.h
@@ -1,32 +1,3 @@
-/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
- * * Neither the name of Code Aurora Forum, Inc. nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
#ifndef _MSM_VIDC_DEC_H_
#define _MSM_VIDC_DEC_H_
@@ -64,8 +35,9 @@
#define VDEC_S_ENOTIMPL (VDEC_S_BASE + 12)
/* Command is not implemented by the driver. */
#define VDEC_S_BUSY (VDEC_S_BASE + 13)
+#define VDEC_S_INPUT_BITSTREAM_ERR (VDEC_S_BASE + 14)
-#define VDEC_INTF_VER 1
+#define VDEC_INTF_VER 1
#define VDEC_MSG_BASE 0x0000000
/* Codes to identify asynchronous message responses and events that driver
wants to communicate to the app.*/
@@ -84,6 +56,8 @@
#define VDEC_EVT_RESOURCES_LOST (VDEC_MSG_BASE + 12)
#define VDEC_MSG_EVT_CONFIG_CHANGED (VDEC_MSG_BASE + 13)
#define VDEC_MSG_EVT_HW_ERROR (VDEC_MSG_BASE + 14)
+#define VDEC_MSG_EVT_INFO_CONFIG_CHANGED (VDEC_MSG_BASE + 15)
+#define VDEC_MSG_EVT_INFO_FIELD_DROPPED (VDEC_MSG_BASE + 16)
/*Buffer flags bits masks.*/
#define VDEC_BUFFERFLAG_EOS 0x00000001
@@ -95,10 +69,12 @@
#define VDEC_BUFFERFLAG_CODECCONFIG 0x00000080
/*Post processing flags bit masks*/
-#define VDEC_EXTRADATA_QP 0x00000001
-#define VDEC_EXTRADATA_SEI 0x00000002
-#define VDEC_EXTRADATA_VUI 0x00000004
-#define VDEC_EXTRADATA_MB_ERROR_MAP 0x00000008
+#define VDEC_EXTRADATA_NONE 0x001
+#define VDEC_EXTRADATA_QP 0x004
+#define VDEC_EXTRADATA_MB_ERROR_MAP 0x008
+#define VDEC_EXTRADATA_SEI 0x010
+#define VDEC_EXTRADATA_VUI 0x020
+#define VDEC_EXTRADATA_VC1 0x040
#define VDEC_CMDBASE 0x800
#define VDEC_CMD_SET_INTF_VERSION (VDEC_CMDBASE)
@@ -106,8 +82,8 @@
#define VDEC_IOCTL_MAGIC 'v'
struct vdec_ioctl_msg {
- void *inputparam;
- void *outputparam;
+ void __user *in;
+ void __user *out;
};
/* CMD params: InputParam:enum vdec_codec
@@ -201,12 +177,43 @@
#define VDEC_IOCTL_GET_NUMBER_INSTANCES \
_IOR(VDEC_IOCTL_MAGIC, 27, struct vdec_ioctl_msg)
+#define VDEC_IOCTL_SET_PICTURE_ORDER \
+ _IOW(VDEC_IOCTL_MAGIC, 28, struct vdec_ioctl_msg)
+
+#define VDEC_IOCTL_SET_FRAME_RATE \
+ _IOW(VDEC_IOCTL_MAGIC, 29, struct vdec_ioctl_msg)
+
+#define VDEC_IOCTL_SET_H264_MV_BUFFER \
+ _IOW(VDEC_IOCTL_MAGIC, 30, struct vdec_ioctl_msg)
+
+#define VDEC_IOCTL_FREE_H264_MV_BUFFER \
+ _IOW(VDEC_IOCTL_MAGIC, 31, struct vdec_ioctl_msg)
+
+#define VDEC_IOCTL_GET_MV_BUFFER_SIZE \
+ _IOR(VDEC_IOCTL_MAGIC, 32, struct vdec_ioctl_msg)
+
+#define VDEC_IOCTL_SET_IDR_ONLY_DECODING \
+ _IO(VDEC_IOCTL_MAGIC, 33)
+
+#define VDEC_IOCTL_SET_CONT_ON_RECONFIG \
+ _IO(VDEC_IOCTL_MAGIC, 34)
+
+#define VDEC_IOCTL_SET_DISABLE_DMX \
+ _IOW(VDEC_IOCTL_MAGIC, 35, struct vdec_ioctl_msg)
+
+#define VDEC_IOCTL_GET_DISABLE_DMX \
+ _IOR(VDEC_IOCTL_MAGIC, 36, struct vdec_ioctl_msg)
+
+#define VDEC_IOCTL_GET_DISABLE_DMX_SUPPORT \
+ _IOR(VDEC_IOCTL_MAGIC, 37, struct vdec_ioctl_msg)
+
enum vdec_picture {
PICTURE_TYPE_I,
PICTURE_TYPE_P,
PICTURE_TYPE_B,
PICTURE_TYPE_BI,
PICTURE_TYPE_SKIP,
+ PICTURE_TYPE_IDR,
PICTURE_TYPE_UNKNOWN
};
@@ -220,17 +227,17 @@
uint32_t mincount;
uint32_t maxcount;
uint32_t actualcount;
- uint32_t buffer_size;
+ size_t buffer_size;
uint32_t alignment;
uint32_t buf_poolid;
};
struct vdec_bufferpayload {
- uint8_t *bufferaddr;
- uint32_t buffer_len;
+ void __user *bufferaddr;
+ size_t buffer_len;
int pmem_fd;
- uint32_t offset;
- uint32_t mmaped_size;
+ size_t offset;
+ size_t mmaped_size;
};
struct vdec_setbuffer_cmd {
@@ -463,6 +470,11 @@
VDEC_YUV_FORMAT_TILE_4x2 = 0x2
};
+enum vdec_output_order {
+ VDEC_ORDER_DISPLAY = 0x1,
+ VDEC_ORDER_DECODE = 0x2
+};
+
struct vdec_picsize {
uint32_t frame_width;
uint32_t frame_height;
@@ -471,45 +483,55 @@
};
struct vdec_seqheader {
- uint8_t *ptr_seqheader;
- uint32_t seq_header_len;
+ void __user *ptr_seqheader;
+ size_t seq_header_len;
int pmem_fd;
- uint32_t pmem_offset;
+ size_t pmem_offset;
};
struct vdec_mberror {
- uint8_t *ptr_errormap;
- uint32_t err_mapsize;
+ void __user *ptr_errormap;
+ size_t err_mapsize;
};
struct vdec_input_frameinfo {
- uint8_t *bufferaddr;
- uint32_t offset;
- uint32_t datalen;
+ void __user *bufferaddr;
+ size_t offset;
+ size_t datalen;
uint32_t flags;
int64_t timestamp;
void *client_data;
int pmem_fd;
- uint32_t pmem_offset;
+ size_t pmem_offset;
+ void __user *desc_addr;
+ uint32_t desc_size;
};
struct vdec_framesize {
- uint32_t n_left;
- uint32_t n_top;
- uint32_t n_right;
- uint32_t n_bottom;
+ uint32_t left;
+ uint32_t top;
+ uint32_t right;
+ uint32_t bottom;
+};
+
+struct vdec_aspectratioinfo {
+ uint32_t aspect_ratio;
+ uint32_t par_width;
+ uint32_t par_height;
};
struct vdec_output_frameinfo {
- uint8_t *phy_addr;
- uint8_t *bufferaddr;
- uint32_t offset;
- uint32_t len;
+ void __user *bufferaddr;
+ size_t offset;
+ size_t len;
uint32_t flags;
int64_t time_stamp;
+ enum vdec_picture pic_type;
void *client_data;
void *input_frame_clientdata;
struct vdec_framesize framesize;
+ enum vdec_interlaced_format interlaced_format;
+ struct vdec_aspectratioinfo aspect_ratio_info;
};
union vdec_msgdata {
@@ -521,6 +543,26 @@
uint32_t status_code;
uint32_t msgcode;
union vdec_msgdata msgdata;
- uint32_t msgdatasize;
+ size_t msgdatasize;
};
+
+struct vdec_framerate {
+ unsigned long fps_denominator;
+ unsigned long fps_numerator;
+};
+
+struct vdec_h264_mv{
+ size_t size;
+ int count;
+ int pmem_fd;
+ int offset;
+};
+
+struct vdec_mv_buff_size{
+ int width;
+ int height;
+ int size;
+ int alignment;
+};
+
#endif /* end of macro _VDECDECODER_H_ */
diff --git a/original/linux/msm_vidc_enc.h b/original/linux/msm_vidc_enc.h
index b5cf584..519c537 100644
--- a/original/linux/msm_vidc_enc.h
+++ b/original/linux/msm_vidc_enc.h
@@ -1,31 +1,3 @@
-/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
- * * Neither the name of Code Aurora Forum, Inc. nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
#ifndef _MSM_VIDC_ENC_H_
#define _MSM_VIDC_ENC_H_
@@ -80,6 +52,11 @@
#define VEN_BUFFLAG_EXTRADATA 0x00000040
#define VEN_BUFFLAG_CODECCONFIG 0x00000080
+/*Post processing flags bit masks*/
+#define VEN_EXTRADATA_NONE 0x001
+#define VEN_EXTRADATA_QCOMFILLER 0x002
+#define VEN_EXTRADATA_SLICEINFO 0x100
+
/*ENCODER CONFIGURATION CONSTANTS*/
/*Encoded video frame types*/
@@ -93,42 +70,44 @@
#define VEN_CODEC_H263 3/* H.263 Codec */
/*Video codec profile types.*/
-#define VEN_PROFILE_MPEG4_SP 1/* 1 - MPEG4 SP profile */
-#define VEN_PROFILE_MPEG4_ASP 2/* 2 - MPEG4 ASP profile */
-#define VEN_PROFILE_H264_BASELINE 3/* 3 - H264 Baseline profile */
-#define VEN_PROFILE_H264_MAIN 4/* 4 - H264 Main profile*/
-#define VEN_PROFILE_H264_HIGH 5/* 5 - H264 High profile*/
-#define VEN_PROFILE_H263_BASELINE 6/* 6 - H263 Baseline profile */
+#define VEN_PROFILE_MPEG4_SP 1/* 1 - MPEG4 SP profile */
+#define VEN_PROFILE_MPEG4_ASP 2/* 2 - MPEG4 ASP profile */
+#define VEN_PROFILE_H264_BASELINE 3/* 3 - H264 Baseline profile */
+#define VEN_PROFILE_H264_MAIN 4/* 4 - H264 Main profile */
+#define VEN_PROFILE_H264_HIGH 5/* 5 - H264 High profile */
+#define VEN_PROFILE_H263_BASELINE 6/* 6 - H263 Baseline profile */
/*Video codec profile level types.*/
-#define VEN_LEVEL_MPEG4_0 0x1/* MPEG4 Level 0 */
-#define VEN_LEVEL_MPEG4_1 0x2/* MPEG4 Level 1 */
-#define VEN_LEVEL_MPEG4_2 0x3/* MPEG4 Level 2 */
-#define VEN_LEVEL_MPEG4_3 0x4/* MPEG4 Level 3 */
-#define VEN_LEVEL_MPEG4_4 0x5/* MPEG4 Level 4 */
-#define VEN_LEVEL_MPEG4_5 0x6/* MPEG4 Level 5 */
-#define VEN_LEVEL_MPEG4_3b 0x7/* MPEG4 Level 3b */
-#define VEN_LEVEL_MPEG4_6 0x8/* MPEG4 Level 6 */
+#define VEN_LEVEL_MPEG4_0 0x1/* MPEG4 Level 0 */
+#define VEN_LEVEL_MPEG4_1 0x2/* MPEG4 Level 1 */
+#define VEN_LEVEL_MPEG4_2 0x3/* MPEG4 Level 2 */
+#define VEN_LEVEL_MPEG4_3 0x4/* MPEG4 Level 3 */
+#define VEN_LEVEL_MPEG4_4 0x5/* MPEG4 Level 4 */
+#define VEN_LEVEL_MPEG4_5 0x6/* MPEG4 Level 5 */
+#define VEN_LEVEL_MPEG4_3b 0x7/* MPEG4 Level 3b */
+#define VEN_LEVEL_MPEG4_6 0x8/* MPEG4 Level 6 */
-#define VEN_LEVEL_H264_1 0x9/* H.264 Level 1 */
-#define VEN_LEVEL_H264_1b 0xA/* H.264 Level 1b */
-#define VEN_LEVEL_H264_1p1 0xB/* H.264 Level 1.1 */
-#define VEN_LEVEL_H264_1p2 0xC/* H.264 Level 1.2 */
-#define VEN_LEVEL_H264_1p3 0xD/* H.264 Level 1.3 */
-#define VEN_LEVEL_H264_2 0xE/* H.264 Level 2 */
-#define VEN_LEVEL_H264_2p1 0xF/* H.264 Level 2.1 */
+#define VEN_LEVEL_H264_1 0x9/* H.264 Level 1 */
+#define VEN_LEVEL_H264_1b 0xA/* H.264 Level 1b */
+#define VEN_LEVEL_H264_1p1 0xB/* H.264 Level 1.1 */
+#define VEN_LEVEL_H264_1p2 0xC/* H.264 Level 1.2 */
+#define VEN_LEVEL_H264_1p3 0xD/* H.264 Level 1.3 */
+#define VEN_LEVEL_H264_2 0xE/* H.264 Level 2 */
+#define VEN_LEVEL_H264_2p1 0xF/* H.264 Level 2.1 */
#define VEN_LEVEL_H264_2p2 0x10/* H.264 Level 2.2 */
-#define VEN_LEVEL_H264_3 0x11/* H.264 Level 3 */
+#define VEN_LEVEL_H264_3 0x11/* H.264 Level 3 */
#define VEN_LEVEL_H264_3p1 0x12/* H.264 Level 3.1 */
+#define VEN_LEVEL_H264_3p2 0x13/* H.264 Level 3.2 */
+#define VEN_LEVEL_H264_4 0x14/* H.264 Level 4 */
-#define VEN_LEVEL_H263_10 0x13/* H.263 Level 10 */
-#define VEN_LEVEL_H263_20 0x14/* H.263 Level 20 */
-#define VEN_LEVEL_H263_30 0x15/* H.263 Level 30 */
-#define VEN_LEVEL_H263_40 0x16/* H.263 Level 40 */
-#define VEN_LEVEL_H263_45 0x17/* H.263 Level 45 */
-#define VEN_LEVEL_H263_50 0x18/* H.263 Level 50 */
-#define VEN_LEVEL_H263_60 0x19/* H.263 Level 60 */
-#define VEN_LEVEL_H263_70 0x1A/* H.263 Level 70 */
+#define VEN_LEVEL_H263_10 0x15/* H.263 Level 10 */
+#define VEN_LEVEL_H263_20 0x16/* H.263 Level 20 */
+#define VEN_LEVEL_H263_30 0x17/* H.263 Level 30 */
+#define VEN_LEVEL_H263_40 0x18/* H.263 Level 40 */
+#define VEN_LEVEL_H263_45 0x19/* H.263 Level 45 */
+#define VEN_LEVEL_H263_50 0x1A/* H.263 Level 50 */
+#define VEN_LEVEL_H263_60 0x1B/* H.263 Level 60 */
+#define VEN_LEVEL_H263_70 0x1C/* H.263 Level 70 */
/*Entropy coding model selection for H.264 encoder.*/
#define VEN_ENTROPY_MODEL_CAVLC 1
@@ -154,6 +133,7 @@
#define VEN_RC_VBR_VFR 2
#define VEN_RC_VBR_CFR 3
#define VEN_RC_CBR_VFR 4
+#define VEN_RC_CBR_CFR 5
/*Different modes for flushing buffers*/
#define VEN_FLUSH_INPUT 1
@@ -163,6 +143,7 @@
/*Different input formats for YUV data.*/
#define VEN_INPUTFMT_NV12 1/* NV12 Linear */
#define VEN_INPUTFMT_NV21 2/* NV21 Linear */
+#define VEN_INPUTFMT_NV12_16M2KA 3/* NV12 Linear */
/*Different allowed rotation modes.*/
#define VEN_ROTATION_0 1/* 0 degrees */
@@ -185,8 +166,8 @@
#define VEN_IOCTLBASE_ENC 0x850
struct venc_ioctl_msg{
- void *inputparam;
- void *outputparam;
+ void __user *in;
+ void __user *out;
};
/*NON ENCODER CONFIGURATION IOCTLs*/
@@ -272,6 +253,16 @@
/* Asynchronous respone message code:VEN_MSG_STOP*/
#define VEN_IOCTL_CMD_STOP _IO(VEN_IOCTLBASE_NENC, 19)
+#define VEN_IOCTL_SET_RECON_BUFFER \
+ _IOW(VEN_IOCTLBASE_NENC, 20, struct venc_ioctl_msg)
+
+#define VEN_IOCTL_FREE_RECON_BUFFER \
+ _IOW(VEN_IOCTLBASE_NENC, 21, struct venc_ioctl_msg)
+
+#define VEN_IOCTL_GET_RECON_BUFFER_SIZE \
+ _IOW(VEN_IOCTLBASE_NENC, 22, struct venc_ioctl_msg)
+
+
/*ENCODER PROPERTY CONFIGURATION & CAPABILITY IOCTLs*/
@@ -449,6 +440,24 @@
#define VEN_IOCTL_GET_QP_RANGE \
_IOR(VEN_IOCTLBASE_ENC, 45, struct venc_ioctl_msg)
+#define VEN_IOCTL_GET_NUMBER_INSTANCES \
+ _IOR(VEN_IOCTLBASE_ENC, 46, struct venc_ioctl_msg)
+
+#define VEN_IOCTL_SET_METABUFFER_MODE \
+ _IOW(VEN_IOCTLBASE_ENC, 47, struct venc_ioctl_msg)
+
+
+/*IOCTL params:SET: InputData - unsigned int, OutputData - NULL.*/
+#define VEN_IOCTL_SET_EXTRADATA \
+ _IOW(VEN_IOCTLBASE_ENC, 48, struct venc_ioctl_msg)
+/*IOCTL params:GET: InputData - NULL, OutputData - unsigned int.*/
+#define VEN_IOCTL_GET_EXTRADATA \
+ _IOR(VEN_IOCTLBASE_ENC, 49, struct venc_ioctl_msg)
+
+/*IOCTL params:SET: InputData - NULL, OutputData - NULL.*/
+#define VEN_IOCTL_SET_SLICE_DELIVERY_MODE \
+ _IO(VEN_IOCTLBASE_ENC, 50)
+
struct venc_switch{
unsigned char status;
};
@@ -465,7 +474,7 @@
struct venc_bufferpayload{
unsigned char *pbuffer;
- unsigned long nsize;
+ size_t sz;
int fd;
unsigned int offset;
unsigned int maped_size;
@@ -474,7 +483,7 @@
struct venc_buffer{
unsigned char *ptrbuffer;
- unsigned long size;
+ unsigned long sz;
unsigned long len;
unsigned long offset;
long long timestamp;
@@ -512,6 +521,7 @@
};
struct venc_intraperiod{
unsigned long num_pframes;
+ unsigned long num_bframes;
};
struct venc_seqheader{
unsigned char *hdrbufptr;
@@ -589,4 +599,19 @@
struct venc_buffer buf;
unsigned long msgdata_size;
};
+
+struct venc_recon_addr{
+ unsigned char *pbuffer;
+ unsigned long buffer_size;
+ unsigned long pmem_fd;
+ unsigned long offset;
+};
+
+struct venc_recon_buff_size{
+ int width;
+ int height;
+ int size;
+ int alignment;
+};
+
#endif /* _MSM_VIDC_ENC_H_ */
diff --git a/original/linux/sync.h b/original/linux/sync.h
index 4f19938..75ed5f1 100644
--- a/original/linux/sync.h
+++ b/original/linux/sync.h
@@ -16,6 +16,7 @@
#include <linux/types.h>
#ifdef __KERNEL__
+#include <linux/kref.h>
#include <linux/ktime.h>
#include <linux/list.h>
#include <linux/spinlock.h>
@@ -79,6 +80,7 @@
/**
* struct sync_timeline - sync object
+ * @kref: reference count on fence.
* @ops: ops that define the implementaiton of the sync_timeline
* @name: name of the sync_timeline. Useful for debugging
* @destoryed: set when sync_timeline is destroyed
@@ -89,6 +91,7 @@
* @sync_timeline_list: membership in global sync_timeline_list
*/
struct sync_timeline {
+ struct kref kref;
const struct sync_timeline_ops *ops;
char name[32];
@@ -109,6 +112,7 @@
* @parent: sync_timeline to which this sync_pt belongs
* @child_list: membership in sync_timeline.child_list_head
* @active_list: membership in sync_timeline.active_list_head
+ * @signaled_list: membership in temorary signaled_list on stack
* @fence: sync_fence to which the sync_pt belongs
* @pt_list: membership in sync_fence.pt_list_head
* @status: 1: signaled, 0:active, <0: error
@@ -120,6 +124,7 @@
struct list_head child_list;
struct list_head active_list;
+ struct list_head signaled_list;
struct sync_fence *fence;
struct list_head pt_list;
@@ -133,6 +138,7 @@
/**
* struct sync_fence - sync fence
* @file: file representing this fence
+ * @kref: referenace count on fence.
* @name: name of sync_fence. Useful for debugging
* @pt_list_head: list of sync_pts in ths fence. immutable once fence
* is created
@@ -145,6 +151,7 @@
*/
struct sync_fence {
struct file *file;
+ struct kref kref;
char name[32];
/* this list is immutable once the fence is created */
@@ -159,6 +166,10 @@
struct list_head sync_fence_list;
};
+struct sync_fence_waiter;
+typedef void (*sync_callback_t)(struct sync_fence *fence,
+ struct sync_fence_waiter *waiter);
+
/**
* struct sync_fence_waiter - metadata for asynchronous waiter on a fence
* @waiter_list: membership in sync_fence.waiter_list_head
@@ -168,10 +179,15 @@
struct sync_fence_waiter {
struct list_head waiter_list;
- void (*callback)(struct sync_fence *fence, void *data);
- void *callback_data;
+ sync_callback_t callback;
};
+static inline void sync_fence_waiter_init(struct sync_fence_waiter *waiter,
+ sync_callback_t callback)
+{
+ waiter->callback = callback;
+}
+
/*
* API for sync_timeline implementers
*/
@@ -284,24 +300,37 @@
/**
* sync_fence_wait_async() - registers and async wait on the fence
* @fence: fence to wait on
- * @callback: callback
- * @callback_data data to pass to the callback
+ * @waiter: waiter callback struck
*
* Returns 1 if @fence has already signaled.
*
- * Registers a callback to be called when @fence signals or has an error
+ * Registers a callback to be called when @fence signals or has an error.
+ * @waiter should be initialized with sync_fence_waiter_init().
*/
int sync_fence_wait_async(struct sync_fence *fence,
- void (*callback)(struct sync_fence *, void *data),
- void *callback_data);
+ struct sync_fence_waiter *waiter);
+
+/**
+ * sync_fence_cancel_async() - cancels an async wait
+ * @fence: fence to wait on
+ * @waiter: waiter callback struck
+ *
+ * returns 0 if waiter was removed from fence's async waiter list.
+ * returns -ENOENT if waiter was not found on fence's async waiter list.
+ *
+ * Cancels a previously registered async wait. Will fail gracefully if
+ * @waiter was never registered or if @fence has already signaled @waiter.
+ */
+int sync_fence_cancel_async(struct sync_fence *fence,
+ struct sync_fence_waiter *waiter);
/**
* sync_fence_wait() - wait on fence
* @fence: fence to wait on
* @tiemout: timeout in ms
*
- * Wait for @fence to be signaled or have an error. Waits indefintly
- * if @timeout = 0
+ * Wait for @fence to be signaled or have an error. Waits indefinitely
+ * if @timeout < 0
*/
int sync_fence_wait(struct sync_fence *fence, long timeout);
@@ -360,9 +389,9 @@
/**
* DOC: SYNC_IOC_WAIT - wait for a fence to signal
*
- * pass timeout in milliseconds.
+ * pass timeout in milliseconds. Waits indefinitely timeout < 0.
*/
-#define SYNC_IOC_WAIT _IOW(SYNC_IOC_MAGIC, 0, __u32)
+#define SYNC_IOC_WAIT _IOW(SYNC_IOC_MAGIC, 0, __s32)
/**
* DOC: SYNC_IOC_MERGE - merge two fences
diff --git a/original/linux/uhid.h b/original/linux/uhid.h
new file mode 100644
index 0000000..9c6974f
--- /dev/null
+++ b/original/linux/uhid.h
@@ -0,0 +1,104 @@
+#ifndef __UHID_H_
+#define __UHID_H_
+
+/*
+ * User-space I/O driver support for HID subsystem
+ * Copyright (c) 2012 David Herrmann
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+/*
+ * Public header for user-space communication. We try to keep every structure
+ * aligned but to be safe we also use __attribute__((__packed__)). Therefore,
+ * the communication should be ABI compatible even between architectures.
+ */
+
+#include <linux/input.h>
+#include <linux/types.h>
+
+enum uhid_event_type {
+ UHID_CREATE,
+ UHID_DESTROY,
+ UHID_START,
+ UHID_STOP,
+ UHID_OPEN,
+ UHID_CLOSE,
+ UHID_OUTPUT,
+ UHID_OUTPUT_EV,
+ UHID_INPUT,
+ UHID_FEATURE,
+ UHID_FEATURE_ANSWER,
+};
+
+struct uhid_create_req {
+ __u8 name[128];
+ __u8 phys[64];
+ __u8 uniq[64];
+ __u8 __user *rd_data;
+ __u16 rd_size;
+
+ __u16 bus;
+ __u32 vendor;
+ __u32 product;
+ __u32 version;
+ __u32 country;
+} __attribute__((__packed__));
+
+#define UHID_DATA_MAX 4096
+
+enum uhid_report_type {
+ UHID_FEATURE_REPORT,
+ UHID_OUTPUT_REPORT,
+ UHID_INPUT_REPORT,
+};
+
+struct uhid_input_req {
+ __u8 data[UHID_DATA_MAX];
+ __u16 size;
+} __attribute__((__packed__));
+
+struct uhid_output_req {
+ __u8 data[UHID_DATA_MAX];
+ __u16 size;
+ __u8 rtype;
+} __attribute__((__packed__));
+
+struct uhid_output_ev_req {
+ __u16 type;
+ __u16 code;
+ __s32 value;
+} __attribute__((__packed__));
+
+struct uhid_feature_req {
+ __u32 id;
+ __u8 rnum;
+ __u8 rtype;
+} __attribute__((__packed__));
+
+struct uhid_feature_answer_req {
+ __u32 id;
+ __u16 err;
+ __u16 size;
+ __u8 data[UHID_DATA_MAX];
+};
+
+struct uhid_event {
+ __u32 type;
+
+ union {
+ struct uhid_create_req create;
+ struct uhid_input_req input;
+ struct uhid_output_req output;
+ struct uhid_output_ev_req output_ev;
+ struct uhid_feature_req feature;
+ struct uhid_feature_answer_req feature_answer;
+ } u;
+} __attribute__((__packed__));
+
+#endif /* __UHID_H_ */
diff --git a/original/linux/v4l2-mediabus.h b/original/linux/v4l2-mediabus.h
new file mode 100644
index 0000000..5ea7f75
--- /dev/null
+++ b/original/linux/v4l2-mediabus.h
@@ -0,0 +1,114 @@
+/*
+ * Media Bus API header
+ *
+ * Copyright (C) 2009, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_V4L2_MEDIABUS_H
+#define __LINUX_V4L2_MEDIABUS_H
+
+#include <linux/types.h>
+#include <linux/videodev2.h>
+
+/*
+ * These pixel codes uniquely identify data formats on the media bus. Mostly
+ * they correspond to similarly named V4L2_PIX_FMT_* formats, format 0 is
+ * reserved, V4L2_MBUS_FMT_FIXED shall be used by host-client pairs, where the
+ * data format is fixed. Additionally, "2X8" means that one pixel is transferred
+ * in two 8-bit samples, "BE" or "LE" specify in which order those samples are
+ * transferred over the bus: "LE" means that the least significant bits are
+ * transferred first, "BE" means that the most significant bits are transferred
+ * first, and "PADHI" and "PADLO" define which bits - low or high, in the
+ * incomplete high byte, are filled with padding bits.
+ *
+ * The pixel codes are grouped by type, bus_width, bits per component, samples
+ * per pixel and order of subsamples. Numerical values are sorted using generic
+ * numerical sort order (8 thus comes before 10).
+ *
+ * As their value can't change when a new pixel code is inserted in the
+ * enumeration, the pixel codes are explicitly given a numerical value. The next
+ * free values for each category are listed below, update them when inserting
+ * new pixel codes.
+ */
+enum v4l2_mbus_pixelcode {
+ V4L2_MBUS_FMT_FIXED = 0x0001,
+
+ /* RGB - next is 0x1009 */
+ V4L2_MBUS_FMT_RGB444_2X8_PADHI_BE = 0x1001,
+ V4L2_MBUS_FMT_RGB444_2X8_PADHI_LE = 0x1002,
+ V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE = 0x1003,
+ V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE = 0x1004,
+ V4L2_MBUS_FMT_BGR565_2X8_BE = 0x1005,
+ V4L2_MBUS_FMT_BGR565_2X8_LE = 0x1006,
+ V4L2_MBUS_FMT_RGB565_2X8_BE = 0x1007,
+ V4L2_MBUS_FMT_RGB565_2X8_LE = 0x1008,
+
+ /* YUV (including grey) - next is 0x2014 */
+ V4L2_MBUS_FMT_Y8_1X8 = 0x2001,
+ V4L2_MBUS_FMT_UYVY8_1_5X8 = 0x2002,
+ V4L2_MBUS_FMT_VYUY8_1_5X8 = 0x2003,
+ V4L2_MBUS_FMT_YUYV8_1_5X8 = 0x2004,
+ V4L2_MBUS_FMT_YVYU8_1_5X8 = 0x2005,
+ V4L2_MBUS_FMT_UYVY8_2X8 = 0x2006,
+ V4L2_MBUS_FMT_VYUY8_2X8 = 0x2007,
+ V4L2_MBUS_FMT_YUYV8_2X8 = 0x2008,
+ V4L2_MBUS_FMT_YVYU8_2X8 = 0x2009,
+ V4L2_MBUS_FMT_Y10_1X10 = 0x200a,
+ V4L2_MBUS_FMT_YUYV10_2X10 = 0x200b,
+ V4L2_MBUS_FMT_YVYU10_2X10 = 0x200c,
+ V4L2_MBUS_FMT_Y12_1X12 = 0x2013,
+ V4L2_MBUS_FMT_UYVY8_1X16 = 0x200f,
+ V4L2_MBUS_FMT_VYUY8_1X16 = 0x2010,
+ V4L2_MBUS_FMT_YUYV8_1X16 = 0x2011,
+ V4L2_MBUS_FMT_YVYU8_1X16 = 0x2012,
+ V4L2_MBUS_FMT_YUYV10_1X20 = 0x200d,
+ V4L2_MBUS_FMT_YVYU10_1X20 = 0x200e,
+
+ /* Bayer - next is 0x3015 */
+ V4L2_MBUS_FMT_SBGGR8_1X8 = 0x3001,
+ V4L2_MBUS_FMT_SGBRG8_1X8 = 0x3013,
+ V4L2_MBUS_FMT_SGRBG8_1X8 = 0x3002,
+ V4L2_MBUS_FMT_SRGGB8_1X8 = 0x3014,
+ V4L2_MBUS_FMT_SBGGR10_DPCM8_1X8 = 0x300b,
+ V4L2_MBUS_FMT_SGBRG10_DPCM8_1X8 = 0x300c,
+ V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8 = 0x3009,
+ V4L2_MBUS_FMT_SRGGB10_DPCM8_1X8 = 0x300d,
+ V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_BE = 0x3003,
+ V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE = 0x3004,
+ V4L2_MBUS_FMT_SBGGR10_2X8_PADLO_BE = 0x3005,
+ V4L2_MBUS_FMT_SBGGR10_2X8_PADLO_LE = 0x3006,
+ V4L2_MBUS_FMT_SBGGR10_1X10 = 0x3007,
+ V4L2_MBUS_FMT_SGBRG10_1X10 = 0x300e,
+ V4L2_MBUS_FMT_SGRBG10_1X10 = 0x300a,
+ V4L2_MBUS_FMT_SRGGB10_1X10 = 0x300f,
+ V4L2_MBUS_FMT_SBGGR12_1X12 = 0x3008,
+ V4L2_MBUS_FMT_SGBRG12_1X12 = 0x3010,
+ V4L2_MBUS_FMT_SGRBG12_1X12 = 0x3011,
+ V4L2_MBUS_FMT_SRGGB12_1X12 = 0x3012,
+
+ /* JPEG compressed formats - next is 0x4002 */
+ V4L2_MBUS_FMT_JPEG_1X8 = 0x4001,
+};
+
+/**
+ * struct v4l2_mbus_framefmt - frame format on the media bus
+ * @width: frame width
+ * @height: frame height
+ * @code: data format code (from enum v4l2_mbus_pixelcode)
+ * @field: used interlacing type (from enum v4l2_field)
+ * @colorspace: colorspace of the data (from enum v4l2_colorspace)
+ */
+struct v4l2_mbus_framefmt {
+ __u32 width;
+ __u32 height;
+ __u32 code;
+ __u32 field;
+ __u32 colorspace;
+ __u32 reserved[7];
+};
+
+#endif
diff --git a/original/linux/videodev2.h b/original/linux/videodev2.h
index 5e11f8a..66b68d0 100644
--- a/original/linux/videodev2.h
+++ b/original/linux/videodev2.h
@@ -235,16 +235,25 @@
__u32 denominator;
};
-/*
- * D R I V E R C A P A B I L I T I E S
- */
+/**
+ * struct v4l2_capability - Describes V4L2 device caps returned by VIDIOC_QUERYCAP
+ *
+ * @driver: name of the driver module (e.g. "bttv")
+ * @card: name of the card (e.g. "Hauppauge WinTV")
+ * @bus_info: name of the bus (e.g. "PCI:" + pci_name(pci_dev) )
+ * @version: KERNEL_VERSION
+ * @capabilities: capabilities of the physical device as a whole
+ * @device_caps: capabilities accessed via this particular device (node)
+ * @reserved: reserved fields for future extensions
+ */
struct v4l2_capability {
- __u8 driver[16]; /* i.e. "bttv" */
- __u8 card[32]; /* i.e. "Hauppauge WinTV" */
- __u8 bus_info[32]; /* "PCI:" + pci_name(pci_dev) */
- __u32 version; /* should use KERNEL_VERSION() */
- __u32 capabilities; /* Device capabilities */
- __u32 reserved[4];
+ __u8 driver[16];
+ __u8 card[32];
+ __u8 bus_info[32];
+ __u32 version;
+ __u32 capabilities;
+ __u32 device_caps;
+ __u32 reserved[3];
};
/* Values for 'capabilities' field */
@@ -274,6 +283,8 @@
#define V4L2_CAP_ASYNCIO 0x02000000 /* async I/O */
#define V4L2_CAP_STREAMING 0x04000000 /* streaming I/O ioctls */
+#define V4L2_CAP_DEVICE_CAPS 0x80000000 /* sets device capabilities field */
+
/*
* V I D E O I M A G E F O R M A T
*/
@@ -388,6 +399,9 @@
#define V4L2_PIX_FMT_XVID v4l2_fourcc('X', 'V', 'I', 'D') /* Xvid */
#define V4L2_PIX_FMT_VC1_ANNEX_G v4l2_fourcc('V', 'C', '1', 'G') /* SMPTE 421M Annex G compliant stream */
#define V4L2_PIX_FMT_VC1_ANNEX_L v4l2_fourcc('V', 'C', '1', 'L') /* SMPTE 421M Annex L compliant stream */
+#define V4L2_PIX_FMT_DIVX_311 v4l2_fourcc('D', 'I', 'V', '3') /* DIVX311 */
+#define V4L2_PIX_FMT_DIVX v4l2_fourcc('D', 'I', 'V', 'X') /* DIVX */
+#define V4L2_PIX_FMT_VP8 v4l2_fourcc('V', 'P', '8', '0') /* ON2 VP8 stream */
/* Vendor-specific formats */
#define V4L2_PIX_FMT_CPIA1 v4l2_fourcc('C', 'P', 'I', 'A') /* cpia1 YUV */
@@ -414,7 +428,28 @@
#define V4L2_PIX_FMT_CIT_YYVYUY v4l2_fourcc('C', 'I', 'T', 'V') /* one line of Y then 1 line of VYUY */
#define V4L2_PIX_FMT_KONICA420 v4l2_fourcc('K', 'O', 'N', 'I') /* YUV420 planar in blocks of 256 pixels */
#define V4L2_PIX_FMT_JPGL v4l2_fourcc('J', 'P', 'G', 'L') /* JPEG-Lite */
-#define V4L2_PIX_FMT_SE401 v4l2_fourcc('S', '4', '0', '1') /* se401 janggu compressed rgb */
+/* se401 janggu compressed rgb */
+#define V4L2_PIX_FMT_SE401 v4l2_fourcc('S', '4', '0', '1')
+/* Composite stats */
+#define V4L2_PIX_FMT_STATS_COMB v4l2_fourcc('S', 'T', 'C', 'M')
+/* AEC stats */
+#define V4L2_PIX_FMT_STATS_AE v4l2_fourcc('S', 'T', 'A', 'E')
+/* AF stats */
+#define V4L2_PIX_FMT_STATS_AF v4l2_fourcc('S', 'T', 'A', 'F')
+/* AWB stats */
+#define V4L2_PIX_FMT_STATS_AWB v4l2_fourcc('S', 'T', 'W', 'B')
+/* IHIST stats */
+#define V4L2_PIX_FMT_STATS_IHST v4l2_fourcc('I', 'H', 'S', 'T')
+/* Column count stats */
+#define V4L2_PIX_FMT_STATS_CS v4l2_fourcc('S', 'T', 'C', 'S')
+/* Row count stats */
+#define V4L2_PIX_FMT_STATS_RS v4l2_fourcc('S', 'T', 'R', 'S')
+/* Bayer Grid stats */
+#define V4L2_PIX_FMT_STATS_BG v4l2_fourcc('S', 'T', 'B', 'G')
+/* Bayer focus stats */
+#define V4L2_PIX_FMT_STATS_BF v4l2_fourcc('S', 'T', 'B', 'F')
+/* Bayer hist stats */
+#define V4L2_PIX_FMT_STATS_BHST v4l2_fourcc('B', 'H', 'S', 'T')
/*
* F O R M A T E N U M E R A T I O N
@@ -660,6 +695,7 @@
/* Cache handling flags */
#define V4L2_BUF_FLAG_NO_CACHE_INVALIDATE 0x0800
#define V4L2_BUF_FLAG_NO_CACHE_CLEAN 0x1000
+#define V4L2_BUF_FLAG_EOS 0x2000
/*
* O V E R L A Y P R E V I E W
@@ -720,6 +756,11 @@
/* Flags for 'capability' and 'capturemode' fields */
#define V4L2_MODE_HIGHQUALITY 0x0001 /* High quality imaging mode */
#define V4L2_CAP_TIMEPERFRAME 0x1000 /* timeperframe field is supported */
+#define V4L2_CAP_QCOM_FRAMESKIP 0x2000 /* frame skipping is supported */
+
+struct v4l2_qcom_frameskip {
+ __u64 maxframeinterval;
+};
struct v4l2_outputparm {
__u32 capability; /* Supported modes */
@@ -751,20 +792,20 @@
/* Selection targets */
-/* current cropping area */
-#define V4L2_SEL_TGT_CROP_ACTIVE 0
-/* default cropping area */
-#define V4L2_SEL_TGT_CROP_DEFAULT 1
-/* cropping bounds */
-#define V4L2_SEL_TGT_CROP_BOUNDS 2
-/* current composing area */
-#define V4L2_SEL_TGT_COMPOSE_ACTIVE 256
-/* default composing area */
-#define V4L2_SEL_TGT_COMPOSE_DEFAULT 257
-/* composing bounds */
-#define V4L2_SEL_TGT_COMPOSE_BOUNDS 258
-/* current composing area plus all padding pixels */
-#define V4L2_SEL_TGT_COMPOSE_PADDED 259
+/* Current cropping area */
+#define V4L2_SEL_TGT_CROP_ACTIVE 0x0000
+/* Default cropping area */
+#define V4L2_SEL_TGT_CROP_DEFAULT 0x0001
+/* Cropping bounds */
+#define V4L2_SEL_TGT_CROP_BOUNDS 0x0002
+/* Current composing area */
+#define V4L2_SEL_TGT_COMPOSE_ACTIVE 0x0100
+/* Default composing area */
+#define V4L2_SEL_TGT_COMPOSE_DEFAULT 0x0101
+/* Composing bounds */
+#define V4L2_SEL_TGT_COMPOSE_BOUNDS 0x0102
+/* Current composing area plus all padding pixels */
+#define V4L2_SEL_TGT_COMPOSE_PADDED 0x0103
/**
* struct v4l2_selection - selection info
@@ -774,7 +815,7 @@
* @r: coordinates of selection window
* @reserved: for future use, rounds structure size to 64 bytes, set to zero
*
- * Hardware may use multiple helper window to process a video stream.
+ * Hardware may use multiple helper windows to process a video stream.
* The structure is used to exchange this selection areas between
* an application and a driver.
*/
@@ -1125,6 +1166,7 @@
#define V4L2_CTRL_CLASS_CAMERA 0x009a0000 /* Camera class controls */
#define V4L2_CTRL_CLASS_FM_TX 0x009b0000 /* FM Modulator control class */
#define V4L2_CTRL_CLASS_FLASH 0x009c0000 /* Camera flash controls */
+#define V4L2_CTRL_CLASS_JPEG 0x009d0000 /* JPEG-compression controls */
#define V4L2_CTRL_ID_MASK (0x0fffffff)
#define V4L2_CTRL_ID2CLASS(id) ((id) & 0x0fff0000UL)
@@ -1254,6 +1296,8 @@
/* last CID + 1 */
#define V4L2_CID_LASTP1 (V4L2_CID_BASE+42)
+#define V4L2_CID_SPECIAL_EFFECT (V4L2_CID_BASE+43)
+/* Minimum number of buffer neede by the device */
/* MPEG-class control IDs defined by V4L2 */
#define V4L2_CID_MPEG_BASE (V4L2_CTRL_CLASS_MPEG | 0x900)
@@ -1396,6 +1440,16 @@
V4L2_MPEG_AUDIO_AC3_BITRATE_576K = 17,
V4L2_MPEG_AUDIO_AC3_BITRATE_640K = 18,
};
+#define V4L2_CID_MPEG_AUDIO_DEC_PLAYBACK (V4L2_CID_MPEG_BASE+112)
+enum v4l2_mpeg_audio_dec_playback {
+ V4L2_MPEG_AUDIO_DEC_PLAYBACK_AUTO = 0,
+ V4L2_MPEG_AUDIO_DEC_PLAYBACK_STEREO = 1,
+ V4L2_MPEG_AUDIO_DEC_PLAYBACK_LEFT = 2,
+ V4L2_MPEG_AUDIO_DEC_PLAYBACK_RIGHT = 3,
+ V4L2_MPEG_AUDIO_DEC_PLAYBACK_MONO = 4,
+ V4L2_MPEG_AUDIO_DEC_PLAYBACK_SWAPPED_STEREO = 5,
+};
+#define V4L2_CID_MPEG_AUDIO_DEC_MULTILINGUAL_PLAYBACK (V4L2_CID_MPEG_BASE+113)
/* MPEG video controls specific to multiplexed streams */
#define V4L2_CID_MPEG_VIDEO_ENCODING (V4L2_CID_MPEG_BASE+200)
@@ -1433,7 +1487,7 @@
enum v4l2_mpeg_video_header_mode {
V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE = 0,
V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME = 1,
-
+ V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_I_FRAME = 2,
};
#define V4L2_CID_MPEG_VIDEO_MAX_REF_PIC (V4L2_CID_MPEG_BASE+217)
#define V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE (V4L2_CID_MPEG_BASE+218)
@@ -1446,6 +1500,9 @@
V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES = 2,
};
#define V4L2_CID_MPEG_VIDEO_VBV_SIZE (V4L2_CID_MPEG_BASE+222)
+#define V4L2_CID_MPEG_VIDEO_DEC_PTS (V4L2_CID_MPEG_BASE+223)
+#define V4L2_CID_MPEG_VIDEO_DEC_FRAME (V4L2_CID_MPEG_BASE+224)
+
#define V4L2_CID_MPEG_VIDEO_H263_I_FRAME_QP (V4L2_CID_MPEG_BASE+300)
#define V4L2_CID_MPEG_VIDEO_H263_P_FRAME_QP (V4L2_CID_MPEG_BASE+301)
#define V4L2_CID_MPEG_VIDEO_H263_B_FRAME_QP (V4L2_CID_MPEG_BASE+302)
@@ -1541,6 +1598,7 @@
#define V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP (V4L2_CID_MPEG_BASE+403)
#define V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP (V4L2_CID_MPEG_BASE+404)
#define V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL (V4L2_CID_MPEG_BASE+405)
+
enum v4l2_mpeg_video_mpeg4_level {
V4L2_MPEG_VIDEO_MPEG4_LEVEL_0 = 0,
V4L2_MPEG_VIDEO_MPEG4_LEVEL_0B = 1,
@@ -1604,6 +1662,13 @@
/* MPEG-class control IDs specific to the Samsung MFC 5.1 driver as defined by V4L2 */
#define V4L2_CID_MPEG_MFC51_BASE (V4L2_CTRL_CLASS_MPEG | 0x1100)
+#define V4L2_CID_MPEG_QCOM_BASE (V4L2_CTRL_CLASS_MPEG | 0x2100)
+
+#define V4L2_CID_MPEG_QCOM_SET_PERF_LEVEL (V4L2_CID_MPEG_QCOM_BASE + 0)
+enum v3l2_mpeg_qcom_perf_level {
+ V4L2_CID_MPEG_QCOM_PERF_LEVEL_PERFORMANCE = 0,
+ V4L2_CID_MPEG_QCOM_PERF_LEVEL_TURBO = 1,
+};
#define V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY (V4L2_CID_MPEG_MFC51_BASE+0)
#define V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY_ENABLE (V4L2_CID_MPEG_MFC51_BASE+1)
@@ -1629,6 +1694,109 @@
#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_STATIC (V4L2_CID_MPEG_MFC51_BASE+53)
#define V4L2_CID_MPEG_MFC51_VIDEO_H264_NUM_REF_PIC_FOR_P (V4L2_CID_MPEG_MFC51_BASE+54)
+/* MPEG-class control IDs specific to the msm_vidc driver */
+#define V4L2_CID_MPEG_MSM_VIDC_BASE (V4L2_CTRL_CLASS_MPEG | 0x2000)
+
+#define V4L2_CID_MPEG_VIDC_VIDEO_ENABLE_PICTURE_TYPE \
+ (V4L2_CID_MPEG_MSM_VIDC_BASE+0)
+#define V4L2_CID_MPEG_VIDC_VIDEO_KEEP_ASPECT_RATIO \
+ (V4L2_CID_MPEG_MSM_VIDC_BASE+1)
+#define V4L2_CID_MPEG_VIDC_VIDEO_POST_LOOP_DEBLOCKER_MODE \
+ (V4L2_CID_MPEG_MSM_VIDC_BASE+2)
+#define V4L2_CID_MPEG_VIDC_VIDEO_DIVX_FORMAT \
+ (V4L2_CID_MPEG_MSM_VIDC_BASE+3)
+enum v4l2_mpeg_vidc_video_divx_format_type {
+ V4L2_MPEG_VIDC_VIDEO_DIVX_FORMAT_4 = 0,
+ V4L2_MPEG_VIDC_VIDEO_DIVX_FORMAT_5 = 1,
+ V4L2_MPEG_VIDC_VIDEO_DIVX_FORMAT_6 = 2,
+};
+#define V4L2_CID_MPEG_VIDC_VIDEO_MB_ERROR_MAP_REPORTING \
+ (V4L2_CID_MPEG_MSM_VIDC_BASE+4)
+#define V4L2_CID_MPEG_VIDC_VIDEO_CONTINUE_DATA_TRANSFER \
+ (V4L2_CID_MPEG_MSM_VIDC_BASE+5)
+
+#define V4L2_CID_MPEG_VIDC_VIDEO_STREAM_FORMAT (V4L2_CID_MPEG_MSM_VIDC_BASE+6)
+enum v4l2_mpeg_vidc_video_stream_format {
+ V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_STARTCODES = 0,
+ V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_ONE_NAL_PER_BUFFER = 1,
+ V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_ONE_BYTE_LENGTH = 2,
+ V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_TWO_BYTE_LENGTH = 3,
+ V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_FOUR_BYTE_LENGTH = 4,
+};
+
+#define V4L2_CID_MPEG_VIDC_VIDEO_OUTPUT_ORDER (V4L2_CID_MPEG_MSM_VIDC_BASE+7)
+enum v4l2_mpeg_vidc_video_output_order {
+ V4L2_MPEG_VIDC_VIDEO_OUTPUT_ORDER_DISPLAY = 0,
+ V4L2_MPEG_VIDC_VIDEO_OUTPUT_ORDER_DECODE = 1,
+};
+
+#define V4L2_CID_MPEG_VIDC_VIDEO_FRAME_RATE (V4L2_CID_MPEG_MSM_VIDC_BASE+8)
+#define V4L2_CID_MPEG_VIDC_VIDEO_IDR_PERIOD (V4L2_CID_MPEG_MSM_VIDC_BASE+9)
+#define V4L2_CID_MPEG_VIDC_VIDEO_NUM_P_FRAMES (V4L2_CID_MPEG_MSM_VIDC_BASE+10)
+#define V4L2_CID_MPEG_VIDC_VIDEO_NUM_B_FRAMES (V4L2_CID_MPEG_MSM_VIDC_BASE+11)
+#define V4L2_CID_MPEG_VIDC_VIDEO_REQUEST_IFRAME (V4L2_CID_MPEG_MSM_VIDC_BASE+12)
+
+#define V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL (V4L2_CID_MPEG_MSM_VIDC_BASE+13)
+enum v4l2_mpeg_vidc_video_rate_control {
+ V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_OFF = 0,
+ V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_VBR_VFR = 1,
+ V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_VBR_CFR = 2,
+ V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_CBR_VFR = 3,
+ V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_CBR_CFR = 4,
+};
+
+#define V4L2_CID_MPEG_VIDC_VIDEO_ROTATION (V4L2_CID_MPEG_MSM_VIDC_BASE+14)
+enum v4l2_mpeg_vidc_video_rotation {
+ V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_NONE = 0,
+ V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_90 = 1,
+ V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_180 = 2,
+ V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_270 = 3,
+};
+#define MSM_VIDC_BASE V4L2_CID_MPEG_MSM_VIDC_BASE
+#define V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL (MSM_VIDC_BASE+15)
+enum v4l2_mpeg_vidc_h264_cabac_model {
+ V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL_0 = 0,
+ V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL_1 = 1,
+ V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL_2 = 2,
+};
+
+#define V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_MODE (MSM_VIDC_BASE+16)
+enum v4l2_mpeg_vidc_video_intra_refresh_mode {
+ V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_NONE = 0,
+ V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_CYCLIC = 1,
+ V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_ADAPTIVE = 2,
+ V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_CYCLIC_ADAPTIVE = 3,
+ V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_RANDOM = 4,
+};
+#define V4L2_CID_MPEG_VIDC_VIDEO_AIR_MBS (V4L2_CID_MPEG_MSM_VIDC_BASE+17)
+#define V4L2_CID_MPEG_VIDC_VIDEO_AIR_REF (V4L2_CID_MPEG_MSM_VIDC_BASE+18)
+#define V4L2_CID_MPEG_VIDC_VIDEO_CIR_MBS (V4L2_CID_MPEG_MSM_VIDC_BASE+19)
+
+#define V4L2_CID_MPEG_VIDC_VIDEO_H263_PROFILE (V4L2_CID_MPEG_MSM_VIDC_BASE+20)
+enum v4l2_mpeg_vidc_video_h263_profile {
+ V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_BASELINE = 0,
+ V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_H320CODING = 1,
+ V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_BACKWARDCOMPATIBLE = 2,
+ V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_ISWV2 = 3,
+ V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_ISWV3 = 4,
+ V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_HIGHCOMPRESSION = 5,
+ V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_INTERNET = 6,
+ V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_INTERLACE = 7,
+ V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_HIGHLATENCY = 8,
+};
+
+#define V4L2_CID_MPEG_VIDC_VIDEO_H263_LEVEL (V4L2_CID_MPEG_MSM_VIDC_BASE+21)
+enum v4l2_mpeg_vidc_video_h263_level {
+ V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_1_0 = 0,
+ V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_2_0 = 1,
+ V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_3_0 = 2,
+ V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_4_0 = 3,
+ V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_4_5 = 4,
+ V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_5_0 = 5,
+ V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_6_0 = 6,
+ V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_7_0 = 7,
+};
+
/* Camera class control IDs */
#define V4L2_CID_CAMERA_CLASS_BASE (V4L2_CTRL_CLASS_CAMERA | 0x900)
#define V4L2_CID_CAMERA_CLASS (V4L2_CTRL_CLASS_CAMERA | 1)
@@ -1734,6 +1902,29 @@
#define V4L2_CID_FLASH_CHARGE (V4L2_CID_FLASH_CLASS_BASE + 11)
#define V4L2_CID_FLASH_READY (V4L2_CID_FLASH_CLASS_BASE + 12)
+/* JPEG-class control IDs defined by V4L2 */
+#define V4L2_CID_JPEG_CLASS_BASE (V4L2_CTRL_CLASS_JPEG | 0x900)
+#define V4L2_CID_JPEG_CLASS (V4L2_CTRL_CLASS_JPEG | 1)
+
+#define V4L2_CID_JPEG_CHROMA_SUBSAMPLING (V4L2_CID_JPEG_CLASS_BASE + 1)
+enum v4l2_jpeg_chroma_subsampling {
+ V4L2_JPEG_CHROMA_SUBSAMPLING_444 = 0,
+ V4L2_JPEG_CHROMA_SUBSAMPLING_422 = 1,
+ V4L2_JPEG_CHROMA_SUBSAMPLING_420 = 2,
+ V4L2_JPEG_CHROMA_SUBSAMPLING_411 = 3,
+ V4L2_JPEG_CHROMA_SUBSAMPLING_410 = 4,
+ V4L2_JPEG_CHROMA_SUBSAMPLING_GRAY = 5,
+};
+#define V4L2_CID_JPEG_RESTART_INTERVAL (V4L2_CID_JPEG_CLASS_BASE + 2)
+#define V4L2_CID_JPEG_COMPRESSION_QUALITY (V4L2_CID_JPEG_CLASS_BASE + 3)
+
+#define V4L2_CID_JPEG_ACTIVE_MARKER (V4L2_CID_JPEG_CLASS_BASE + 4)
+#define V4L2_JPEG_ACTIVE_MARKER_APP0 (1 << 0)
+#define V4L2_JPEG_ACTIVE_MARKER_APP1 (1 << 1)
+#define V4L2_JPEG_ACTIVE_MARKER_COM (1 << 16)
+#define V4L2_JPEG_ACTIVE_MARKER_DQT (1 << 17)
+#define V4L2_JPEG_ACTIVE_MARKER_DHT (1 << 18)
+
/*
* T U N I N G
*/
@@ -1897,6 +2088,59 @@
};
};
+/* Decoder commands */
+#define V4L2_DEC_CMD_START (0)
+#define V4L2_DEC_CMD_STOP (1)
+#define V4L2_DEC_CMD_PAUSE (2)
+#define V4L2_DEC_CMD_RESUME (3)
+#define V4L2_DEC_QCOM_CMD_FLUSH (4)
+
+/* Flags for V4L2_DEC_CMD_START */
+#define V4L2_DEC_CMD_START_MUTE_AUDIO (1 << 0)
+
+/* Flags for V4L2_DEC_CMD_PAUSE */
+#define V4L2_DEC_CMD_PAUSE_TO_BLACK (1 << 0)
+
+/* Flags for V4L2_DEC_CMD_STOP */
+#define V4L2_DEC_CMD_STOP_TO_BLACK (1 << 0)
+#define V4L2_DEC_CMD_STOP_IMMEDIATELY (1 << 1)
+
+/* Flags for V4L2_DEC_QCOM_CMD_FLUSH */
+#define V4L2_DEC_QCOM_CMD_FLUSH_OUTPUT (1 << 0)
+#define V4L2_DEC_QCOM_CMD_FLUSH_CAPTURE (1 << 1)
+
+/* Play format requirements (returned by the driver): */
+
+/* The decoder has no special format requirements */
+#define V4L2_DEC_START_FMT_NONE (0)
+/* The decoder requires full GOPs */
+#define V4L2_DEC_START_FMT_GOP (1)
+
+/* The structure must be zeroed before use by the application
+ This ensures it can be extended safely in the future. */
+struct v4l2_decoder_cmd {
+ __u32 cmd;
+ __u32 flags;
+ union {
+ struct {
+ __u64 pts;
+ } stop;
+
+ struct {
+ /* 0 or 1000 specifies normal speed,
+ 1 specifies forward single stepping,
+ -1 specifies backward single stepping,
+ >1: playback at speed/1000 of the normal speed,
+ <-1: reverse playback at (-speed/1000) of the normal speed. */
+ __s32 speed;
+ __u32 format;
+ } start;
+
+ struct {
+ __u32 data[16];
+ } raw;
+ };
+};
#endif
@@ -2102,6 +2346,15 @@
#define V4L2_EVENT_FRAME_SYNC 4
#define V4L2_EVENT_PRIVATE_START 0x08000000
+#define V4L2_EVENT_MSM_VIDC_START (V4L2_EVENT_PRIVATE_START + 0x00001000)
+#define V4L2_EVENT_MSM_VIDC_FLUSH_DONE (V4L2_EVENT_MSM_VIDC_START + 1)
+#define V4L2_EVENT_MSM_VIDC_PORT_SETTINGS_CHANGED_SUFFICIENT \
+ (V4L2_EVENT_MSM_VIDC_START + 2)
+#define V4L2_EVENT_MSM_VIDC_PORT_SETTINGS_CHANGED_INSUFFICIENT \
+ (V4L2_EVENT_MSM_VIDC_START + 3)
+#define V4L2_EVENT_MSM_VIDC_CLOSE_DONE (V4L2_EVENT_MSM_VIDC_START + 4)
+
+
/* Payload for V4L2_EVENT_VSYNC */
struct v4l2_event_vsync {
/* Can be V4L2_FIELD_ANY, _NONE, _TOP or _BOTTOM */
@@ -2307,6 +2560,11 @@
#define VIDIOC_G_SELECTION _IOWR('V', 94, struct v4l2_selection)
#define VIDIOC_S_SELECTION _IOWR('V', 95, struct v4l2_selection)
+/* Experimental, these two ioctls may change over the next couple of kernel
+ versions. */
+#define VIDIOC_DECODER_CMD _IOWR('V', 96, struct v4l2_decoder_cmd)
+#define VIDIOC_TRY_DECODER_CMD _IOWR('V', 97, struct v4l2_decoder_cmd)
+
/* Reminder: when adding new ioctls please add support for them to
drivers/media/video/v4l2-compat-ioctl32.c as well! */
diff --git a/original/media/msm_camera.h b/original/media/msm_camera.h
index c016540..d1d4eaa 100644
--- a/original/media/msm_camera.h
+++ b/original/media/msm_camera.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -9,19 +9,27 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- *
*/
-
#ifndef __LINUX_MSM_CAMERA_H
#define __LINUX_MSM_CAMERA_H
+#ifdef MSM_CAMERA_BIONIC
+#include <sys/types.h>
+#endif
#include <linux/types.h>
-#include <asm/sizes.h>
#include <linux/ioctl.h>
+#ifdef __KERNEL__
+#include <linux/cdev.h>
+#endif
+#ifdef MSM_CAMERA_GCC
+#include <time.h>
+#else
+#include <linux/time.h>
+#endif
+
+#include <linux/ion.h>
+
+#define BIT(nr) (1UL << (nr))
#define MSM_CAM_IOCTL_MAGIC 'm'
@@ -74,24 +82,20 @@
_IOW(MSM_CAM_IOCTL_MAGIC, 16, struct msm_camera_vfe_cfg_cmd *)
#define MSM_CAM_IOCTL_GET_PICTURE \
- _IOW(MSM_CAM_IOCTL_MAGIC, 17, struct msm_camera_ctrl_cmd *)
+ _IOW(MSM_CAM_IOCTL_MAGIC, 17, struct msm_frame *)
#define MSM_CAM_IOCTL_SET_CROP \
_IOW(MSM_CAM_IOCTL_MAGIC, 18, struct crop_info *)
-#define MSM_CAM_IOCTL_PP \
+#define MSM_CAM_IOCTL_PICT_PP \
_IOW(MSM_CAM_IOCTL_MAGIC, 19, uint8_t *)
-#define MSM_CAM_IOCTL_PP_DONE \
+#define MSM_CAM_IOCTL_PICT_PP_DONE \
_IOW(MSM_CAM_IOCTL_MAGIC, 20, struct msm_snapshot_pp_status *)
#define MSM_CAM_IOCTL_SENSOR_IO_CFG \
_IOW(MSM_CAM_IOCTL_MAGIC, 21, struct sensor_cfg_data *)
-#define MSM_CAMERA_LED_OFF 0
-#define MSM_CAMERA_LED_LOW 1
-#define MSM_CAMERA_LED_HIGH 2
-
#define MSM_CAM_IOCTL_FLASH_LED_CFG \
_IOW(MSM_CAM_IOCTL_MAGIC, 22, unsigned *)
@@ -101,25 +105,174 @@
#define MSM_CAM_IOCTL_CTRL_COMMAND_2 \
_IOW(MSM_CAM_IOCTL_MAGIC, 24, struct msm_ctrl_cmd *)
-#define MSM_CAM_IOCTL_ENABLE_OUTPUT_IND \
- _IOW(MSM_CAM_IOCTL_MAGIC, 25, uint32_t *)
-
#define MSM_CAM_IOCTL_AF_CTRL \
- _IOR(MSM_CAM_IOCTL_MAGIC, 26, struct msm_ctrl_cmt_t *)
+ _IOR(MSM_CAM_IOCTL_MAGIC, 25, struct msm_ctrl_cmt_t *)
+
#define MSM_CAM_IOCTL_AF_CTRL_DONE \
- _IOW(MSM_CAM_IOCTL_MAGIC, 27, struct msm_ctrl_cmt_t *)
+ _IOW(MSM_CAM_IOCTL_MAGIC, 26, struct msm_ctrl_cmt_t *)
-#define MAX_SENSOR_NUM 3
+#define MSM_CAM_IOCTL_CONFIG_VPE \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 27, struct msm_camera_vpe_cfg_cmd *)
+
+#define MSM_CAM_IOCTL_AXI_VPE_CONFIG \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 28, struct msm_camera_vpe_cfg_cmd *)
+
+#define MSM_CAM_IOCTL_STROBE_FLASH_CFG \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 29, uint32_t *)
+
+#define MSM_CAM_IOCTL_STROBE_FLASH_CHARGE \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 30, uint32_t *)
+
+#define MSM_CAM_IOCTL_STROBE_FLASH_RELEASE \
+ _IO(MSM_CAM_IOCTL_MAGIC, 31)
+
+#define MSM_CAM_IOCTL_FLASH_CTRL \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 32, struct flash_ctrl_data *)
+
+#define MSM_CAM_IOCTL_ERROR_CONFIG \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 33, uint32_t *)
+
+#define MSM_CAM_IOCTL_ABORT_CAPTURE \
+ _IO(MSM_CAM_IOCTL_MAGIC, 34)
+
+#define MSM_CAM_IOCTL_SET_FD_ROI \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 35, struct fd_roi_info *)
+
+#define MSM_CAM_IOCTL_GET_CAMERA_INFO \
+ _IOR(MSM_CAM_IOCTL_MAGIC, 36, struct msm_camera_info *)
+
+#define MSM_CAM_IOCTL_UNBLOCK_POLL_PIC_FRAME \
+ _IO(MSM_CAM_IOCTL_MAGIC, 37)
+
+#define MSM_CAM_IOCTL_RELEASE_PIC_BUFFER \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 38, struct camera_enable_cmd *)
+
+#define MSM_CAM_IOCTL_PUT_ST_FRAME \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 39, struct msm_camera_st_frame *)
+
+#define MSM_CAM_IOCTL_V4L2_EVT_NOTIFY \
+ _IOR(MSM_CAM_IOCTL_MAGIC, 40, struct v4l2_event *)
+
+#define MSM_CAM_IOCTL_SET_MEM_MAP_INFO \
+ _IOR(MSM_CAM_IOCTL_MAGIC, 41, struct msm_mem_map_info *)
+
+#define MSM_CAM_IOCTL_ACTUATOR_IO_CFG \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 42, struct msm_actuator_cfg_data *)
+
+#define MSM_CAM_IOCTL_MCTL_POST_PROC \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 43, struct msm_mctl_post_proc_cmd *)
+
+#define MSM_CAM_IOCTL_RESERVE_FREE_FRAME \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 44, struct msm_cam_evt_divert_frame *)
+
+#define MSM_CAM_IOCTL_RELEASE_FREE_FRAME \
+ _IOR(MSM_CAM_IOCTL_MAGIC, 45, struct msm_cam_evt_divert_frame *)
+
+#define MSM_CAM_IOCTL_PICT_PP_DIVERT_DONE \
+ _IOR(MSM_CAM_IOCTL_MAGIC, 46, struct msm_pp_frame *)
+
+#define MSM_CAM_IOCTL_SENSOR_V4l2_S_CTRL \
+ _IOR(MSM_CAM_IOCTL_MAGIC, 47, struct v4l2_control)
+
+#define MSM_CAM_IOCTL_SENSOR_V4l2_QUERY_CTRL \
+ _IOR(MSM_CAM_IOCTL_MAGIC, 48, struct v4l2_queryctrl)
+
+#define MSM_CAM_IOCTL_GET_KERNEL_SYSTEM_TIME \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 49, struct timeval *)
+
+#define MSM_CAM_IOCTL_SET_VFE_OUTPUT_TYPE \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 50, uint32_t *)
+
+#define MSM_CAM_IOCTL_MCTL_DIVERT_DONE \
+ _IOR(MSM_CAM_IOCTL_MAGIC, 51, struct msm_cam_evt_divert_frame *)
+
+#define MSM_CAM_IOCTL_GET_ACTUATOR_INFO \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 52, struct msm_actuator_cfg_data *)
+
+#define MSM_CAM_IOCTL_EEPROM_IO_CFG \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 53, struct msm_eeprom_cfg_data *)
+
+#define MSM_CAM_IOCTL_ISPIF_IO_CFG \
+ _IOR(MSM_CAM_IOCTL_MAGIC, 54, struct ispif_cfg_data *)
+
+#define MSM_CAM_IOCTL_STATS_REQBUF \
+ _IOR(MSM_CAM_IOCTL_MAGIC, 55, struct msm_stats_reqbuf *)
+
+#define MSM_CAM_IOCTL_STATS_ENQUEUEBUF \
+ _IOR(MSM_CAM_IOCTL_MAGIC, 56, struct msm_stats_buf_info *)
+
+#define MSM_CAM_IOCTL_STATS_FLUSH_BUFQ \
+ _IOR(MSM_CAM_IOCTL_MAGIC, 57, struct msm_stats_flush_bufq *)
+
+#define MSM_CAM_IOCTL_SET_MCTL_SDEV \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 58, struct msm_mctl_set_sdev_data *)
+
+#define MSM_CAM_IOCTL_UNSET_MCTL_SDEV \
+ _IOW(MSM_CAM_IOCTL_MAGIC, 59, struct msm_mctl_set_sdev_data *)
+
+#define MSM_CAM_IOCTL_GET_INST_HANDLE \
+ _IOR(MSM_CAM_IOCTL_MAGIC, 60, uint32_t *)
+
+#define MSM_CAM_IOCTL_STATS_UNREG_BUF \
+ _IOR(MSM_CAM_IOCTL_MAGIC, 61, struct msm_stats_flush_bufq *)
+
+
+struct msm_stats_reqbuf {
+ int num_buf; /* how many buffers requested */
+ int stats_type; /* stats type */
+};
+
+struct msm_stats_flush_bufq {
+ int stats_type; /* enum msm_stats_enum_type */
+};
+
+struct msm_mctl_pp_cmd {
+ int32_t id;
+ uint16_t length;
+ void *value;
+};
+
+struct msm_mctl_post_proc_cmd {
+ int32_t type;
+ struct msm_mctl_pp_cmd cmd;
+};
+
+#define MSM_CAMERA_LED_OFF 0
+#define MSM_CAMERA_LED_LOW 1
+#define MSM_CAMERA_LED_HIGH 2
+#define MSM_CAMERA_LED_INIT 3
+#define MSM_CAMERA_LED_RELEASE 4
+
+#define MSM_CAMERA_STROBE_FLASH_NONE 0
+#define MSM_CAMERA_STROBE_FLASH_XENON 1
+
+#define MSM_MAX_CAMERA_SENSORS 5
#define MAX_SENSOR_NAME 32
+#define MAX_CAM_NAME_SIZE 32
+#define MAX_ACT_MOD_NAME_SIZE 32
+#define MAX_ACT_NAME_SIZE 32
+#define NUM_ACTUATOR_DIR 2
+#define MAX_ACTUATOR_SCENARIO 8
+#define MAX_ACTUATOR_REGION 5
+#define MAX_ACTUATOR_INIT_SET 12
+#define MAX_ACTUATOR_TYPE_SIZE 32
+#define MAX_ACTUATOR_REG_TBL_SIZE 8
-#define PP_SNAP 1
-#define PP_RAW_SNAP (1<<1)
-#define PP_PREV (1<<2)
-#define PP_MASK (PP_SNAP|PP_RAW_SNAP|PP_PREV)
+
+#define MSM_MAX_CAMERA_CONFIGS 2
+
+#define PP_SNAP 0x01
+#define PP_RAW_SNAP ((0x01)<<1)
+#define PP_PREV ((0x01)<<2)
+#define PP_THUMB ((0x01)<<3)
+#define PP_MASK (PP_SNAP|PP_RAW_SNAP|PP_PREV|PP_THUMB)
#define MSM_CAM_CTRL_CMD_DONE 0
#define MSM_CAM_SENSOR_VFE_CMD 1
+/* Should be same as VIDEO_MAX_PLANES in videodev2.h */
+#define MAX_PLANES 8
+
/*****************************************************
* structure
*****************************************************/
@@ -139,21 +292,111 @@
uint16_t status;
uint32_t timeout_ms;
int resp_fd; /* FIXME: to be used by the kernel, pass-through for now */
+ int vnode_id; /* video dev id. Can we overload resp_fd? */
+ int queue_idx;
+ uint32_t evt_id;
+ uint32_t stream_type; /* used to pass value to qcamera server */
+ int config_ident; /*used as identifier for config node*/
};
-struct msm_vfe_evt_msg {
- unsigned short type; /* 1 == event (RPC), 0 == message (adsp) */
+struct msm_cam_evt_msg {
+ unsigned short type; /* 1 == event (RPC), 0 == message (adsp) */
unsigned short msg_id;
- unsigned int len; /* size in, number of bytes out */
+ unsigned int len; /* size in, number of bytes out */
+ uint32_t frame_id;
void *data;
+ struct timespec timestamp;
};
-#define MSM_CAM_RESP_CTRL 0
-#define MSM_CAM_RESP_STAT_EVT_MSG 1
-#define MSM_CAM_RESP_V4L2 2
-#define MSM_CAM_RESP_MAX 3
+struct msm_pp_frame_sp {
+ /* phy addr of the buffer */
+ unsigned long phy_addr;
+ uint32_t y_off;
+ uint32_t cbcr_off;
+ /* buffer length */
+ uint32_t length;
+ int32_t fd;
+ uint32_t addr_offset;
+ /* mapped addr */
+ unsigned long vaddr;
+};
+
+struct msm_pp_frame_mp {
+ /* phy addr of the plane */
+ unsigned long phy_addr;
+ /* offset of plane data */
+ uint32_t data_offset;
+ /* plane length */
+ uint32_t length;
+ int32_t fd;
+ uint32_t addr_offset;
+ /* mapped addr */
+ unsigned long vaddr;
+};
+
+struct msm_pp_frame {
+ uint32_t handle; /* stores vb cookie */
+ uint32_t frame_id;
+ unsigned short buf_idx;
+ int path;
+ unsigned short image_type;
+ unsigned short num_planes; /* 1 for sp */
+ struct timeval timestamp;
+ union {
+ struct msm_pp_frame_sp sp;
+ struct msm_pp_frame_mp mp[MAX_PLANES];
+ };
+ int node_type;
+ uint32_t inst_handle;
+};
+
+struct msm_cam_evt_divert_frame {
+ unsigned short image_mode;
+ unsigned short op_mode;
+ unsigned short inst_idx;
+ unsigned short node_idx;
+ struct msm_pp_frame frame;
+ int do_pp;
+};
+
+struct msm_mctl_pp_cmd_ack_event {
+ uint32_t cmd; /* VPE_CMD_ZOOM? */
+ int status; /* 0 done, < 0 err */
+ uint32_t cookie; /* daemon's cookie */
+};
+
+struct msm_mctl_pp_event_info {
+ int32_t event;
+ union {
+ struct msm_mctl_pp_cmd_ack_event ack;
+ };
+};
+
+struct msm_isp_event_ctrl {
+ unsigned short resptype;
+ union {
+ struct msm_cam_evt_msg isp_msg;
+ struct msm_ctrl_cmd ctrl;
+ struct msm_cam_evt_divert_frame div_frame;
+ struct msm_mctl_pp_event_info pp_event_info;
+ } isp_data;
+};
+
+#define MSM_CAM_RESP_CTRL 0
+#define MSM_CAM_RESP_STAT_EVT_MSG 1
+#define MSM_CAM_RESP_STEREO_OP_1 2
+#define MSM_CAM_RESP_STEREO_OP_2 3
+#define MSM_CAM_RESP_V4L2 4
+#define MSM_CAM_RESP_DIV_FRAME_EVT_MSG 5
+#define MSM_CAM_RESP_DONE_EVENT 6
+#define MSM_CAM_RESP_MCTL_PP_EVENT 7
+#define MSM_CAM_RESP_MAX 8
+
+#define MSM_CAM_APP_NOTIFY_EVENT 0
+#define MSM_CAM_APP_NOTIFY_ERROR_EVENT 1
/* this one is used to send ctrl/status up to config thread */
+
struct msm_stats_event_ctrl {
/* 0 - ctrl_cmd from control thread,
* 1 - stats/event kernel,
@@ -162,7 +405,7 @@
int timeout_ms;
struct msm_ctrl_cmd ctrl_cmd;
/* struct vfe_event_t stats_event; */
- struct msm_vfe_evt_msg stats_event;
+ struct msm_cam_evt_msg stats_event;
};
/* 2. config command: config command(from config thread); */
@@ -185,35 +428,37 @@
#define CMD_PICT_T_AXI_CFG 4
#define CMD_PICT_M_AXI_CFG 5
#define CMD_RAW_PICT_AXI_CFG 6
-#define CMD_STATS_AXI_CFG 7
-#define CMD_STATS_AF_AXI_CFG 8
-#define CMD_FRAME_BUF_RELEASE 9
-#define CMD_PREV_BUF_CFG 10
-#define CMD_SNAP_BUF_RELEASE 11
-#define CMD_SNAP_BUF_CFG 12
-#define CMD_STATS_DISABLE 13
-#define CMD_STATS_AEC_AWB_ENABLE 14
-#define CMD_STATS_AF_ENABLE 15
-#define CMD_STATS_BUF_RELEASE 16
-#define CMD_STATS_AF_BUF_RELEASE 17
-#define CMD_STATS_ENABLE 18
-#define UPDATE_STATS_INVALID 19
-#define CMD_STATS_AEC_ENABLE 20
-#define CMD_STATS_AWB_ENABLE 21
-#define CMD_STATS_AEC_AXI_CFG 22
-#define CMD_STATS_AWB_AXI_CFG 23
-#define CMD_STATS_RS_AXI_CFG 24
-#define CMD_STATS_CS_AXI_CFG 25
-#define CMD_STATS_IHIST_AXI_CFG 26
-#define CMD_STATS_SKIN_AXI_CFG 27
-#define CMD_STATS_AEC_BUF_RELEASE 28
-#define CMD_STATS_AWB_BUF_RELEASE 29
-#define CMD_STATS_RS_BUF_RELEASE 30
-#define CMD_STATS_CS_BUF_RELEASE 31
-#define CMD_STATS_IHIST_BUF_RELEASE 32
-#define CMD_STATS_SKIN_BUF_RELEASE 33
+#define CMD_FRAME_BUF_RELEASE 7
+#define CMD_PREV_BUF_CFG 8
+#define CMD_SNAP_BUF_RELEASE 9
+#define CMD_SNAP_BUF_CFG 10
+#define CMD_STATS_DISABLE 11
+#define CMD_STATS_AEC_AWB_ENABLE 12
+#define CMD_STATS_AF_ENABLE 13
+#define CMD_STATS_AEC_ENABLE 14
+#define CMD_STATS_AWB_ENABLE 15
+#define CMD_STATS_ENABLE 16
+#define CMD_STATS_AXI_CFG 17
+#define CMD_STATS_AEC_AXI_CFG 18
+#define CMD_STATS_AF_AXI_CFG 19
+#define CMD_STATS_AWB_AXI_CFG 20
+#define CMD_STATS_RS_AXI_CFG 21
+#define CMD_STATS_CS_AXI_CFG 22
+#define CMD_STATS_IHIST_AXI_CFG 23
+#define CMD_STATS_SKIN_AXI_CFG 24
+
+#define CMD_STATS_BUF_RELEASE 25
+#define CMD_STATS_AEC_BUF_RELEASE 26
+#define CMD_STATS_AF_BUF_RELEASE 27
+#define CMD_STATS_AWB_BUF_RELEASE 28
+#define CMD_STATS_RS_BUF_RELEASE 29
+#define CMD_STATS_CS_BUF_RELEASE 30
+#define CMD_STATS_IHIST_BUF_RELEASE 31
+#define CMD_STATS_SKIN_BUF_RELEASE 32
+
+#define UPDATE_STATS_INVALID 33
#define CMD_AXI_CFG_SNAP_GEMINI 34
#define CMD_AXI_CFG_SNAP 35
#define CMD_AXI_CFG_PREVIEW 36
@@ -222,7 +467,46 @@
#define CMD_STATS_IHIST_ENABLE 38
#define CMD_STATS_RS_ENABLE 39
#define CMD_STATS_CS_ENABLE 40
-#define CMD_AXI_CFG_O1_AND_O2 41 /* output1 and output2 */
+#define CMD_VPE 41
+#define CMD_AXI_CFG_VPE 42
+#define CMD_AXI_CFG_ZSL 43
+#define CMD_AXI_CFG_SNAP_VPE 44
+#define CMD_AXI_CFG_SNAP_THUMB_VPE 45
+
+#define CMD_CONFIG_PING_ADDR 46
+#define CMD_CONFIG_PONG_ADDR 47
+#define CMD_CONFIG_FREE_BUF_ADDR 48
+#define CMD_AXI_CFG_ZSL_ALL_CHNLS 49
+#define CMD_AXI_CFG_VIDEO_ALL_CHNLS 50
+#define CMD_VFE_BUFFER_RELEASE 51
+#define CMD_VFE_PROCESS_IRQ 52
+#define CMD_STATS_BG_ENABLE 53
+#define CMD_STATS_BF_ENABLE 54
+#define CMD_STATS_BHIST_ENABLE 55
+#define CMD_STATS_BG_BUF_RELEASE 56
+#define CMD_STATS_BF_BUF_RELEASE 57
+#define CMD_STATS_BHIST_BUF_RELEASE 58
+#define CMD_VFE_SOF_COUNT_UPDATE 59
+#define CMD_VFE_COUNT_SOF_ENABLE 60
+
+#define CMD_AXI_CFG_PRIM BIT(8)
+#define CMD_AXI_CFG_PRIM_ALL_CHNLS BIT(9)
+#define CMD_AXI_CFG_SEC BIT(10)
+#define CMD_AXI_CFG_SEC_ALL_CHNLS BIT(11)
+#define CMD_AXI_CFG_TERT1 BIT(12)
+#define CMD_AXI_CFG_TERT2 BIT(13)
+
+#define CMD_AXI_START 0xE1
+#define CMD_AXI_STOP 0xE2
+#define CMD_AXI_RESET 0xE3
+
+
+#define AXI_CMD_PREVIEW BIT(0)
+#define AXI_CMD_CAPTURE BIT(1)
+#define AXI_CMD_RECORD BIT(2)
+#define AXI_CMD_ZSL BIT(3)
+#define AXI_CMD_RAW_CAPTURE BIT(4)
+#define AXI_CMD_LIVESHOT BIT(5)
/* vfe config command: config command(from config thread)*/
struct msm_vfe_cfg_cmd {
@@ -231,6 +515,12 @@
void *value;
};
+struct msm_vpe_cfg_cmd {
+ int cmd_type;
+ uint16_t length;
+ void *value;
+};
+
#define MAX_CAMERA_ENABLE_NAME_LEN 32
struct camera_enable_cmd {
char name[MAX_CAMERA_ENABLE_NAME_LEN];
@@ -246,30 +536,83 @@
#define MSM_PMEM_AF 7
#define MSM_PMEM_AEC 8
#define MSM_PMEM_AWB 9
-#define MSM_PMEM_RS 10
-#define MSM_PMEM_CS 11
+#define MSM_PMEM_RS 10
+#define MSM_PMEM_CS 11
#define MSM_PMEM_IHIST 12
#define MSM_PMEM_SKIN 13
#define MSM_PMEM_VIDEO 14
#define MSM_PMEM_PREVIEW 15
-#define MSM_PMEM_MAX 16
+#define MSM_PMEM_VIDEO_VPE 16
+#define MSM_PMEM_C2D 17
+#define MSM_PMEM_MAINIMG_VPE 18
+#define MSM_PMEM_THUMBNAIL_VPE 19
+#define MSM_PMEM_BAYER_GRID 20
+#define MSM_PMEM_BAYER_FOCUS 21
+#define MSM_PMEM_BAYER_HIST 22
+#define MSM_PMEM_MAX 23
+
+#define STAT_AEAW 0
+#define STAT_AEC 1
+#define STAT_AF 2
+#define STAT_AWB 3
+#define STAT_RS 4
+#define STAT_CS 5
+#define STAT_IHIST 6
+#define STAT_SKIN 7
+#define STAT_BG 8
+#define STAT_BF 9
+#define STAT_BHIST 10
+#define STAT_MAX 11
#define FRAME_PREVIEW_OUTPUT1 0
#define FRAME_PREVIEW_OUTPUT2 1
#define FRAME_SNAPSHOT 2
-#define FRAME_THUMBNAIL 3
+#define FRAME_THUMBNAIL 3
#define FRAME_RAW_SNAPSHOT 4
#define FRAME_MAX 5
+enum msm_stats_enum_type {
+ MSM_STATS_TYPE_AEC, /* legacy based AEC */
+ MSM_STATS_TYPE_AF, /* legacy based AF */
+ MSM_STATS_TYPE_AWB, /* legacy based AWB */
+ MSM_STATS_TYPE_RS, /* legacy based RS */
+ MSM_STATS_TYPE_CS, /* legacy based CS */
+ MSM_STATS_TYPE_IHIST, /* legacy based HIST */
+ MSM_STATS_TYPE_SKIN, /* legacy based SKIN */
+ MSM_STATS_TYPE_BG, /* Bayer Grids */
+ MSM_STATS_TYPE_BF, /* Bayer Focus */
+ MSM_STATS_TYPE_BHIST, /* Bayer Hist */
+ MSM_STATS_TYPE_AE_AW, /* legacy stats for vfe 2.x*/
+ MSM_STATS_TYPE_MAX /* MAX */
+};
+
+struct msm_stats_buf_info {
+ int type; /* msm_stats_enum_type */
+ int fd;
+ void *vaddr;
+ uint32_t offset;
+ uint32_t len;
+ uint32_t y_off;
+ uint32_t cbcr_off;
+ uint32_t planar0_off;
+ uint32_t planar1_off;
+ uint32_t planar2_off;
+ uint8_t active;
+ int buf_idx;
+};
+
struct msm_pmem_info {
int type;
int fd;
void *vaddr;
uint32_t offset;
uint32_t len;
- uint32_t y_off; /* relative to offset */
- uint32_t cbcr_off; /* relative to offset */
- uint8_t vfe_can_write;
+ uint32_t y_off;
+ uint32_t cbcr_off;
+ uint32_t planar0_off;
+ uint32_t planar1_off;
+ uint32_t planar2_off;
+ uint8_t active;
};
struct outputCfg {
@@ -280,61 +623,236 @@
uint32_t window_height_lastline;
};
+#define VIDEO_NODE 0
+#define MCTL_NODE 1
+
#define OUTPUT_1 0
#define OUTPUT_2 1
-#define OUTPUT_1_AND_2 2
-#define CAMIF_TO_AXI_VIA_OUTPUT_2 3
-#define OUTPUT_1_AND_CAMIF_TO_AXI_VIA_OUTPUT_2 4
-#define OUTPUT_2_AND_CAMIF_TO_AXI_VIA_OUTPUT_1 5
-#define OUTPUT_1_AND_3 6
-#define LAST_AXI_OUTPUT_MODE_ENUM = OUTPUT_1_AND_3 7 /* video */
+#define OUTPUT_1_AND_2 2 /* snapshot only */
+#define OUTPUT_1_AND_3 3 /* video */
+#define CAMIF_TO_AXI_VIA_OUTPUT_2 4
+#define OUTPUT_1_AND_CAMIF_TO_AXI_VIA_OUTPUT_2 5
+#define OUTPUT_2_AND_CAMIF_TO_AXI_VIA_OUTPUT_1 6
+#define OUTPUT_1_2_AND_3 7
+#define OUTPUT_ALL_CHNLS 8
+#define OUTPUT_VIDEO_ALL_CHNLS 9
+#define OUTPUT_ZSL_ALL_CHNLS 10
+#define LAST_AXI_OUTPUT_MODE_ENUM = OUTPUT_ZSL_ALL_CHNLS
+
+#define OUTPUT_PRIM BIT(8)
+#define OUTPUT_PRIM_ALL_CHNLS BIT(9)
+#define OUTPUT_SEC BIT(10)
+#define OUTPUT_SEC_ALL_CHNLS BIT(11)
+#define OUTPUT_TERT1 BIT(12)
+#define OUTPUT_TERT2 BIT(13)
+
#define MSM_FRAME_PREV_1 0
#define MSM_FRAME_PREV_2 1
#define MSM_FRAME_ENC 2
-#define OUTPUT_TYPE_P 1
-#define OUTPUT_TYPE_T 2
-#define OUTPUT_TYPE_S 3
-#define OUTPUT_TYPE_V 4
+#define OUTPUT_TYPE_P BIT(0)
+#define OUTPUT_TYPE_T BIT(1)
+#define OUTPUT_TYPE_S BIT(2)
+#define OUTPUT_TYPE_V BIT(3)
+#define OUTPUT_TYPE_L BIT(4)
+#define OUTPUT_TYPE_ST_L BIT(5)
+#define OUTPUT_TYPE_ST_R BIT(6)
+#define OUTPUT_TYPE_ST_D BIT(7)
+#define OUTPUT_TYPE_R BIT(8)
+#define OUTPUT_TYPE_R1 BIT(9)
+
+
+
+struct fd_roi_info {
+ void *info;
+ int info_len;
+};
+
+struct msm_mem_map_info {
+ uint32_t cookie;
+ uint32_t length;
+ uint32_t mem_type;
+};
+
+#define MSM_MEM_MMAP 0
+#define MSM_MEM_USERPTR 1
+#define MSM_PLANE_MAX 8
+#define MSM_PLANE_Y 0
+#define MSM_PLANE_UV 1
struct msm_frame {
+ struct timespec ts;
int path;
+ int type;
unsigned long buffer;
+ uint32_t phy_offset;
uint32_t y_off;
uint32_t cbcr_off;
+ uint32_t planar0_off;
+ uint32_t planar1_off;
+ uint32_t planar2_off;
int fd;
void *cropinfo;
int croplen;
+ uint32_t error_code;
+ struct fd_roi_info roi_info;
+ uint32_t frame_id;
+ int stcam_quality_ind;
+ uint32_t stcam_conv_value;
+
+ struct ion_allocation_data ion_alloc;
+ struct ion_fd_data fd_data;
+ int ion_dev_fd;
};
-#define STAT_AEAW 0
-#define STAT_AF 1
-#define STAT_AEC 2
-#define STAT_AWB 3
-#define STAT_RS 4
-#define STAT_CS 5
-#define STAT_IHIST 6
-#define STAT_SKIN 7
-#define STAT_MAX 8
+enum msm_st_frame_packing {
+ SIDE_BY_SIDE_HALF,
+ SIDE_BY_SIDE_FULL,
+ TOP_DOWN_HALF,
+ TOP_DOWN_FULL,
+};
-struct msm_stats_buf {
+struct msm_st_crop {
+ uint32_t in_w;
+ uint32_t in_h;
+ uint32_t out_w;
+ uint32_t out_h;
+};
+
+struct msm_st_half {
+ uint32_t buf_p0_off;
+ uint32_t buf_p1_off;
+ uint32_t buf_p0_stride;
+ uint32_t buf_p1_stride;
+ uint32_t pix_x_off;
+ uint32_t pix_y_off;
+ struct msm_st_crop stCropInfo;
+};
+
+struct msm_st_frame {
+ struct msm_frame buf_info;
int type;
- unsigned long buffer;
+ enum msm_st_frame_packing packing;
+ struct msm_st_half L;
+ struct msm_st_half R;
+ int frame_id;
+};
+
+#define MSM_CAMERA_ERR_MASK (0xFFFFFFFF & 1)
+
+struct stats_buff {
+ unsigned long buff;
int fd;
};
+struct msm_stats_buf {
+ uint8_t awb_ymin;
+ struct stats_buff aec;
+ struct stats_buff awb;
+ struct stats_buff af;
+ struct stats_buff ihist;
+ struct stats_buff rs;
+ struct stats_buff cs;
+ struct stats_buff skin;
+ int type;
+ uint32_t status_bits;
+ unsigned long buffer;
+ int fd;
+ int length;
+ struct ion_handle *handle;
+ uint32_t frame_id;
+ int buf_idx;
+};
+#define MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT 0
+/* video capture mode in VIDIOC_S_PARM */
+#define MSM_V4L2_EXT_CAPTURE_MODE_PREVIEW \
+ (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+1)
+/* extendedmode for video recording in VIDIOC_S_PARM */
+#define MSM_V4L2_EXT_CAPTURE_MODE_VIDEO \
+ (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+2)
+/* extendedmode for the full size main image in VIDIOC_S_PARM */
+#define MSM_V4L2_EXT_CAPTURE_MODE_MAIN (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+3)
+/* extendedmode for the thumb nail image in VIDIOC_S_PARM */
+#define MSM_V4L2_EXT_CAPTURE_MODE_THUMBNAIL \
+ (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+4)
+#define MSM_V4L2_EXT_CAPTURE_MODE_RAW \
+ (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+5)
+#define MSM_V4L2_EXT_CAPTURE_MODE_RDI \
+ (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+6)
+#define MSM_V4L2_EXT_CAPTURE_MODE_RDI1 \
+ (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+7)
+#define MSM_V4L2_EXT_CAPTURE_MODE_RDI2 \
+ (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+8)
+#define MSM_V4L2_EXT_CAPTURE_MODE_AEC \
+ (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+9)
+#define MSM_V4L2_EXT_CAPTURE_MODE_AWB \
+ (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+10)
+#define MSM_V4L2_EXT_CAPTURE_MODE_AF \
+ (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+11)
+#define MSM_V4L2_EXT_CAPTURE_MODE_IHIST \
+ (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+12)
+#define MSM_V4L2_EXT_CAPTURE_MODE_CS \
+ (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+13)
+#define MSM_V4L2_EXT_CAPTURE_MODE_RS \
+ (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+14)
+#define MSM_V4L2_EXT_CAPTURE_MODE_MAX (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+15)
+
+#define MSM_V4L2_PID_MOTION_ISO V4L2_CID_PRIVATE_BASE
+#define MSM_V4L2_PID_EFFECT (V4L2_CID_PRIVATE_BASE+1)
+#define MSM_V4L2_PID_HJR (V4L2_CID_PRIVATE_BASE+2)
+#define MSM_V4L2_PID_LED_MODE (V4L2_CID_PRIVATE_BASE+3)
+#define MSM_V4L2_PID_PREP_SNAPSHOT (V4L2_CID_PRIVATE_BASE+4)
+#define MSM_V4L2_PID_EXP_METERING (V4L2_CID_PRIVATE_BASE+5)
+#define MSM_V4L2_PID_ISO (V4L2_CID_PRIVATE_BASE+6)
+#define MSM_V4L2_PID_CAM_MODE (V4L2_CID_PRIVATE_BASE+7)
+#define MSM_V4L2_PID_LUMA_ADAPTATION (V4L2_CID_PRIVATE_BASE+8)
+#define MSM_V4L2_PID_BEST_SHOT (V4L2_CID_PRIVATE_BASE+9)
+#define MSM_V4L2_PID_FOCUS_MODE (V4L2_CID_PRIVATE_BASE+10)
+#define MSM_V4L2_PID_BL_DETECTION (V4L2_CID_PRIVATE_BASE+11)
+#define MSM_V4L2_PID_SNOW_DETECTION (V4L2_CID_PRIVATE_BASE+12)
+#define MSM_V4L2_PID_CTRL_CMD (V4L2_CID_PRIVATE_BASE+13)
+#define MSM_V4L2_PID_EVT_SUB_INFO (V4L2_CID_PRIVATE_BASE+14)
+#define MSM_V4L2_PID_STROBE_FLASH (V4L2_CID_PRIVATE_BASE+15)
+#define MSM_V4L2_PID_INST_HANDLE (V4L2_CID_PRIVATE_BASE+16)
+#define MSM_V4L2_PID_MMAP_INST (V4L2_CID_PRIVATE_BASE+17)
+#define MSM_V4L2_PID_PP_PLANE_INFO (V4L2_CID_PRIVATE_BASE+18)
+#define MSM_V4L2_PID_MAX MSM_V4L2_PID_PP_PLANE_INFO
+
+/* camera operation mode for video recording - two frame output queues */
+#define MSM_V4L2_CAM_OP_DEFAULT 0
+/* camera operation mode for video recording - two frame output queues */
+#define MSM_V4L2_CAM_OP_PREVIEW (MSM_V4L2_CAM_OP_DEFAULT+1)
+/* camera operation mode for video recording - two frame output queues */
+#define MSM_V4L2_CAM_OP_VIDEO (MSM_V4L2_CAM_OP_DEFAULT+2)
+/* camera operation mode for standard shapshot - two frame output queues */
+#define MSM_V4L2_CAM_OP_CAPTURE (MSM_V4L2_CAM_OP_DEFAULT+3)
+/* camera operation mode for zsl shapshot - three output queues */
+#define MSM_V4L2_CAM_OP_ZSL (MSM_V4L2_CAM_OP_DEFAULT+4)
+/* camera operation mode for raw snapshot - one frame output queue */
+#define MSM_V4L2_CAM_OP_RAW (MSM_V4L2_CAM_OP_DEFAULT+5)
+/* camera operation mode for jpeg snapshot - one frame output queue */
+#define MSM_V4L2_CAM_OP_JPEG_CAPTURE (MSM_V4L2_CAM_OP_DEFAULT+6)
+
+
#define MSM_V4L2_VID_CAP_TYPE 0
-#define MSM_V4L2_STREAM_ON 1
-#define MSM_V4L2_STREAM_OFF 2
-#define MSM_V4L2_SNAPSHOT 3
-#define MSM_V4L2_QUERY_CTRL 4
-#define MSM_V4L2_GET_CTRL 5
-#define MSM_V4L2_SET_CTRL 6
-#define MSM_V4L2_QUERY 7
-#define MSM_V4L2_MAX 8
+#define MSM_V4L2_STREAM_ON 1
+#define MSM_V4L2_STREAM_OFF 2
+#define MSM_V4L2_SNAPSHOT 3
+#define MSM_V4L2_QUERY_CTRL 4
+#define MSM_V4L2_GET_CTRL 5
+#define MSM_V4L2_SET_CTRL 6
+#define MSM_V4L2_QUERY 7
+#define MSM_V4L2_GET_CROP 8
+#define MSM_V4L2_SET_CROP 9
+#define MSM_V4L2_OPEN 10
+#define MSM_V4L2_CLOSE 11
+#define MSM_V4L2_SET_CTRL_CMD 12
+#define MSM_V4L2_EVT_SUB_MASK 13
+#define MSM_V4L2_MAX 14
+#define V4L2_CAMERA_EXIT 43
struct crop_info {
void *info;
@@ -380,7 +898,28 @@
#define CFG_GET_PICT_P_PL 25
#define CFG_GET_AF_MAX_STEPS 26
#define CFG_GET_PICT_MAX_EXP_LC 27
-#define CFG_MAX 28
+#define CFG_SEND_WB_INFO 28
+#define CFG_SENSOR_INIT 29
+#define CFG_GET_3D_CALI_DATA 30
+#define CFG_GET_CALIB_DATA 31
+#define CFG_GET_OUTPUT_INFO 32
+#define CFG_GET_EEPROM_INFO 33
+#define CFG_GET_EEPROM_DATA 34
+#define CFG_SET_ACTUATOR_INFO 35
+#define CFG_GET_ACTUATOR_INFO 36
+/* TBD: QRD */
+#define CFG_SET_SATURATION 37
+#define CFG_SET_SHARPNESS 38
+#define CFG_SET_TOUCHAEC 39
+#define CFG_SET_AUTO_FOCUS 40
+#define CFG_SET_AUTOFLASH 41
+#define CFG_SET_EXPOSURE_COMPENSATION 42
+#define CFG_SET_ISO 43
+#define CFG_START_STREAM 44
+#define CFG_STOP_STREAM 45
+#define CFG_GET_CSI_PARAMS 46
+#define CFG_MAX 47
+
#define MOVE_NEAR 0
#define MOVE_FAR 1
@@ -388,25 +927,207 @@
#define SENSOR_PREVIEW_MODE 0
#define SENSOR_SNAPSHOT_MODE 1
#define SENSOR_RAW_SNAPSHOT_MODE 2
+#define SENSOR_HFR_60FPS_MODE 3
+#define SENSOR_HFR_90FPS_MODE 4
+#define SENSOR_HFR_120FPS_MODE 5
#define SENSOR_QTR_SIZE 0
#define SENSOR_FULL_SIZE 1
-#define SENSOR_INVALID_SIZE 2
+#define SENSOR_QVGA_SIZE 2
+#define SENSOR_INVALID_SIZE 3
#define CAMERA_EFFECT_OFF 0
#define CAMERA_EFFECT_MONO 1
#define CAMERA_EFFECT_NEGATIVE 2
#define CAMERA_EFFECT_SOLARIZE 3
-#define CAMERA_EFFECT_PASTEL 4
-#define CAMERA_EFFECT_MOSAIC 5
-#define CAMERA_EFFECT_RESIZE 6
-#define CAMERA_EFFECT_SEPIA 7
-#define CAMERA_EFFECT_POSTERIZE 8
-#define CAMERA_EFFECT_WHITEBOARD 9
-#define CAMERA_EFFECT_BLACKBOARD 10
-#define CAMERA_EFFECT_AQUA 11
+#define CAMERA_EFFECT_SEPIA 4
+#define CAMERA_EFFECT_POSTERIZE 5
+#define CAMERA_EFFECT_WHITEBOARD 6
+#define CAMERA_EFFECT_BLACKBOARD 7
+#define CAMERA_EFFECT_AQUA 8
+#define CAMERA_EFFECT_EMBOSS 9
+#define CAMERA_EFFECT_SKETCH 10
+#define CAMERA_EFFECT_NEON 11
#define CAMERA_EFFECT_MAX 12
+/* QRD */
+#define CAMERA_EFFECT_BW 10
+#define CAMERA_EFFECT_BLUISH 12
+#define CAMERA_EFFECT_REDDISH 13
+#define CAMERA_EFFECT_GREENISH 14
+
+/* QRD */
+#define CAMERA_ANTIBANDING_OFF 0
+#define CAMERA_ANTIBANDING_50HZ 2
+#define CAMERA_ANTIBANDING_60HZ 1
+#define CAMERA_ANTIBANDING_AUTO 3
+
+#define CAMERA_CONTRAST_LV0 0
+#define CAMERA_CONTRAST_LV1 1
+#define CAMERA_CONTRAST_LV2 2
+#define CAMERA_CONTRAST_LV3 3
+#define CAMERA_CONTRAST_LV4 4
+#define CAMERA_CONTRAST_LV5 5
+#define CAMERA_CONTRAST_LV6 6
+#define CAMERA_CONTRAST_LV7 7
+#define CAMERA_CONTRAST_LV8 8
+#define CAMERA_CONTRAST_LV9 9
+
+#define CAMERA_BRIGHTNESS_LV0 0
+#define CAMERA_BRIGHTNESS_LV1 1
+#define CAMERA_BRIGHTNESS_LV2 2
+#define CAMERA_BRIGHTNESS_LV3 3
+#define CAMERA_BRIGHTNESS_LV4 4
+#define CAMERA_BRIGHTNESS_LV5 5
+#define CAMERA_BRIGHTNESS_LV6 6
+#define CAMERA_BRIGHTNESS_LV7 7
+#define CAMERA_BRIGHTNESS_LV8 8
+
+
+#define CAMERA_SATURATION_LV0 0
+#define CAMERA_SATURATION_LV1 1
+#define CAMERA_SATURATION_LV2 2
+#define CAMERA_SATURATION_LV3 3
+#define CAMERA_SATURATION_LV4 4
+#define CAMERA_SATURATION_LV5 5
+#define CAMERA_SATURATION_LV6 6
+#define CAMERA_SATURATION_LV7 7
+#define CAMERA_SATURATION_LV8 8
+
+#define CAMERA_SHARPNESS_LV0 0
+#define CAMERA_SHARPNESS_LV1 3
+#define CAMERA_SHARPNESS_LV2 6
+#define CAMERA_SHARPNESS_LV3 9
+#define CAMERA_SHARPNESS_LV4 12
+#define CAMERA_SHARPNESS_LV5 15
+#define CAMERA_SHARPNESS_LV6 18
+#define CAMERA_SHARPNESS_LV7 21
+#define CAMERA_SHARPNESS_LV8 24
+#define CAMERA_SHARPNESS_LV9 27
+#define CAMERA_SHARPNESS_LV10 30
+
+#define CAMERA_SETAE_AVERAGE 0
+#define CAMERA_SETAE_CENWEIGHT 1
+
+#define CAMERA_WB_AUTO 1 /* This list must match aeecamera.h */
+#define CAMERA_WB_CUSTOM 2
+#define CAMERA_WB_INCANDESCENT 3
+#define CAMERA_WB_FLUORESCENT 4
+#define CAMERA_WB_DAYLIGHT 5
+#define CAMERA_WB_CLOUDY_DAYLIGHT 6
+#define CAMERA_WB_TWILIGHT 7
+#define CAMERA_WB_SHADE 8
+
+#define CAMERA_EXPOSURE_COMPENSATION_LV0 12
+#define CAMERA_EXPOSURE_COMPENSATION_LV1 6
+#define CAMERA_EXPOSURE_COMPENSATION_LV2 0
+#define CAMERA_EXPOSURE_COMPENSATION_LV3 -6
+#define CAMERA_EXPOSURE_COMPENSATION_LV4 -12
+
+enum msm_v4l2_saturation_level {
+ MSM_V4L2_SATURATION_L0,
+ MSM_V4L2_SATURATION_L1,
+ MSM_V4L2_SATURATION_L2,
+ MSM_V4L2_SATURATION_L3,
+ MSM_V4L2_SATURATION_L4,
+ MSM_V4L2_SATURATION_L5,
+ MSM_V4L2_SATURATION_L6,
+ MSM_V4L2_SATURATION_L7,
+ MSM_V4L2_SATURATION_L8,
+ MSM_V4L2_SATURATION_L9,
+ MSM_V4L2_SATURATION_L10,
+};
+
+enum msm_v4l2_contrast_level {
+ MSM_V4L2_CONTRAST_L0,
+ MSM_V4L2_CONTRAST_L1,
+ MSM_V4L2_CONTRAST_L2,
+ MSM_V4L2_CONTRAST_L3,
+ MSM_V4L2_CONTRAST_L4,
+ MSM_V4L2_CONTRAST_L5,
+ MSM_V4L2_CONTRAST_L6,
+ MSM_V4L2_CONTRAST_L7,
+ MSM_V4L2_CONTRAST_L8,
+ MSM_V4L2_CONTRAST_L9,
+ MSM_V4L2_CONTRAST_L10,
+};
+
+
+enum msm_v4l2_exposure_level {
+ MSM_V4L2_EXPOSURE_N2,
+ MSM_V4L2_EXPOSURE_N1,
+ MSM_V4L2_EXPOSURE_D,
+ MSM_V4L2_EXPOSURE_P1,
+ MSM_V4L2_EXPOSURE_P2,
+};
+
+enum msm_v4l2_sharpness_level {
+ MSM_V4L2_SHARPNESS_L0,
+ MSM_V4L2_SHARPNESS_L1,
+ MSM_V4L2_SHARPNESS_L2,
+ MSM_V4L2_SHARPNESS_L3,
+ MSM_V4L2_SHARPNESS_L4,
+ MSM_V4L2_SHARPNESS_L5,
+ MSM_V4L2_SHARPNESS_L6,
+};
+
+enum msm_v4l2_expo_metering_mode {
+ MSM_V4L2_EXP_FRAME_AVERAGE,
+ MSM_V4L2_EXP_CENTER_WEIGHTED,
+ MSM_V4L2_EXP_SPOT_METERING,
+};
+
+enum msm_v4l2_iso_mode {
+ MSM_V4L2_ISO_AUTO = 0,
+ MSM_V4L2_ISO_DEBLUR,
+ MSM_V4L2_ISO_100,
+ MSM_V4L2_ISO_200,
+ MSM_V4L2_ISO_400,
+ MSM_V4L2_ISO_800,
+ MSM_V4L2_ISO_1600,
+};
+
+enum msm_v4l2_wb_mode {
+ MSM_V4L2_WB_OFF,
+ MSM_V4L2_WB_AUTO ,
+ MSM_V4L2_WB_CUSTOM,
+ MSM_V4L2_WB_INCANDESCENT,
+ MSM_V4L2_WB_FLUORESCENT,
+ MSM_V4L2_WB_DAYLIGHT,
+ MSM_V4L2_WB_CLOUDY_DAYLIGHT,
+};
+
+enum msm_v4l2_special_effect {
+ MSM_V4L2_EFFECT_OFF,
+ MSM_V4L2_EFFECT_MONO,
+ MSM_V4L2_EFFECT_NEGATIVE,
+ MSM_V4L2_EFFECT_SOLARIZE,
+ MSM_V4L2_EFFECT_SEPIA,
+ MSM_V4L2_EFFECT_POSTERAIZE,
+ MSM_V4L2_EFFECT_WHITEBOARD,
+ MSM_V4L2_EFFECT_BLACKBOARD,
+ MSM_V4L2_EFFECT_AQUA,
+ MSM_V4L2_EFFECT_EMBOSS,
+ MSM_V4L2_EFFECT_SKETCH,
+ MSM_V4L2_EFFECT_NEON,
+ MSM_V4L2_EFFECT_MAX,
+};
+
+enum msm_v4l2_power_line_frequency {
+ MSM_V4L2_POWER_LINE_OFF,
+ MSM_V4L2_POWER_LINE_60HZ,
+ MSM_V4L2_POWER_LINE_50HZ,
+ MSM_V4L2_POWER_LINE_AUTO,
+};
+
+#define CAMERA_ISO_TYPE_AUTO 0
+#define CAMEAR_ISO_TYPE_HJR 1
+#define CAMEAR_ISO_TYPE_100 2
+#define CAMERA_ISO_TYPE_200 3
+#define CAMERA_ISO_TYPE_400 4
+#define CAMEAR_ISO_TYPE_800 5
+#define CAMERA_ISO_TYPE_1600 6
+
struct sensor_pict_fps {
uint16_t prevfps;
uint16_t pictfps;
@@ -427,6 +1148,229 @@
uint16_t fps_div;
uint32_t pict_fps_div;
};
+struct wb_info_cfg {
+ uint16_t red_gain;
+ uint16_t green_gain;
+ uint16_t blue_gain;
+};
+struct sensor_3d_exp_cfg {
+ uint16_t gain;
+ uint32_t line;
+ uint16_t r_gain;
+ uint16_t b_gain;
+ uint16_t gr_gain;
+ uint16_t gb_gain;
+ uint16_t gain_adjust;
+};
+struct sensor_3d_cali_data_t{
+ unsigned char left_p_matrix[3][4][8];
+ unsigned char right_p_matrix[3][4][8];
+ unsigned char square_len[8];
+ unsigned char focal_len[8];
+ unsigned char pixel_pitch[8];
+ uint16_t left_r;
+ uint16_t left_b;
+ uint16_t left_gb;
+ uint16_t left_af_far;
+ uint16_t left_af_mid;
+ uint16_t left_af_short;
+ uint16_t left_af_5um;
+ uint16_t left_af_50up;
+ uint16_t left_af_50down;
+ uint16_t right_r;
+ uint16_t right_b;
+ uint16_t right_gb;
+ uint16_t right_af_far;
+ uint16_t right_af_mid;
+ uint16_t right_af_short;
+ uint16_t right_af_5um;
+ uint16_t right_af_50up;
+ uint16_t right_af_50down;
+};
+struct sensor_init_cfg {
+ uint8_t prev_res;
+ uint8_t pict_res;
+};
+
+#define ROLLOFF_CALDATA_SIZE (17 * 13)
+typedef struct
+{
+ unsigned short mesh_rolloff_table_size; // TableSize
+ uint8_t r_gain[ROLLOFF_CALDATA_SIZE]; // RGain
+ uint8_t gr_gain[ROLLOFF_CALDATA_SIZE]; // GRGain
+ uint8_t gb_gain[ROLLOFF_CALDATA_SIZE]; // GBGain
+ uint8_t b_gain[ROLLOFF_CALDATA_SIZE]; // BGain
+ uint8_t red_ref[17];
+} rolloff_caldata_array_type;
+
+struct sensor_calib_data {
+ /* Color Related Measurements */
+ uint16_t r_over_g;
+ uint16_t b_over_g;
+ uint16_t gr_over_gb;
+
+ /* Lens Related Measurements */
+ uint16_t macro_2_inf;
+ uint16_t inf_2_macro;
+ uint16_t stroke_amt;
+ uint16_t af_pos_1m;
+ uint16_t af_pos_inf;
+ /* Lens Shading Calibration Data */
+ rolloff_caldata_array_type rolloff;
+};
+
+enum msm_sensor_resolution_t {
+ MSM_SENSOR_RES_FULL,
+ MSM_SENSOR_RES_QTR,
+ MSM_SENSOR_RES_2,
+ MSM_SENSOR_RES_3,
+ MSM_SENSOR_RES_4,
+ MSM_SENSOR_RES_5,
+ MSM_SENSOR_RES_6,
+ MSM_SENSOR_RES_7,
+ MSM_SENSOR_INVALID_RES,
+};
+
+struct msm_sensor_output_info_t {
+ uint16_t x_output;
+ uint16_t y_output;
+ uint16_t line_length_pclk;
+ uint16_t frame_length_lines;
+ uint32_t vt_pixel_clk;
+ uint32_t op_pixel_clk;
+ uint16_t binning_factor;
+};
+
+struct sensor_output_info_t {
+ struct msm_sensor_output_info_t *output_info;
+ uint16_t num_info;
+};
+
+struct mirror_flip {
+ int32_t x_mirror;
+ int32_t y_flip;
+};
+
+struct cord {
+ uint32_t x;
+ uint32_t y;
+};
+
+struct msm_eeprom_data_t {
+ void *eeprom_data;
+ uint16_t index;
+};
+
+struct msm_camera_csid_vc_cfg {
+ uint8_t cid;
+ uint8_t dt;
+ uint8_t decode_format;
+};
+
+struct csi_lane_params_t {
+ uint8_t csi_lane_assign;
+ uint8_t csi_lane_mask;
+ uint8_t csi_if;
+ uint8_t csid_core;
+ uint32_t csid_version;
+};
+
+#define CSI_EMBED_DATA 0x12
+#define CSI_RESERVED_DATA_0 0x13
+#define CSI_YUV422_8 0x1E
+#define CSI_RAW8 0x2A
+#define CSI_RAW10 0x2B
+#define CSI_RAW12 0x2C
+
+#define CSI_DECODE_6BIT 0
+#define CSI_DECODE_8BIT 1
+#define CSI_DECODE_10BIT 2
+#define CSI_DECODE_DPCM_10_8_10 5
+
+#define ISPIF_STREAM(intf, action, vfe) (((intf)<<ISPIF_S_STREAM_SHIFT)+\
+ (action)+((vfe)<<ISPIF_VFE_INTF_SHIFT))
+#define ISPIF_ON_FRAME_BOUNDARY (0x01 << 0)
+#define ISPIF_OFF_FRAME_BOUNDARY (0x01 << 1)
+#define ISPIF_OFF_IMMEDIATELY (0x01 << 2)
+#define ISPIF_S_STREAM_SHIFT 4
+#define ISPIF_VFE_INTF_SHIFT 12
+
+#define PIX_0 (0x01 << 0)
+#define RDI_0 (0x01 << 1)
+#define PIX_1 (0x01 << 2)
+#define RDI_1 (0x01 << 3)
+#define RDI_2 (0x01 << 4)
+
+enum msm_ispif_vfe_intf {
+ VFE0,
+ VFE1,
+ VFE_MAX,
+};
+
+enum msm_ispif_intftype {
+ PIX0,
+ RDI0,
+ PIX1,
+ RDI1,
+ RDI2,
+ INTF_MAX,
+};
+
+enum msm_ispif_vc {
+ VC0,
+ VC1,
+ VC2,
+ VC3,
+};
+
+enum msm_ispif_cid {
+ CID0,
+ CID1,
+ CID2,
+ CID3,
+ CID4,
+ CID5,
+ CID6,
+ CID7,
+ CID8,
+ CID9,
+ CID10,
+ CID11,
+ CID12,
+ CID13,
+ CID14,
+ CID15,
+};
+
+struct msm_ispif_params {
+ uint8_t intftype;
+ uint16_t cid_mask;
+ uint8_t csid;
+ uint8_t vfe_intf;
+};
+
+struct msm_ispif_params_list {
+ uint32_t len;
+ struct msm_ispif_params params[4];
+};
+
+enum ispif_cfg_type_t {
+ ISPIF_INIT,
+ ISPIF_SET_CFG,
+ ISPIF_SET_ON_FRAME_BOUNDARY,
+ ISPIF_SET_OFF_FRAME_BOUNDARY,
+ ISPIF_SET_OFF_IMMEDIATELY,
+ ISPIF_RELEASE,
+};
+
+struct ispif_cfg_data {
+ enum ispif_cfg_type_t cfgtype;
+ union {
+ uint32_t csid_version;
+ int cmd;
+ struct msm_ispif_params_list ispif_params;
+ } cfg;
+};
struct sensor_cfg_data {
int cfgtype;
@@ -443,13 +1387,262 @@
uint16_t pictp_pl;
uint32_t pict_max_exp_lc;
uint16_t p_fps;
+ uint8_t iso_type;
+ struct sensor_init_cfg init_info;
struct sensor_pict_fps gfps;
struct exp_gain_cfg exp_gain;
struct focus_cfg focus;
struct fps_cfg fps;
+ struct wb_info_cfg wb_info;
+ struct sensor_3d_exp_cfg sensor_3d_exp;
+ struct sensor_calib_data calib_info;
+ struct sensor_output_info_t output_info;
+ struct msm_eeprom_data_t eeprom_data;
+ struct csi_lane_params_t csi_lane_params;
+ /* QRD */
+ uint16_t antibanding;
+ uint8_t contrast;
+ uint8_t saturation;
+ uint8_t sharpness;
+ int8_t brightness;
+ int ae_mode;
+ uint8_t wb_val;
+ int8_t exp_compensation;
+ struct cord aec_cord;
+ int is_autoflash;
+ struct mirror_flip mirror_flip;
} cfg;
};
+struct damping_params_t {
+ uint32_t damping_step;
+ uint32_t damping_delay;
+ uint32_t hw_params;
+};
+
+enum actuator_type {
+ ACTUATOR_VCM,
+ ACTUATOR_PIEZO,
+};
+
+enum msm_actuator_data_type {
+ MSM_ACTUATOR_BYTE_DATA = 1,
+ MSM_ACTUATOR_WORD_DATA,
+};
+
+enum msm_actuator_addr_type {
+ MSM_ACTUATOR_BYTE_ADDR = 1,
+ MSM_ACTUATOR_WORD_ADDR,
+};
+
+enum msm_actuator_write_type {
+ MSM_ACTUATOR_WRITE_HW_DAMP,
+ MSM_ACTUATOR_WRITE_DAC,
+};
+
+struct msm_actuator_reg_params_t {
+ enum msm_actuator_write_type reg_write_type;
+ uint32_t hw_mask;
+ uint16_t reg_addr;
+ uint16_t hw_shift;
+ uint16_t data_shift;
+};
+
+struct reg_settings_t {
+ uint16_t reg_addr;
+ uint16_t reg_data;
+};
+
+struct region_params_t {
+ /* [0] = ForwardDirection Macro boundary
+ [1] = ReverseDirection Inf boundary
+ */
+ uint16_t step_bound[2];
+ uint16_t code_per_step;
+};
+
+struct msm_actuator_move_params_t {
+ int8_t dir;
+ int8_t sign_dir;
+ int16_t dest_step_pos;
+ int32_t num_steps;
+ struct damping_params_t *ringing_params;
+};
+
+struct msm_actuator_tuning_params_t {
+ int16_t initial_code;
+ uint16_t pwd_step;
+ uint16_t region_size;
+ uint32_t total_steps;
+ struct region_params_t *region_params;
+};
+
+struct msm_actuator_params_t {
+ enum actuator_type act_type;
+ uint8_t reg_tbl_size;
+ uint16_t data_size;
+ uint16_t init_setting_size;
+ uint32_t i2c_addr;
+ enum msm_actuator_addr_type i2c_addr_type;
+ enum msm_actuator_data_type i2c_data_type;
+ struct msm_actuator_reg_params_t *reg_tbl_params;
+ struct reg_settings_t *init_settings;
+};
+
+struct msm_actuator_set_info_t {
+ struct msm_actuator_params_t actuator_params;
+ struct msm_actuator_tuning_params_t af_tuning_params;
+};
+
+struct msm_actuator_get_info_t {
+ uint32_t focal_length_num;
+ uint32_t focal_length_den;
+ uint32_t f_number_num;
+ uint32_t f_number_den;
+ uint32_t f_pix_num;
+ uint32_t f_pix_den;
+ uint32_t total_f_dist_num;
+ uint32_t total_f_dist_den;
+ uint32_t hor_view_angle_num;
+ uint32_t hor_view_angle_den;
+ uint32_t ver_view_angle_num;
+ uint32_t ver_view_angle_den;
+};
+
+enum af_camera_name {
+ ACTUATOR_MAIN_CAM_0,
+ ACTUATOR_MAIN_CAM_1,
+ ACTUATOR_MAIN_CAM_2,
+ ACTUATOR_MAIN_CAM_3,
+ ACTUATOR_MAIN_CAM_4,
+ ACTUATOR_MAIN_CAM_5,
+ ACTUATOR_WEB_CAM_0,
+ ACTUATOR_WEB_CAM_1,
+ ACTUATOR_WEB_CAM_2,
+};
+
+struct msm_actuator_cfg_data {
+ int cfgtype;
+ uint8_t is_af_supported;
+ union {
+ struct msm_actuator_move_params_t move;
+ struct msm_actuator_set_info_t set_info;
+ struct msm_actuator_get_info_t get_info;
+ enum af_camera_name cam_name;
+ } cfg;
+};
+
+struct msm_eeprom_support {
+ uint16_t is_supported;
+ uint16_t size;
+ uint16_t index;
+ uint16_t qvalue;
+};
+
+struct msm_calib_wb {
+ uint16_t r_over_g;
+ uint16_t b_over_g;
+ uint16_t gr_over_gb;
+};
+
+struct msm_calib_af {
+ uint16_t macro_dac;
+ uint16_t inf_dac;
+ uint16_t start_dac;
+};
+
+struct msm_calib_lsc {
+ uint16_t r_gain[221];
+ uint16_t b_gain[221];
+ uint16_t gr_gain[221];
+ uint16_t gb_gain[221];
+};
+
+struct pixel_t {
+ int x;
+ int y;
+};
+
+struct msm_calib_dpc {
+ uint16_t validcount;
+ struct pixel_t snapshot_coord[128];
+ struct pixel_t preview_coord[128];
+ struct pixel_t video_coord[128];
+};
+
+struct msm_camera_eeprom_info_t {
+ struct msm_eeprom_support af;
+ struct msm_eeprom_support wb;
+ struct msm_eeprom_support lsc;
+ struct msm_eeprom_support dpc;
+};
+
+struct msm_eeprom_cfg_data {
+ int cfgtype;
+ uint8_t is_eeprom_supported;
+ union {
+ struct msm_eeprom_data_t get_data;
+ struct msm_camera_eeprom_info_t get_info;
+ } cfg;
+};
+
+struct sensor_large_data {
+ int cfgtype;
+ union {
+ struct sensor_3d_cali_data_t sensor_3d_cali_data;
+ } data;
+};
+
+enum sensor_type_t {
+ BAYER,
+ YUV,
+ JPEG_SOC,
+};
+
+enum flash_type {
+ LED_FLASH,
+ STROBE_FLASH,
+};
+
+enum strobe_flash_ctrl_type {
+ STROBE_FLASH_CTRL_INIT,
+ STROBE_FLASH_CTRL_CHARGE,
+ STROBE_FLASH_CTRL_RELEASE
+};
+
+struct strobe_flash_ctrl_data {
+ enum strobe_flash_ctrl_type type;
+ int charge_en;
+};
+
+struct msm_camera_info {
+ int num_cameras;
+ uint8_t has_3d_support[MSM_MAX_CAMERA_SENSORS];
+ uint8_t is_internal_cam[MSM_MAX_CAMERA_SENSORS];
+ uint32_t s_mount_angle[MSM_MAX_CAMERA_SENSORS];
+ const char *video_dev_name[MSM_MAX_CAMERA_SENSORS];
+ enum sensor_type_t sensor_type[MSM_MAX_CAMERA_SENSORS];
+};
+
+struct msm_cam_config_dev_info {
+ int num_config_nodes;
+ const char *config_dev_name[MSM_MAX_CAMERA_CONFIGS];
+ int config_dev_id[MSM_MAX_CAMERA_CONFIGS];
+};
+
+struct msm_mctl_node_info {
+ int num_mctl_nodes;
+ const char *mctl_node_name[MSM_MAX_CAMERA_SENSORS];
+};
+
+struct flash_ctrl_data {
+ int flashtype;
+ union {
+ int led_state;
+ struct strobe_flash_ctrl_data strobe_ctrl;
+ } ctrl_data;
+};
+
#define GET_NAME 0
#define GET_PREVIEW_LINE_PER_FRAME 1
#define GET_PREVIEW_PIXELS_PER_LINE 2
@@ -461,5 +1654,326 @@
struct msm_camsensor_info {
char name[MAX_SENSOR_NAME];
uint8_t flash_enabled;
+ uint8_t strobe_flash_enabled;
+ uint8_t actuator_enabled;
+ uint8_t ispif_supported;
+ int8_t total_steps;
+ uint8_t support_3d;
+ enum flash_type flashtype;
+ enum sensor_type_t sensor_type;
+ uint32_t pxlcode; /* enum v4l2_mbus_pixelcode */
+ uint32_t camera_type; /* msm_camera_type */
+ int mount_angle;
+ uint32_t max_width;
+ uint32_t max_height;
};
+
+#define V4L2_SINGLE_PLANE 0
+#define V4L2_MULTI_PLANE_Y 0
+#define V4L2_MULTI_PLANE_CBCR 1
+#define V4L2_MULTI_PLANE_CB 1
+#define V4L2_MULTI_PLANE_CR 2
+
+struct plane_data {
+ int plane_id;
+ uint32_t offset;
+ unsigned long size;
+};
+
+struct img_plane_info {
+ uint32_t width;
+ uint32_t height;
+ uint32_t pixelformat;
+ uint8_t buffer_type; /*Single/Multi planar*/
+ uint8_t output_port;
+ uint32_t ext_mode;
+ uint8_t num_planes;
+ struct plane_data plane[MAX_PLANES];
+ uint32_t sp_y_offset;
+ uint32_t inst_handle;
+};
+
+#define QCAMERA_NAME "qcamera"
+#define QCAMERA_SERVER_NAME "qcamera_server"
+#define QCAMERA_DEVICE_GROUP_ID 1
+#define QCAMERA_VNODE_GROUP_ID 2
+
+enum msm_cam_subdev_type {
+ CSIPHY_DEV,
+ CSID_DEV,
+ CSIC_DEV,
+ ISPIF_DEV,
+ VFE_DEV,
+ AXI_DEV,
+ VPE_DEV,
+ SENSOR_DEV,
+ ACTUATOR_DEV,
+ EEPROM_DEV,
+ GESTURE_DEV,
+ IRQ_ROUTER_DEV,
+ CPP_DEV,
+ CCI_DEV,
+};
+
+struct msm_mctl_set_sdev_data {
+ uint32_t revision;
+ enum msm_cam_subdev_type sdev_type;
+};
+
+#define MSM_CAM_V4L2_IOCTL_GET_CAMERA_INFO \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct msm_camera_v4l2_ioctl_t)
+
+#define MSM_CAM_V4L2_IOCTL_GET_CONFIG_INFO \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct msm_camera_v4l2_ioctl_t)
+
+#define MSM_CAM_V4L2_IOCTL_GET_MCTL_INFO \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 3, struct msm_camera_v4l2_ioctl_t)
+
+#define MSM_CAM_V4L2_IOCTL_CTRL_CMD_DONE \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct msm_camera_v4l2_ioctl_t)
+
+#define MSM_CAM_V4L2_IOCTL_GET_EVENT_PAYLOAD \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct msm_camera_v4l2_ioctl_t)
+
+#define MSM_CAM_IOCTL_SEND_EVENT \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct v4l2_event)
+
+#define MSM_CAM_V4L2_IOCTL_CFG_VPE \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 7, struct msm_vpe_cfg_cmd)
+
+#define MSM_CAM_V4L2_IOCTL_PRIVATE_S_CTRL \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_camera_v4l2_ioctl_t)
+
+#define MSM_CAM_V4L2_IOCTL_PRIVATE_G_CTRL \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 9, struct msm_camera_v4l2_ioctl_t)
+
+#define VIDIOC_MSM_VPE_INIT \
+ _IO('V', BASE_VIDIOC_PRIVATE + 15)
+
+#define VIDIOC_MSM_VPE_RELEASE \
+ _IO('V', BASE_VIDIOC_PRIVATE + 16)
+
+#define VIDIOC_MSM_VPE_CFG \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 17, struct msm_mctl_pp_params *)
+
+#define VIDIOC_MSM_AXI_INIT \
+ _IO('V', BASE_VIDIOC_PRIVATE + 18)
+
+#define VIDIOC_MSM_AXI_RELEASE \
+ _IO('V', BASE_VIDIOC_PRIVATE + 19)
+
+#define VIDIOC_MSM_AXI_CFG \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 20, void *)
+
+#define VIDIOC_MSM_AXI_IRQ \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 21, void *)
+
+#define VIDIOC_MSM_AXI_BUF_CFG \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 22, void *)
+
+#define VIDIOC_MSM_VFE_INIT \
+ _IO('V', BASE_VIDIOC_PRIVATE + 22)
+
+#define VIDIOC_MSM_VFE_RELEASE \
+ _IO('V', BASE_VIDIOC_PRIVATE + 23)
+
+struct msm_camera_v4l2_ioctl_t {
+ uint32_t id;
+ void __user *ioctl_ptr;
+ uint32_t len;
+};
+
+struct msm_camera_vfe_params_t {
+ uint32_t operation_mode;
+ uint32_t capture_count;
+ uint32_t skip_abort;
+ uint16_t port_info;
+ uint32_t inst_handle;
+ uint16_t cmd_type;
+};
+
+enum msm_camss_irq_idx {
+ CAMERA_SS_IRQ_0,
+ CAMERA_SS_IRQ_1,
+ CAMERA_SS_IRQ_2,
+ CAMERA_SS_IRQ_3,
+ CAMERA_SS_IRQ_4,
+ CAMERA_SS_IRQ_5,
+ CAMERA_SS_IRQ_6,
+ CAMERA_SS_IRQ_7,
+ CAMERA_SS_IRQ_8,
+ CAMERA_SS_IRQ_9,
+ CAMERA_SS_IRQ_10,
+ CAMERA_SS_IRQ_11,
+ CAMERA_SS_IRQ_12,
+ CAMERA_SS_IRQ_MAX
+};
+
+enum msm_cam_hw_idx {
+ MSM_CAM_HW_MICRO,
+ MSM_CAM_HW_CCI,
+ MSM_CAM_HW_CSI0,
+ MSM_CAM_HW_CSI1,
+ MSM_CAM_HW_CSI2,
+ MSM_CAM_HW_CSI3,
+ MSM_CAM_HW_ISPIF,
+ MSM_CAM_HW_CPP,
+ MSM_CAM_HW_VFE0,
+ MSM_CAM_HW_VFE1,
+ MSM_CAM_HW_JPEG0,
+ MSM_CAM_HW_JPEG1,
+ MSM_CAM_HW_JPEG2,
+ MSM_CAM_HW_MAX
+};
+
+struct msm_camera_irq_cfg {
+ /* Bit mask of all the camera hardwares that needs to
+ * be composited into a single IRQ to the MSM.
+ * Current usage: (may be updated based on hw changes)
+ * Bits 31:13 - Reserved.
+ * Bits 12:0
+ * 12 - MSM_CAM_HW_JPEG2
+ * 11 - MSM_CAM_HW_JPEG1
+ * 10 - MSM_CAM_HW_JPEG0
+ * 9 - MSM_CAM_HW_VFE1
+ * 8 - MSM_CAM_HW_VFE0
+ * 7 - MSM_CAM_HW_CPP
+ * 6 - MSM_CAM_HW_ISPIF
+ * 5 - MSM_CAM_HW_CSI3
+ * 4 - MSM_CAM_HW_CSI2
+ * 3 - MSM_CAM_HW_CSI1
+ * 2 - MSM_CAM_HW_CSI0
+ * 1 - MSM_CAM_HW_CCI
+ * 0 - MSM_CAM_HW_MICRO
+ */
+ uint32_t cam_hw_mask;
+ uint8_t irq_idx;
+ uint8_t num_hwcore;
+};
+
+#define MSM_IRQROUTER_CFG_COMPIRQ \
+ _IOWR('V', BASE_VIDIOC_PRIVATE, void __user *)
+
+#define MAX_NUM_CPP_STRIPS 8
+
+enum msm_cpp_frame_type {
+ MSM_CPP_OFFLINE_FRAME,
+ MSM_CPP_REALTIME_FRAME,
+};
+
+struct msm_cpp_frame_strip_info {
+ int scale_v_en;
+ int scale_h_en;
+
+ int upscale_v_en;
+ int upscale_h_en;
+
+ int src_start_x;
+ int src_end_x;
+ int src_start_y;
+ int src_end_y;
+
+ /* Padding is required for upscaler because it does not
+ * pad internally like other blocks, also needed for rotation
+ * rotation expects all the blocks in the stripe to be the same size
+ * Padding is done such that all the extra padded pixels
+ * are on the right and bottom
+ */
+ int pad_bottom;
+ int pad_top;
+ int pad_right;
+ int pad_left;
+
+ int v_init_phase;
+ int h_init_phase;
+ int h_phase_step;
+ int v_phase_step;
+
+ int prescale_crop_width_first_pixel;
+ int prescale_crop_width_last_pixel;
+ int prescale_crop_height_first_line;
+ int prescale_crop_height_last_line;
+
+ int postscale_crop_height_first_line;
+ int postscale_crop_height_last_line;
+ int postscale_crop_width_first_pixel;
+ int postscale_crop_width_last_pixel;
+
+ int dst_start_x;
+ int dst_end_x;
+ int dst_start_y;
+ int dst_end_y;
+
+ int bytes_per_pixel;
+ unsigned int source_address;
+ unsigned int destination_address;
+ unsigned int src_stride;
+ unsigned int dst_stride;
+ int rotate_270;
+ int horizontal_flip;
+ int vertical_flip;
+ int scale_output_width;
+ int scale_output_height;
+};
+
+struct msm_cpp_frame_info_t {
+ int32_t frame_id;
+ uint32_t inst_id;
+ uint32_t client_id;
+ enum msm_cpp_frame_type frame_type;
+ uint32_t num_strips;
+ struct msm_cpp_frame_strip_info *strip_info;
+};
+
+struct msm_ver_num_info {
+ uint32_t main;
+ uint32_t minor;
+ uint32_t rev;
+};
+
+#define VIDIOC_MSM_CPP_CFG \
+ _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_camera_v4l2_ioctl_t)
+
+#define VIDIOC_MSM_CPP_GET_EVENTPAYLOAD \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct msm_camera_v4l2_ioctl_t)
+
+#define VIDIOC_MSM_CPP_GET_INST_INFO \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct msm_camera_v4l2_ioctl_t)
+
+#define V4L2_EVENT_CPP_FRAME_DONE (V4L2_EVENT_PRIVATE_START + 0)
+
+/* Instance Handle - inst_handle
+ * Data bundle containing the information about where
+ * to get a buffer for a particular camera instance.
+ * This is a bitmask containing the following data:
+ * Buffer Handle Bitmask:
+ * ------------------------------------
+ * Bits : Purpose
+ * ------------------------------------
+ * 31 - 24 : Reserved.
+ * 23 : is Image mode valid?
+ * 22 - 16 : Image mode.
+ * 15 : is MCTL PP inst idx valid?
+ * 14 - 8 : MCTL PP inst idx.
+ * 7 : is Video inst idx valid?
+ * 6 - 0 : Video inst idx.
+ */
+#define CLR_IMG_MODE(handle) (handle &= 0xFF00FFFF)
+#define SET_IMG_MODE(handle, data) \
+ (handle |= ((0x1 << 23) | ((data & 0x7F) << 16)))
+#define GET_IMG_MODE(handle) \
+ ((handle & 0x800000) ? ((handle & 0x7F0000) >> 16) : 0xFF)
+
+#define CLR_MCTLPP_INST_IDX(handle) (handle &= 0xFFFF00FF)
+#define SET_MCTLPP_INST_IDX(handle, data) \
+ (handle |= ((0x1 << 15) | ((data & 0x7F) << 8)))
+#define GET_MCTLPP_INST_IDX(handle) \
+ ((handle & 0x8000) ? ((handle & 0x7F00) >> 8) : 0xFF)
+
+#define CLR_VIDEO_INST_IDX(handle) (handle &= 0xFFFFFF00)
+#define GET_VIDEO_INST_IDX(handle) \
+ ((handle & 0x80) ? (handle & 0x7F) : 0xFF)
+#define SET_VIDEO_INST_IDX(handle, data) \
+ (handle |= (0x1 << 7) | (data & 0x7F))
+
#endif /* __LINUX_MSM_CAMERA_H */
diff --git a/original/media/msm_gemini.h b/original/media/msm_gemini.h
new file mode 100644
index 0000000..0167335
--- /dev/null
+++ b/original/media/msm_gemini.h
@@ -0,0 +1,114 @@
+#ifndef __LINUX_MSM_GEMINI_H
+#define __LINUX_MSM_GEMINI_H
+
+#include <linux/types.h>
+#include <linux/ioctl.h>
+
+#define MSM_GMN_IOCTL_MAGIC 'g'
+
+#define MSM_GMN_IOCTL_GET_HW_VERSION \
+ _IOW(MSM_GMN_IOCTL_MAGIC, 1, struct msm_gemini_hw_cmd *)
+
+#define MSM_GMN_IOCTL_RESET \
+ _IOW(MSM_GMN_IOCTL_MAGIC, 2, struct msm_gemini_ctrl_cmd *)
+
+#define MSM_GMN_IOCTL_STOP \
+ _IOW(MSM_GMN_IOCTL_MAGIC, 3, struct msm_gemini_hw_cmds *)
+
+#define MSM_GMN_IOCTL_START \
+ _IOW(MSM_GMN_IOCTL_MAGIC, 4, struct msm_gemini_hw_cmds *)
+
+#define MSM_GMN_IOCTL_INPUT_BUF_ENQUEUE \
+ _IOW(MSM_GMN_IOCTL_MAGIC, 5, struct msm_gemini_buf *)
+
+#define MSM_GMN_IOCTL_INPUT_GET \
+ _IOW(MSM_GMN_IOCTL_MAGIC, 6, struct msm_gemini_buf *)
+
+#define MSM_GMN_IOCTL_INPUT_GET_UNBLOCK \
+ _IOW(MSM_GMN_IOCTL_MAGIC, 7, int)
+
+#define MSM_GMN_IOCTL_OUTPUT_BUF_ENQUEUE \
+ _IOW(MSM_GMN_IOCTL_MAGIC, 8, struct msm_gemini_buf *)
+
+#define MSM_GMN_IOCTL_OUTPUT_GET \
+ _IOW(MSM_GMN_IOCTL_MAGIC, 9, struct msm_gemini_buf *)
+
+#define MSM_GMN_IOCTL_OUTPUT_GET_UNBLOCK \
+ _IOW(MSM_GMN_IOCTL_MAGIC, 10, int)
+
+#define MSM_GMN_IOCTL_EVT_GET \
+ _IOW(MSM_GMN_IOCTL_MAGIC, 11, struct msm_gemini_ctrl_cmd *)
+
+#define MSM_GMN_IOCTL_EVT_GET_UNBLOCK \
+ _IOW(MSM_GMN_IOCTL_MAGIC, 12, int)
+
+#define MSM_GMN_IOCTL_HW_CMD \
+ _IOW(MSM_GMN_IOCTL_MAGIC, 13, struct msm_gemini_hw_cmd *)
+
+#define MSM_GMN_IOCTL_HW_CMDS \
+ _IOW(MSM_GMN_IOCTL_MAGIC, 14, struct msm_gemini_hw_cmds *)
+
+#define MSM_GMN_IOCTL_TEST_DUMP_REGION \
+ _IOW(MSM_GMN_IOCTL_MAGIC, 15, unsigned long)
+
+#define MSM_GEMINI_MODE_REALTIME_ENCODE 0
+#define MSM_GEMINI_MODE_OFFLINE_ENCODE 1
+#define MSM_GEMINI_MODE_REALTIME_ROTATION 2
+#define MSM_GEMINI_MODE_OFFLINE_ROTATION 3
+struct msm_gemini_ctrl_cmd {
+ uint32_t type;
+ uint32_t len;
+ void *value;
+};
+
+#define MSM_GEMINI_EVT_RESET 0
+#define MSM_GEMINI_EVT_FRAMEDONE 1
+#define MSM_GEMINI_EVT_ERR 2
+
+struct msm_gemini_buf {
+ uint32_t type;
+ int fd;
+
+ void *vaddr;
+
+ uint32_t y_off;
+ uint32_t y_len;
+ uint32_t framedone_len;
+
+ uint32_t cbcr_off;
+ uint32_t cbcr_len;
+
+ uint32_t num_of_mcu_rows;
+ uint32_t offset;
+};
+
+#define MSM_GEMINI_HW_CMD_TYPE_READ 0
+#define MSM_GEMINI_HW_CMD_TYPE_WRITE 1
+#define MSM_GEMINI_HW_CMD_TYPE_WRITE_OR 2
+#define MSM_GEMINI_HW_CMD_TYPE_UWAIT 3
+#define MSM_GEMINI_HW_CMD_TYPE_MWAIT 4
+#define MSM_GEMINI_HW_CMD_TYPE_MDELAY 5
+#define MSM_GEMINI_HW_CMD_TYPE_UDELAY 6
+struct msm_gemini_hw_cmd {
+
+ uint32_t type:4;
+
+ /* n microseconds of timeout for WAIT */
+ /* n microseconds of time for DELAY */
+ /* repeat n times for READ/WRITE */
+ /* max is 0xFFF, 4095 */
+ uint32_t n:12;
+ uint32_t offset:16;
+ uint32_t mask;
+ union {
+ uint32_t data; /* for single READ/WRITE/WAIT, n = 1 */
+ uint32_t *pdata; /* for multiple READ/WRITE/WAIT, n > 1 */
+ };
+};
+
+struct msm_gemini_hw_cmds {
+ uint32_t m; /* number of elements in the hw_cmd array */
+ struct msm_gemini_hw_cmd hw_cmd[1];
+};
+
+#endif /* __LINUX_MSM_GEMINI_H */
diff --git a/original/media/msm_gestures.h b/original/media/msm_gestures.h
new file mode 100644
index 0000000..c9af034
--- /dev/null
+++ b/original/media/msm_gestures.h
@@ -0,0 +1,66 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __LINUX_MSM_GESTURES_H
+#define __LINUX_MSM_GESTURES_H
+
+#include <linux/types.h>
+#include <linux/ioctl.h>
+#include <media/msm_camera.h>
+
+#define MSM_GES_IOCTL_CTRL_COMMAND \
+ _IOW('V', BASE_VIDIOC_PRIVATE + 20, struct v4l2_control)
+
+#define VIDIOC_MSM_GESTURE_EVT \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 21, struct v4l2_event)
+
+#define MSM_GES_GET_EVT_PAYLOAD \
+ _IOW('V', BASE_VIDIOC_PRIVATE + 22, struct msm_ges_evt)
+
+#define VIDIOC_MSM_GESTURE_CAM_EVT \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 23, int)
+
+#define MSM_GES_RESP_V4L2 MSM_CAM_RESP_MAX
+#define MSM_GES_RESP_MAX (MSM_GES_RESP_V4L2 + 1)
+
+#define MSM_SVR_RESP_MAX MSM_GES_RESP_MAX
+
+
+#define MSM_V4L2_GES_BASE 100
+#define MSM_V4L2_GES_OPEN (MSM_V4L2_GES_BASE + 0)
+#define MSM_V4L2_GES_CLOSE (MSM_V4L2_GES_BASE + 1)
+#define MSM_V4L2_GES_CAM_OPEN (MSM_V4L2_GES_BASE + 2)
+#define MSM_V4L2_GES_CAM_CLOSE (MSM_V4L2_GES_BASE + 3)
+
+#define MSM_GES_APP_EVT_MIN (V4L2_EVENT_PRIVATE_START + 0x14)
+#define MSM_GES_APP_NOTIFY_EVENT (MSM_GES_APP_EVT_MIN + 0)
+#define MSM_GES_APP_NOTIFY_ERROR_EVENT (MSM_GES_APP_EVT_MIN + 1)
+#define MSM_GES_APP_EVT_MAX (MSM_GES_APP_EVT_MIN + 2)
+
+#define MSM_GESTURE_CID_CTRL_CMD V4L2_CID_BRIGHTNESS
+
+#define MAX_GES_EVENTS 25
+
+struct msm_ges_ctrl_cmd {
+ int type;
+ void *value;
+ int len;
+ int fd;
+ uint32_t cookie;
+};
+
+struct msm_ges_evt {
+ void *evt_data;
+ int evt_len;
+};
+
+#endif /*__LINUX_MSM_GESTURES_H*/
diff --git a/original/media/msm_isp.h b/original/media/msm_isp.h
new file mode 100644
index 0000000..9fa5932
--- /dev/null
+++ b/original/media/msm_isp.h
@@ -0,0 +1,371 @@
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __MSM_ISP_H__
+#define __MSM_ISP_H__
+
+#define BIT(nr) (1UL << (nr))
+
+/* ISP message IDs */
+#define MSG_ID_RESET_ACK 0
+#define MSG_ID_START_ACK 1
+#define MSG_ID_STOP_ACK 2
+#define MSG_ID_UPDATE_ACK 3
+#define MSG_ID_OUTPUT_P 4
+#define MSG_ID_OUTPUT_T 5
+#define MSG_ID_OUTPUT_S 6
+#define MSG_ID_OUTPUT_V 7
+#define MSG_ID_SNAPSHOT_DONE 8
+#define MSG_ID_STATS_AEC 9
+#define MSG_ID_STATS_AF 10
+#define MSG_ID_STATS_AWB 11
+#define MSG_ID_STATS_RS 12
+#define MSG_ID_STATS_CS 13
+#define MSG_ID_STATS_IHIST 14
+#define MSG_ID_STATS_SKIN 15
+#define MSG_ID_EPOCH1 16
+#define MSG_ID_EPOCH2 17
+#define MSG_ID_SYNC_TIMER0_DONE 18
+#define MSG_ID_SYNC_TIMER1_DONE 19
+#define MSG_ID_SYNC_TIMER2_DONE 20
+#define MSG_ID_ASYNC_TIMER0_DONE 21
+#define MSG_ID_ASYNC_TIMER1_DONE 22
+#define MSG_ID_ASYNC_TIMER2_DONE 23
+#define MSG_ID_ASYNC_TIMER3_DONE 24
+#define MSG_ID_AE_OVERFLOW 25
+#define MSG_ID_AF_OVERFLOW 26
+#define MSG_ID_AWB_OVERFLOW 27
+#define MSG_ID_RS_OVERFLOW 28
+#define MSG_ID_CS_OVERFLOW 29
+#define MSG_ID_IHIST_OVERFLOW 30
+#define MSG_ID_SKIN_OVERFLOW 31
+#define MSG_ID_AXI_ERROR 32
+#define MSG_ID_CAMIF_OVERFLOW 33
+#define MSG_ID_VIOLATION 34
+#define MSG_ID_CAMIF_ERROR 35
+#define MSG_ID_BUS_OVERFLOW 36
+#define MSG_ID_SOF_ACK 37
+#define MSG_ID_STOP_REC_ACK 38
+#define MSG_ID_STATS_AWB_AEC 39
+#define MSG_ID_OUTPUT_PRIMARY 40
+#define MSG_ID_OUTPUT_SECONDARY 41
+#define MSG_ID_STATS_COMPOSITE 42
+#define MSG_ID_OUTPUT_TERTIARY1 43
+#define MSG_ID_STOP_LS_ACK 44
+#define MSG_ID_OUTPUT_TERTIARY2 45
+#define MSG_ID_STATS_BG 46
+#define MSG_ID_STATS_BF 47
+#define MSG_ID_STATS_BHIST 48
+#define MSG_ID_RDI0_UPDATE_ACK 49
+#define MSG_ID_RDI1_UPDATE_ACK 50
+#define MSG_ID_RDI2_UPDATE_ACK 51
+
+/* ISP command IDs */
+#define VFE_CMD_DUMMY_0 0
+#define VFE_CMD_SET_CLK 1
+#define VFE_CMD_RESET 2
+#define VFE_CMD_START 3
+#define VFE_CMD_TEST_GEN_START 4
+#define VFE_CMD_OPERATION_CFG 5
+#define VFE_CMD_AXI_OUT_CFG 6
+#define VFE_CMD_CAMIF_CFG 7
+#define VFE_CMD_AXI_INPUT_CFG 8
+#define VFE_CMD_BLACK_LEVEL_CFG 9
+#define VFE_CMD_MESH_ROLL_OFF_CFG 10
+#define VFE_CMD_DEMUX_CFG 11
+#define VFE_CMD_FOV_CFG 12
+#define VFE_CMD_MAIN_SCALER_CFG 13
+#define VFE_CMD_WB_CFG 14
+#define VFE_CMD_COLOR_COR_CFG 15
+#define VFE_CMD_RGB_G_CFG 16
+#define VFE_CMD_LA_CFG 17
+#define VFE_CMD_CHROMA_EN_CFG 18
+#define VFE_CMD_CHROMA_SUP_CFG 19
+#define VFE_CMD_MCE_CFG 20
+#define VFE_CMD_SK_ENHAN_CFG 21
+#define VFE_CMD_ASF_CFG 22
+#define VFE_CMD_S2Y_CFG 23
+#define VFE_CMD_S2CbCr_CFG 24
+#define VFE_CMD_CHROMA_SUBS_CFG 25
+#define VFE_CMD_OUT_CLAMP_CFG 26
+#define VFE_CMD_FRAME_SKIP_CFG 27
+#define VFE_CMD_DUMMY_1 28
+#define VFE_CMD_DUMMY_2 29
+#define VFE_CMD_DUMMY_3 30
+#define VFE_CMD_UPDATE 31
+#define VFE_CMD_BL_LVL_UPDATE 32
+#define VFE_CMD_DEMUX_UPDATE 33
+#define VFE_CMD_FOV_UPDATE 34
+#define VFE_CMD_MAIN_SCALER_UPDATE 35
+#define VFE_CMD_WB_UPDATE 36
+#define VFE_CMD_COLOR_COR_UPDATE 37
+#define VFE_CMD_RGB_G_UPDATE 38
+#define VFE_CMD_LA_UPDATE 39
+#define VFE_CMD_CHROMA_EN_UPDATE 40
+#define VFE_CMD_CHROMA_SUP_UPDATE 41
+#define VFE_CMD_MCE_UPDATE 42
+#define VFE_CMD_SK_ENHAN_UPDATE 43
+#define VFE_CMD_S2CbCr_UPDATE 44
+#define VFE_CMD_S2Y_UPDATE 45
+#define VFE_CMD_ASF_UPDATE 46
+#define VFE_CMD_FRAME_SKIP_UPDATE 47
+#define VFE_CMD_CAMIF_FRAME_UPDATE 48
+#define VFE_CMD_STATS_AF_UPDATE 49
+#define VFE_CMD_STATS_AE_UPDATE 50
+#define VFE_CMD_STATS_AWB_UPDATE 51
+#define VFE_CMD_STATS_RS_UPDATE 52
+#define VFE_CMD_STATS_CS_UPDATE 53
+#define VFE_CMD_STATS_SKIN_UPDATE 54
+#define VFE_CMD_STATS_IHIST_UPDATE 55
+#define VFE_CMD_DUMMY_4 56
+#define VFE_CMD_EPOCH1_ACK 57
+#define VFE_CMD_EPOCH2_ACK 58
+#define VFE_CMD_START_RECORDING 59
+#define VFE_CMD_STOP_RECORDING 60
+#define VFE_CMD_DUMMY_5 61
+#define VFE_CMD_DUMMY_6 62
+#define VFE_CMD_CAPTURE 63
+#define VFE_CMD_DUMMY_7 64
+#define VFE_CMD_STOP 65
+#define VFE_CMD_GET_HW_VERSION 66
+#define VFE_CMD_GET_FRAME_SKIP_COUNTS 67
+#define VFE_CMD_OUTPUT1_BUFFER_ENQ 68
+#define VFE_CMD_OUTPUT2_BUFFER_ENQ 69
+#define VFE_CMD_OUTPUT3_BUFFER_ENQ 70
+#define VFE_CMD_JPEG_OUT_BUF_ENQ 71
+#define VFE_CMD_RAW_OUT_BUF_ENQ 72
+#define VFE_CMD_RAW_IN_BUF_ENQ 73
+#define VFE_CMD_STATS_AF_ENQ 74
+#define VFE_CMD_STATS_AE_ENQ 75
+#define VFE_CMD_STATS_AWB_ENQ 76
+#define VFE_CMD_STATS_RS_ENQ 77
+#define VFE_CMD_STATS_CS_ENQ 78
+#define VFE_CMD_STATS_SKIN_ENQ 79
+#define VFE_CMD_STATS_IHIST_ENQ 80
+#define VFE_CMD_DUMMY_8 81
+#define VFE_CMD_JPEG_ENC_CFG 82
+#define VFE_CMD_DUMMY_9 83
+#define VFE_CMD_STATS_AF_START 84
+#define VFE_CMD_STATS_AF_STOP 85
+#define VFE_CMD_STATS_AE_START 86
+#define VFE_CMD_STATS_AE_STOP 87
+#define VFE_CMD_STATS_AWB_START 88
+#define VFE_CMD_STATS_AWB_STOP 89
+#define VFE_CMD_STATS_RS_START 90
+#define VFE_CMD_STATS_RS_STOP 91
+#define VFE_CMD_STATS_CS_START 92
+#define VFE_CMD_STATS_CS_STOP 93
+#define VFE_CMD_STATS_SKIN_START 94
+#define VFE_CMD_STATS_SKIN_STOP 95
+#define VFE_CMD_STATS_IHIST_START 96
+#define VFE_CMD_STATS_IHIST_STOP 97
+#define VFE_CMD_DUMMY_10 98
+#define VFE_CMD_SYNC_TIMER_SETTING 99
+#define VFE_CMD_ASYNC_TIMER_SETTING 100
+#define VFE_CMD_LIVESHOT 101
+#define VFE_CMD_LA_SETUP 102
+#define VFE_CMD_LINEARIZATION_CFG 103
+#define VFE_CMD_DEMOSAICV3 104
+#define VFE_CMD_DEMOSAICV3_ABCC_CFG 105
+#define VFE_CMD_DEMOSAICV3_DBCC_CFG 106
+#define VFE_CMD_DEMOSAICV3_DBPC_CFG 107
+#define VFE_CMD_DEMOSAICV3_ABF_CFG 108
+#define VFE_CMD_DEMOSAICV3_ABCC_UPDATE 109
+#define VFE_CMD_DEMOSAICV3_DBCC_UPDATE 110
+#define VFE_CMD_DEMOSAICV3_DBPC_UPDATE 111
+#define VFE_CMD_XBAR_CFG 112
+#define VFE_CMD_MODULE_CFG 113
+#define VFE_CMD_ZSL 114
+#define VFE_CMD_LINEARIZATION_UPDATE 115
+#define VFE_CMD_DEMOSAICV3_ABF_UPDATE 116
+#define VFE_CMD_CLF_CFG 117
+#define VFE_CMD_CLF_LUMA_UPDATE 118
+#define VFE_CMD_CLF_CHROMA_UPDATE 119
+#define VFE_CMD_PCA_ROLL_OFF_CFG 120
+#define VFE_CMD_PCA_ROLL_OFF_UPDATE 121
+#define VFE_CMD_GET_REG_DUMP 122
+#define VFE_CMD_GET_LINEARIZATON_TABLE 123
+#define VFE_CMD_GET_MESH_ROLLOFF_TABLE 124
+#define VFE_CMD_GET_PCA_ROLLOFF_TABLE 125
+#define VFE_CMD_GET_RGB_G_TABLE 126
+#define VFE_CMD_GET_LA_TABLE 127
+#define VFE_CMD_DEMOSAICV3_UPDATE 128
+#define VFE_CMD_ACTIVE_REGION_CFG 129
+#define VFE_CMD_COLOR_PROCESSING_CONFIG 130
+#define VFE_CMD_STATS_WB_AEC_CONFIG 131
+#define VFE_CMD_STATS_WB_AEC_UPDATE 132
+#define VFE_CMD_Y_GAMMA_CONFIG 133
+#define VFE_CMD_SCALE_OUTPUT1_CONFIG 134
+#define VFE_CMD_SCALE_OUTPUT2_CONFIG 135
+#define VFE_CMD_CAPTURE_RAW 136
+#define VFE_CMD_STOP_LIVESHOT 137
+#define VFE_CMD_RECONFIG_VFE 138
+#define VFE_CMD_STATS_REQBUF 139
+#define VFE_CMD_STATS_ENQUEUEBUF 140
+#define VFE_CMD_STATS_FLUSH_BUFQ 141
+#define VFE_CMD_STATS_UNREGBUF 142
+#define VFE_CMD_STATS_BG_START 143
+#define VFE_CMD_STATS_BG_STOP 144
+#define VFE_CMD_STATS_BF_START 145
+#define VFE_CMD_STATS_BF_STOP 146
+#define VFE_CMD_STATS_BHIST_START 147
+#define VFE_CMD_STATS_BHIST_STOP 148
+#define VFE_CMD_RESET_2 149
+#define VFE_CMD_FOV_ENC_CFG 150
+#define VFE_CMD_FOV_VIEW_CFG 151
+#define VFE_CMD_FOV_ENC_UPDATE 152
+#define VFE_CMD_FOV_VIEW_UPDATE 153
+#define VFE_CMD_SCALER_ENC_CFG 154
+#define VFE_CMD_SCALER_VIEW_CFG 155
+#define VFE_CMD_SCALER_ENC_UPDATE 156
+#define VFE_CMD_SCALER_VIEW_UPDATE 157
+#define VFE_CMD_COLORXFORM_ENC_CFG 158
+#define VFE_CMD_COLORXFORM_VIEW_CFG 159
+#define VFE_CMD_COLORXFORM_ENC_UPDATE 160
+#define VFE_CMD_COLORXFORM_VIEW_UPDATE 161
+#define VFE_CMD_TEST_GEN_CFG 162
+
+struct msm_isp_cmd {
+ int32_t id;
+ uint16_t length;
+ void *value;
+};
+
+#define VPE_CMD_DUMMY_0 0
+#define VPE_CMD_INIT 1
+#define VPE_CMD_DEINIT 2
+#define VPE_CMD_ENABLE 3
+#define VPE_CMD_DISABLE 4
+#define VPE_CMD_RESET 5
+#define VPE_CMD_FLUSH 6
+#define VPE_CMD_OPERATION_MODE_CFG 7
+#define VPE_CMD_INPUT_PLANE_CFG 8
+#define VPE_CMD_OUTPUT_PLANE_CFG 9
+#define VPE_CMD_INPUT_PLANE_UPDATE 10
+#define VPE_CMD_SCALE_CFG_TYPE 11
+#define VPE_CMD_ZOOM 13
+#define VPE_CMD_MAX 14
+
+#define MSM_PP_CMD_TYPE_NOT_USED 0 /* not used */
+#define MSM_PP_CMD_TYPE_VPE 1 /* VPE cmd */
+#define MSM_PP_CMD_TYPE_MCTL 2 /* MCTL cmd */
+
+#define MCTL_CMD_DUMMY_0 0 /* not used */
+#define MCTL_CMD_GET_FRAME_BUFFER 1 /* reserve a free frame buffer */
+#define MCTL_CMD_PUT_FRAME_BUFFER 2 /* return the free frame buffer */
+#define MCTL_CMD_DIVERT_FRAME_PP_PATH 3 /* divert frame for pp */
+
+/* event typese sending to MCTL PP module */
+#define MCTL_PP_EVENT_NOTUSED 0
+#define MCTL_PP_EVENT_CMD_ACK 1
+
+#define VPE_OPERATION_MODE_CFG_LEN 4
+#define VPE_INPUT_PLANE_CFG_LEN 24
+#define VPE_OUTPUT_PLANE_CFG_LEN 20
+#define VPE_INPUT_PLANE_UPDATE_LEN 12
+#define VPE_SCALER_CONFIG_LEN 260
+#define VPE_DIS_OFFSET_CFG_LEN 12
+
+
+#define CAPTURE_WIDTH 1280
+#define IMEM_Y_SIZE (CAPTURE_WIDTH*16)
+#define IMEM_CBCR_SIZE (CAPTURE_WIDTH*8)
+
+#define IMEM_Y_PING_OFFSET 0x2E000000
+#define IMEM_CBCR_PING_OFFSET (IMEM_Y_PING_OFFSET + IMEM_Y_SIZE)
+
+#define IMEM_Y_PONG_OFFSET (IMEM_CBCR_PING_OFFSET + IMEM_CBCR_SIZE)
+#define IMEM_CBCR_PONG_OFFSET (IMEM_Y_PONG_OFFSET + IMEM_Y_SIZE)
+
+
+struct msm_vpe_op_mode_cfg {
+ uint8_t op_mode_cfg[VPE_OPERATION_MODE_CFG_LEN];
+};
+
+struct msm_vpe_input_plane_cfg {
+ uint8_t input_plane_cfg[VPE_INPUT_PLANE_CFG_LEN];
+};
+
+struct msm_vpe_output_plane_cfg {
+ uint8_t output_plane_cfg[VPE_OUTPUT_PLANE_CFG_LEN];
+};
+
+struct msm_vpe_input_plane_update_cfg {
+ uint8_t input_plane_update_cfg[VPE_INPUT_PLANE_UPDATE_LEN];
+};
+
+struct msm_vpe_scaler_cfg {
+ uint8_t scaler_cfg[VPE_SCALER_CONFIG_LEN];
+};
+
+struct msm_vpe_flush_frame_buffer {
+ uint32_t src_buf_handle;
+ uint32_t dest_buf_handle;
+ int path;
+};
+
+struct msm_mctl_pp_frame_buffer {
+ uint32_t buf_handle;
+ int path;
+};
+struct msm_mctl_pp_divert_pp {
+ int path;
+ int enable;
+};
+struct msm_vpe_clock_rate {
+ uint32_t rate;
+};
+struct msm_pp_crop {
+ uint32_t src_x;
+ uint32_t src_y;
+ uint32_t src_w;
+ uint32_t src_h;
+ uint32_t dst_x;
+ uint32_t dst_y;
+ uint32_t dst_w;
+ uint32_t dst_h;
+ uint8_t update_flag;
+};
+#define MSM_MCTL_PP_VPE_FRAME_ACK (1<<0)
+#define MSM_MCTL_PP_VPE_FRAME_TO_APP (1<<1)
+
+struct msm_mctl_pp_frame_cmd {
+ uint32_t cookie;
+ uint8_t vpe_output_action;
+ uint32_t src_buf_handle;
+ uint32_t dest_buf_handle;
+ struct msm_pp_crop crop;
+ int path;
+ /* TBD: 3D related */
+};
+
+#define VFE_OUTPUTS_MAIN_AND_PREVIEW BIT(0)
+#define VFE_OUTPUTS_MAIN_AND_VIDEO BIT(1)
+#define VFE_OUTPUTS_MAIN_AND_THUMB BIT(2)
+#define VFE_OUTPUTS_THUMB_AND_MAIN BIT(3)
+#define VFE_OUTPUTS_PREVIEW_AND_VIDEO BIT(4)
+#define VFE_OUTPUTS_VIDEO_AND_PREVIEW BIT(5)
+#define VFE_OUTPUTS_PREVIEW BIT(6)
+#define VFE_OUTPUTS_VIDEO BIT(7)
+#define VFE_OUTPUTS_RAW BIT(8)
+#define VFE_OUTPUTS_JPEG_AND_THUMB BIT(9)
+#define VFE_OUTPUTS_THUMB_AND_JPEG BIT(10)
+#define VFE_OUTPUTS_RDI0 BIT(11)
+#define VFE_OUTPUTS_RDI1 BIT(12)
+
+struct msm_frame_info {
+ uint32_t inst_handle;
+ uint32_t path;
+};
+
+#endif /*__MSM_ISP_H__*/
+
diff --git a/original/media/msm_mercury.h b/original/media/msm_mercury.h
new file mode 100644
index 0000000..1d14724
--- /dev/null
+++ b/original/media/msm_mercury.h
@@ -0,0 +1,119 @@
+#ifndef __LINUX_MSM_MERCURY_H
+#define __LINUX_MSM_MERCURY_H
+
+#include <linux/types.h>
+#include <linux/ioctl.h>
+
+#define MSM_MERCURY_HW_VERSION_REG 0x0004/* this offset does not exist in HW*/
+
+#define OUTPUT_H2V1 0
+#define OUTPUT_H2V2 1
+#define OUTPUT_BYTE 6
+
+#define MSM_MERCURY_MODE_REALTIME_ENCODE 0
+#define MSM_MERCURY_MODE_OFFLINE_ENCODE 1
+#define MSM_MERCURY_MODE_REALTIME_ROTATION 2
+#define MSM_MERCURY_MODE_OFFLINE_ROTATION 3
+
+#define MSM_MERCURY_EVT_RESET 1
+#define MSM_MERCURY_EVT_FRAMEDONE 2
+#define MSM_MERCURY_EVT_ERR 3
+#define MSM_MERCURY_EVT_UNBLOCK 4
+
+#define MSM_MERCURY_HW_CMD_TYPE_READ 0
+#define MSM_MERCURY_HW_CMD_TYPE_WRITE 1
+#define MSM_MERCURY_HW_CMD_TYPE_WRITE_OR 2
+#define MSM_MERCURY_HW_CMD_TYPE_UWAIT 3
+#define MSM_MERCURY_HW_CMD_TYPE_MWAIT 4
+#define MSM_MERCURY_HW_CMD_TYPE_MDELAY 5
+#define MSM_MERCURY_HW_CMD_TYPE_UDELAY 6
+
+#define MSM_MCR_IOCTL_MAGIC 'g'
+
+#define MSM_MCR_IOCTL_GET_HW_VERSION \
+ _IOW(MSM_MCR_IOCTL_MAGIC, 1, struct msm_mercury_hw_cmd *)
+
+#define MSM_MCR_IOCTL_RESET \
+ _IOW(MSM_MCR_IOCTL_MAGIC, 2, struct msm_mercury_ctrl_cmd *)
+
+#define MSM_MCR_IOCTL_STOP \
+ _IOW(MSM_MCR_IOCTL_MAGIC, 3, struct msm_mercury_hw_cmds *)
+
+#define MSM_MCR_IOCTL_START \
+ _IOW(MSM_MCR_IOCTL_MAGIC, 4, struct msm_mercury_hw_cmds *)
+
+#define MSM_MCR_IOCTL_INPUT_BUF_CFG \
+ _IOW(MSM_MCR_IOCTL_MAGIC, 5, struct msm_mercury_buf *)
+
+#define MSM_MCR_IOCTL_INPUT_GET \
+ _IOW(MSM_MCR_IOCTL_MAGIC, 6, struct msm_mercury_buf *)
+
+#define MSM_MCR_IOCTL_INPUT_GET_UNBLOCK \
+ _IOW(MSM_MCR_IOCTL_MAGIC, 7, int)
+
+#define MSM_MCR_IOCTL_OUTPUT_BUF_CFG \
+ _IOW(MSM_MCR_IOCTL_MAGIC, 8, struct msm_mercury_buf *)
+
+#define MSM_MCR_IOCTL_OUTPUT_GET \
+ _IOW(MSM_MCR_IOCTL_MAGIC, 9, struct msm_mercury_buf *)
+
+#define MSM_MCR_IOCTL_OUTPUT_GET_UNBLOCK \
+ _IOW(MSM_MCR_IOCTL_MAGIC, 10, int)
+
+#define MSM_MCR_IOCTL_EVT_GET \
+ _IOW(MSM_MCR_IOCTL_MAGIC, 11, struct msm_mercury_ctrl_cmd *)
+
+#define MSM_MCR_IOCTL_EVT_GET_UNBLOCK \
+ _IOW(MSM_MCR_IOCTL_MAGIC, 12, int)
+
+#define MSM_MCR_IOCTL_HW_CMD \
+ _IOW(MSM_MCR_IOCTL_MAGIC, 13, struct msm_mercury_hw_cmd *)
+
+#define MSM_MCR_IOCTL_HW_CMDS \
+ _IOW(MSM_MCR_IOCTL_MAGIC, 14, struct msm_mercury_hw_cmds *)
+
+#define MSM_MCR_IOCTL_TEST_DUMP_REGION \
+ _IOW(MSM_MCR_IOCTL_MAGIC, 15, unsigned long)
+
+struct msm_mercury_ctrl_cmd {
+ uint32_t type;
+ uint32_t len;
+ void *value;
+};
+
+struct msm_mercury_buf {
+ uint32_t type;
+ int fd;
+ void *vaddr;
+ uint32_t y_off;
+ uint32_t y_len;
+ uint32_t framedone_len;
+ uint32_t cbcr_off;
+ uint32_t cbcr_len;
+ uint32_t num_of_mcu_rows;
+ uint32_t offset;
+};
+
+struct msm_mercury_hw_cmd {
+
+ uint32_t type:4;
+ /* n microseconds of timeout for WAIT */
+ /* n microseconds of time for DELAY */
+ /* repeat n times for READ/WRITE */
+ /* max is 0xFFF, 4095 */
+ uint32_t n:12;
+ uint32_t offset:16;
+ uint32_t mask;
+ union {
+ /* for single READ/WRITE/WAIT, n = 1 */
+ uint32_t data;
+ uint32_t *pdata;/* for multiple READ/WRITE/WAIT, n > 1 */
+ };
+};
+
+struct msm_mercury_hw_cmds {
+ uint32_t m; /* number of elements in the hw_cmd array */
+ struct msm_mercury_hw_cmd hw_cmd[1];
+};
+
+#endif /* __LINUX_MSM_MERCURY_H */
diff --git a/original/media/v4l2-mediabus.h b/original/media/v4l2-mediabus.h
new file mode 100644
index 0000000..83ae07e
--- /dev/null
+++ b/original/media/v4l2-mediabus.h
@@ -0,0 +1,107 @@
+/*
+ * Media Bus API header
+ *
+ * Copyright (C) 2009, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef V4L2_MEDIABUS_H
+#define V4L2_MEDIABUS_H
+
+#include <linux/v4l2-mediabus.h>
+
+/* Parallel flags */
+/*
+ * Can the client run in master or in slave mode. By "Master mode" an operation
+ * mode is meant, when the client (e.g., a camera sensor) is producing
+ * horizontal and vertical synchronisation. In "Slave mode" the host is
+ * providing these signals to the slave.
+ */
+#define V4L2_MBUS_MASTER (1 << 0)
+#define V4L2_MBUS_SLAVE (1 << 1)
+/*
+ * Signal polarity flags
+ * Note: in BT.656 mode HSYNC, FIELD, and VSYNC are unused
+ * V4L2_MBUS_[HV]SYNC* flags should be also used for specifying
+ * configuration of hardware that uses [HV]REF signals
+ */
+#define V4L2_MBUS_HSYNC_ACTIVE_HIGH (1 << 2)
+#define V4L2_MBUS_HSYNC_ACTIVE_LOW (1 << 3)
+#define V4L2_MBUS_VSYNC_ACTIVE_HIGH (1 << 4)
+#define V4L2_MBUS_VSYNC_ACTIVE_LOW (1 << 5)
+#define V4L2_MBUS_PCLK_SAMPLE_RISING (1 << 6)
+#define V4L2_MBUS_PCLK_SAMPLE_FALLING (1 << 7)
+#define V4L2_MBUS_DATA_ACTIVE_HIGH (1 << 8)
+#define V4L2_MBUS_DATA_ACTIVE_LOW (1 << 9)
+/* FIELD = 0/1 - Field1 (odd)/Field2 (even) */
+#define V4L2_MBUS_FIELD_EVEN_HIGH (1 << 10)
+/* FIELD = 1/0 - Field1 (odd)/Field2 (even) */
+#define V4L2_MBUS_FIELD_EVEN_LOW (1 << 11)
+
+/* Serial flags */
+/* How many lanes the client can use */
+#define V4L2_MBUS_CSI2_1_LANE (1 << 0)
+#define V4L2_MBUS_CSI2_2_LANE (1 << 1)
+#define V4L2_MBUS_CSI2_3_LANE (1 << 2)
+#define V4L2_MBUS_CSI2_4_LANE (1 << 3)
+/* On which channels it can send video data */
+#define V4L2_MBUS_CSI2_CHANNEL_0 (1 << 4)
+#define V4L2_MBUS_CSI2_CHANNEL_1 (1 << 5)
+#define V4L2_MBUS_CSI2_CHANNEL_2 (1 << 6)
+#define V4L2_MBUS_CSI2_CHANNEL_3 (1 << 7)
+/* Does it support only continuous or also non-continuous clock mode */
+#define V4L2_MBUS_CSI2_CONTINUOUS_CLOCK (1 << 8)
+#define V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK (1 << 9)
+
+#define V4L2_MBUS_CSI2_LANES (V4L2_MBUS_CSI2_1_LANE | V4L2_MBUS_CSI2_2_LANE | \
+ V4L2_MBUS_CSI2_3_LANE | V4L2_MBUS_CSI2_4_LANE)
+#define V4L2_MBUS_CSI2_CHANNELS (V4L2_MBUS_CSI2_CHANNEL_0 | V4L2_MBUS_CSI2_CHANNEL_1 | \
+ V4L2_MBUS_CSI2_CHANNEL_2 | V4L2_MBUS_CSI2_CHANNEL_3)
+
+/**
+ * v4l2_mbus_type - media bus type
+ * @V4L2_MBUS_PARALLEL: parallel interface with hsync and vsync
+ * @V4L2_MBUS_BT656: parallel interface with embedded synchronisation, can
+ * also be used for BT.1120
+ * @V4L2_MBUS_CSI2: MIPI CSI-2 serial interface
+ */
+enum v4l2_mbus_type {
+ V4L2_MBUS_PARALLEL,
+ V4L2_MBUS_BT656,
+ V4L2_MBUS_CSI2,
+};
+
+/**
+ * v4l2_mbus_config - media bus configuration
+ * @type: in: interface type
+ * @flags: in / out: configuration flags, depending on @type
+ */
+struct v4l2_mbus_config {
+ enum v4l2_mbus_type type;
+ unsigned int flags;
+};
+
+static inline void v4l2_fill_pix_format(struct v4l2_pix_format *pix_fmt,
+ const struct v4l2_mbus_framefmt *mbus_fmt)
+{
+ pix_fmt->width = mbus_fmt->width;
+ pix_fmt->height = mbus_fmt->height;
+ pix_fmt->field = mbus_fmt->field;
+ pix_fmt->colorspace = mbus_fmt->colorspace;
+}
+
+static inline void v4l2_fill_mbus_format(struct v4l2_mbus_framefmt *mbus_fmt,
+ const struct v4l2_pix_format *pix_fmt,
+ enum v4l2_mbus_pixelcode code)
+{
+ mbus_fmt->width = pix_fmt->width;
+ mbus_fmt->height = pix_fmt->height;
+ mbus_fmt->field = pix_fmt->field;
+ mbus_fmt->colorspace = pix_fmt->colorspace;
+ mbus_fmt->code = code;
+}
+
+#endif
diff --git a/original/sound/tlv.h b/original/sound/tlv.h
new file mode 100644
index 0000000..7067e2d
--- /dev/null
+++ b/original/sound/tlv.h
@@ -0,0 +1,76 @@
+#ifndef __SOUND_TLV_H
+#define __SOUND_TLV_H
+
+/*
+ * Advanced Linux Sound Architecture - ALSA - Driver
+ * Copyright (c) 2006 by Jaroslav Kysela <perex@perex.cz>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+/*
+ * TLV structure is right behind the struct snd_ctl_tlv:
+ * unsigned int type - see SNDRV_CTL_TLVT_*
+ * unsigned int length
+ * .... data aligned to sizeof(unsigned int), use
+ * block_length = (length + (sizeof(unsigned int) - 1)) &
+ * ~(sizeof(unsigned int) - 1)) ....
+ */
+
+#define SNDRV_CTL_TLVT_CONTAINER 0 /* one level down - group of TLVs */
+#define SNDRV_CTL_TLVT_DB_SCALE 1 /* dB scale */
+#define SNDRV_CTL_TLVT_DB_LINEAR 2 /* linear volume */
+#define SNDRV_CTL_TLVT_DB_RANGE 3 /* dB range container */
+#define SNDRV_CTL_TLVT_DB_MINMAX 4 /* dB scale with min/max */
+#define SNDRV_CTL_TLVT_DB_MINMAX_MUTE 5 /* dB scale with min/max with mute */
+
+#define TLV_DB_SCALE_MASK 0xffff
+#define TLV_DB_SCALE_MUTE 0x10000
+#define TLV_DB_SCALE_ITEM(min, step, mute) \
+ SNDRV_CTL_TLVT_DB_SCALE, 2 * sizeof(unsigned int), \
+ (min), ((step) & TLV_DB_SCALE_MASK) | ((mute) ? TLV_DB_SCALE_MUTE : 0)
+#define DECLARE_TLV_DB_SCALE(name, min, step, mute) \
+ unsigned int name[] = { TLV_DB_SCALE_ITEM(min, step, mute) }
+
+/* dB scale specified with min/max values instead of step */
+#define TLV_DB_MINMAX_ITEM(min_dB, max_dB) \
+ SNDRV_CTL_TLVT_DB_MINMAX, 2 * sizeof(unsigned int), \
+ (min_dB), (max_dB)
+#define TLV_DB_MINMAX_MUTE_ITEM(min_dB, max_dB) \
+ SNDRV_CTL_TLVT_DB_MINMAX_MUTE, 2 * sizeof(unsigned int), \
+ (min_dB), (max_dB)
+#define DECLARE_TLV_DB_MINMAX(name, min_dB, max_dB) \
+ unsigned int name[] = { TLV_DB_MINMAX_ITEM(min_dB, max_dB) }
+#define DECLARE_TLV_DB_MINMAX_MUTE(name, min_dB, max_dB) \
+ unsigned int name[] = { TLV_DB_MINMAX_MUTE_ITEM(min_dB, max_dB) }
+
+/* linear volume between min_dB and max_dB (.01dB unit) */
+#define TLV_DB_LINEAR_ITEM(min_dB, max_dB) \
+ SNDRV_CTL_TLVT_DB_LINEAR, 2 * sizeof(unsigned int), \
+ (min_dB), (max_dB)
+#define DECLARE_TLV_DB_LINEAR(name, min_dB, max_dB) \
+ unsigned int name[] = { TLV_DB_LINEAR_ITEM(min_dB, max_dB) }
+
+/* dB range container */
+/* Each item is: <min> <max> <TLV> */
+/* The below assumes that each item TLV is 4 words like DB_SCALE or LINEAR */
+#define TLV_DB_RANGE_HEAD(num) \
+ SNDRV_CTL_TLVT_DB_RANGE, 6 * (num) * sizeof(unsigned int)
+
+#define TLV_DB_GAIN_MUTE -9999999
+
+#endif /* __SOUND_TLV_H */
