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ara-mdk / platform / external / llvm / 707e0184233f27e0e9f9aee0309f2daab8cfe7f8 / lib / Target / PowerPC / PPCISelLowering.cpp
  1. 707e018 Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal by Dan Gohman · 17 years ago
  2. 36b5c13 Rename MemOperand to MachineMemOperand. This was suggested by by Dan Gohman · 17 years ago
  3. dc1adac Re-commit of the r48822, where the infinite looping problem discovered by Roman Levenstein · 17 years ago
  4. 6397c64 Backing out 48222 temporarily. by Evan Cheng · 17 years ago
  5. d27c991 Fix "Control reaches the end of non-void function" warnings, by Chris Lattner · 17 years ago
  6. e326332 Use a linked data structure for the uses lists of an SDNode, just like by Roman Levenstein · 17 years ago
  7. 3e98c30 Use the bit size of the operand instead of the hard-coded 32 to generate the by Bill Wendling · 17 years ago
  8. 276dcbd Introduce a new node for holding call argument by Duncan Sands · 17 years ago
  9. 7925ed0 Add support for multiple return values for the PPC target by by Dan Gohman · 17 years ago
  10. 257f75d Make Complex long long/double/long double work in ppc64 mode. by Dale Johannesen · 17 years ago
  11. fdd3ade Next round of PPC32 ABI changes. Allow for gcc by Dale Johannesen · 17 years ago
  12. 8f5422c Implement the real calling convention for ppc32 Altivec: by Dale Johannesen · 17 years ago
  13. d75686a Do not promote float params to double in varargs by Dale Johannesen · 17 years ago
  14. 404d990 One more bit of Altivec parameter passing. by Dale Johannesen · 17 years ago
  15. 75092de Implement Altivec passing to varargs functions on ppc. by Dale Johannesen · 17 years ago
  16. 034f60e Generalize ExpandIntToFP to handle the case where the operand is legal by Dan Gohman · 17 years ago
  17. d2cde68 Default ISD::PREFETCH to expand. by Evan Cheng · 17 years ago
  18. 5b8f82e Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's by Scott Michel · 17 years ago
  19. 0404cd9 Add description of individual bits in CR. This fix PR1765. by Nicolas Geoffray · 17 years ago
  20. b8cafe3 Increase ISD::ParamFlags to 64 bits. Increase the ByValSize by Dale Johannesen · 17 years ago
  21. dc9971a Darwin PPC64 indirect call target goes in X12, not R12. This fixes these by Chris Lattner · 17 years ago
  22. 7f96f39 More ppc32 byval handling (bug fixes). Things are looking pretty good now. by Dale Johannesen · 17 years ago
  23. 27b7db5 Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions. by Evan Cheng · 17 years ago
  24. a2fcff4 Add support for calls with i128 return values on ppc64. by Dan Gohman · 17 years ago
  25. 5f5bf3a PPC64 passes arguments of integral type in i64 registers, not i32. Reflect this by Bill Wendling · 17 years ago
  26. 9ed06db Add support for lowering 128-bit shifts on ppc64. by Dan Gohman · 17 years ago
  27. 8419dd6 Next bits of PPC byval handling. Basically functional but there are bugs. by Dale Johannesen · 17 years ago
  28. 1f797a3 Next bit of PPC ByVal handling; call-site code seems correct now. by Dale Johannesen · 17 years ago
  29. 5b3b695 Move PPC lowering functions into PPCTargetLowering by Dale Johannesen · 17 years ago
  30. 28d08fd Interface of getByValTypeAlignment differed between by Dale Johannesen · 17 years ago
  31. ec59b95 Don't hard-code the mask size to be 32, which is incorrect on ppc64 by Dan Gohman · 17 years ago
  32. b3564aa Convert the last remaining users of the non-APInt form of by Dan Gohman · 17 years ago
  33. d497d9f I cannot find a libgcc function for this builtin. Therefor expanding it to a noop (which is how it use to be treated). If someone who knows the x86 backend better than me could tell me how to get a lock prefix on an instruction, that would be nice to complete x86 support. by Andrew Lenharth · 17 years ago
  34. e179584 Change how FP immediates are handled. by Nate Begeman · 17 years ago
  35. 977a76f Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBits by Dan Gohman · 17 years ago
  36. 9f72d1a don't try to avoid inserting loads when lowering FORMAL_ARGUMENTS. by Chris Lattner · 17 years ago
  37. fd29e0e Convert SelectionDAG::ComputeMaskedBits to use APInt instead of uint64_t. by Dan Gohman · 17 years ago
  38. 3069b87 Follow Chris' suggestion; change the PseudoSourceValue accessors by Dan Gohman · 17 years ago
  39. 69de193 Re-apply the memory operand changes, with a fix for the static by Dan Gohman · 17 years ago
  40. fcf5d4f Unbreak ppc debug support. by Evan Cheng · 17 years ago
  41. 334dc1f Revert 46556 and 46585. Dan please fix the PseudoSourceValue problem and re-commit. by Evan Cheng · 17 years ago
  42. 1a02486 Rename ISD::FLT_ROUNDS to ISD::FLT_ROUNDS_ to avoid conflicting by Dan Gohman · 17 years ago
  43. c6c391d Create a new class, MemOperand, for describing memory references by Dan Gohman · 17 years ago
  44. ff9b373 Even though InsertAtEndOfBasicBlock is an ugly hack it still deserves a proper name. Rename it to EmitInstrWithCustomInserter since it does not necessarily insert by Evan Cheng · 17 years ago
  45. b625f2f Factor the addressing mode and the load/store VT out of LoadSDNode by Dan Gohman · 17 years ago
  46. f9c98e6 The last pieces needed for loading arbitrary by Duncan Sands · 17 years ago
  47. 5c5eb80 Implement flt_rounds for PowerPC. by Dale Johannesen · 17 years ago
  48. ef97c67 get symbolic information for ppc ldbl nodes. by Chris Lattner · 17 years ago
  49. a7a02fb Fix a latent bug exposed by my truncstore patch. We compiled stfiwx-2.ll to: by Chris Lattner · 17 years ago
  50. ddf8956 This commit changes: by Chris Lattner · 17 years ago
  51. 0bd4893 * Introduce a new SelectionDAG::getIntPtrConstant method by Chris Lattner · 17 years ago
  52. 007f984 Output sinl for a long double FSIN node, not sin. by Duncan Sands · 17 years ago
  53. 84bc542 Rename SSARegMap -> MachineRegisterInfo in keeping with the idea by Chris Lattner · 17 years ago
  54. 4ee451d Remove attribution from file headers, per discussion on llvmdev. by Chris Lattner · 17 years ago
  55. 5a6c91a Fix unintented change from last commit by Nicolas Geoffray · 17 years ago
  56. 616585b Enable EH for linux/ppc32 targets by Nicolas Geoffray · 17 years ago
  57. 3fc027d implement __builtin_return_addr(0) on ppc. by Chris Lattner · 17 years ago
  58. 1f87300 Implement ExpandOperationResult for ppc i64 fp->int, which fixes by Chris Lattner · 17 years ago
  59. 0f8d9c0 Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack by Bill Wendling · 17 years ago
  60. 7921706 Disable a couple more things for ppcf128. by Dale Johannesen · 17 years ago
  61. 3311876 Use ptr type in the immediate field of a BxA instruction so we don't end up selecting 32-bit call instruction for ppc64. by Evan Cheng · 17 years ago
  62. 26cb286 comment fixes by Chris Lattner · 17 years ago
  63. fabd32d More ppcf128 issues (maybe the last)? by Dale Johannesen · 17 years ago
  64. 1de7c1d Change LowerFP_TO_SINT to create the specific code it needs instead of by Chris Lattner · 17 years ago
  65. 296c176 Fix type mismatch error in PPC Altivec (only causes by Dale Johannesen · 17 years ago
  66. a3f269f Mark vector pow, ctpop, cttz, and ctlz as Expand on PowerPC. by Dan Gohman · 17 years ago
  67. f96e4de Set ISD::FPOW to Expand. by Dan Gohman · 17 years ago
  68. 6eaeff2 Next PPC long double bits: ppcf128->i32 conversion. by Dale Johannesen · 17 years ago
  69. 3ce990d When we start enabling SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM in by Dan Gohman · 17 years ago
  70. 638ccd5 Next powerpc long double bits. Comparisons work, by Dale Johannesen · 17 years ago
  71. 161e897 First round of ppc long double. call/return and by Dale Johannesen · 17 years ago
  72. f7331b3 Fold the adjust_trampoline intrinsic into by Duncan Sands · 18 years ago
  73. 718cb66 Add lengthof and endof templates that hide a lot of sizeof computations. by Owen Anderson · 18 years ago
  74. eaf0894 Enhance APFloat to retain bits of NaNs (fixes oggenc). by Dale Johannesen · 18 years ago
  75. b8a80f0 Use i64 on a PPC64 machine by Bill Wendling · 18 years ago
  76. 48884cd rename isOperandValidForConstraint to LowerAsmOperandForConstraint, by Chris Lattner · 18 years ago
  77. 66ffe6b Vector fneg must be expanded into fsub -0.0, X. by Evan Cheng · 18 years ago
  78. 36397f5 Support for trampolines, except for X86 codegen which is still under discussion. by Duncan Sands · 18 years ago
  79. 75ce010 Assert when TLS is not implemented. by Lauro Ramos Venancio · 18 years ago
  80. 532dc2e Change getCopyToParts and getCopyFromParts to always use target-endian by Dan Gohman · 18 years ago
  81. ea859be Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from by Dan Gohman · 18 years ago
  82. 3ee7740 describe an argument, hide it. by Chris Lattner · 18 years ago
  83. 52387be If a function is vararg, never pass inreg arguments in registers. Thanks to by Chris Lattner · 18 years ago
  84. 51eaa86 Rename MVT::getVectorBaseType to MVT::getVectorElementType. by Dan Gohman · 18 years ago
  85. f5135be Apply this patch: by Dan Gohman · 18 years ago
  86. 9f5d578 fix some subtle inline asm selection issues by Chris Lattner · 18 years ago
  87. 7c7ba9d Fix a bug in PPCTargetLowering::isLegalAddressingMode, scales other than 0/1/2 by Chris Lattner · 18 years ago
  88. 0111999 Starting implementation of the ELF32 ABI specification of varargs handling. by Nicolas Geoffray · 18 years ago
  89. ec58d9f The PPC64 ELF ABI is "intended to use the same structure layout and calling convention rules by Nicolas Geoffray · 18 years ago
  90. ef3c030 The ELF ABI specifies F1-F8 registers as argument registers for double, not by Nicolas Geoffray · 18 years ago
  91. c9addb7 implement the new addressing mode description hook. by Chris Lattner · 18 years ago
  92. 1baa197 "The C standards do say that "char" may either be a "signed char" or "unsigned by Lauro Ramos Venancio · 18 years ago
  93. 4234f57 switch TargetLowering::getConstraintType to take the entire constraint, by Chris Lattner · 18 years ago
  94. b2ec1cc Stack and register alignment of call arguments in the ELF ABI by Nicolas Geoffray · 18 years ago
  95. 8619391 More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale. by Evan Cheng · 18 years ago
  96. b9a7bea Switch PPC return lower to use an autogenerated CC description. by Chris Lattner · 18 years ago
  97. 43c6e7c Implemented the frameaddress intrinsic for PPC. by Nicolas Geoffray · 18 years ago
  98. 63f8fb1 Differentiate between the MachO and the ELF ABI the CALL instruction. by Nicolas Geoffray · 18 years ago
  99. caddd44 always lower to RETFLAG, never leave it as just ret. by Chris Lattner · 18 years ago
  100. 4ddf7a4 no really, this is the right patch by Chris Lattner · 18 years ago