- 7b76da1 Fixe typos and 80 column size problems by Bruno Cardoso Lopes · 17 years ago
- 97c2537 MipsTargetLowering cleanup by Bruno Cardoso Lopes · 17 years ago
- 1512642 Pacify gcc-4.3. by Duncan Sands · 17 years ago
- 8e5f2c6 Pool-allocation for MachineInstrs, MachineBasicBlocks, and by Dan Gohman · 17 years ago
- 85e9212 fixed 32-bit fp_to_sint pattern by Bruno Cardoso Lopes · 17 years ago
- 225ca9c Several changes to Mips backend, experimental fp support being the most by Bruno Cardoso Lopes · 17 years ago
- 4406604 Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminating by Dan Gohman · 17 years ago
- 7f46020 Rename ISD::LOCATION to ISD::DBG_STOPPOINT to better reflect its by Dan Gohman · 17 years ago
- f951620 Revert the SelectionDAG optimization that makes by Duncan Sands · 17 years ago
- 83ec4b6 Wrap MVT::ValueType in a struct to get type safety by Duncan Sands · 17 years ago
- 07cec75 Added custom SELECT_CC lowering by Bruno Cardoso Lopes · 17 years ago
- d2947ee Some Mips minor fixes Added support for mips little endian arch => mipsel by Bruno Cardoso Lopes · 17 years ago
- bdbb750 Fixed flag issue that was generating infinite loop while in list scheduling. by Bruno Cardoso Lopes · 17 years ago
- 707e018 Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal by Dan Gohman · 17 years ago
- d27c991 Fix "Control reaches the end of non-void function" warnings, by Chris Lattner · 17 years ago
- e0b1215 minor cleanups by Chris Lattner · 17 years ago
- d2cde68 Default ISD::PREFETCH to expand. by Evan Cheng · 17 years ago
- 5b8f82e Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's by Scott Michel · 17 years ago
- 27b7db5 Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions. by Evan Cheng · 17 years ago
- d497d9f I cannot find a libgcc function for this builtin. Therefor expanding it to a noop (which is how it use to be treated). If someone who knows the x86 backend better than me could tell me how to get a lock prefix on an instruction, that would be nice to complete x86 support. by Andrew Lenharth · 17 years ago
- ddf8956 This commit changes: by Chris Lattner · 17 years ago
- 84bc542 Rename SSARegMap -> MachineRegisterInfo in keeping with the idea by Chris Lattner · 17 years ago
- 4ee451d Remove attribution from file headers, per discussion on llvmdev. by Chris Lattner · 17 years ago
- 0f8d9c0 Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack by Bill Wendling · 17 years ago
- 753a987 Added JumpTable support by Bruno Cardoso Lopes · 17 years ago
- c7db561 Added support for PIC code with "explicit relocations" *only*. by Bruno Cardoso Lopes · 17 years ago
- 8262df3 Position Independent Code (PIC) support [3] by Bruno Cardoso Lopes · 17 years ago
- f7331b3 Fold the adjust_trampoline intrinsic into by Duncan Sands · 18 years ago
- a2b1bb5 Changed stack allocation On LowerFORMAL_ARGUMENTS. by Bruno Cardoso Lopes · 18 years ago
- 84f47c5 InlineAsm asm support for integer registers added by Bruno Cardoso Lopes · 18 years ago
- 7ff6fa2 Removed LowerRETURADDR, fixed small bug into LowerRET, LowerGlobalAddress by Bruno Cardoso Lopes · 18 years ago
- 36397f5 Support for trampolines, except for X86 codegen which is still under discussion. by Duncan Sands · 18 years ago
- 2ab22d1 Fixed AddLiveOut issues FI's created the write way to represent Mips stack by Bruno Cardoso Lopes · 18 years ago
- 75ce010 Assert when TLS is not implemented. by Lauro Ramos Venancio · 18 years ago
- 972f589 Initial Mips support, here we go! =) by Bruno Cardoso Lopes · 18 years ago
