[MIPS] Avoid splitting TB's at page boundary for branch instructions.
If a branch occurred at last word of page, the delay slot instruction
would be in a separate TB in following page. This causes TB invalidation
problems if the branch target is patched, i.e., in JIT code.
Fixes some rare v8 browser and test-suite crashes on qemu for mips.
Change-Id: I62946b7e724f71b880225df0a888614a9e64e3bf
diff --git a/target-mips/translate.c b/target-mips/translate.c
old mode 100644
new mode 100755
index 27a8df7..ebbebc8
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -8357,7 +8357,10 @@
if (env->singlestep_enabled && (ctx.hflags & MIPS_HFLAG_BMASK) == 0)
break;
- if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
+ /* Do not split a branch instruction and its delay slot into two
+ TB's when a page boundary is crossed. This causes TB's to be
+ invalidated incorrectly if branch target is patched. */
+ if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0 && (ctx.hflags & MIPS_HFLAG_BMASK) == 0)
break;
if (gen_opc_ptr >= gen_opc_end)
