commit 970400d98f2cf2313db6dcaf7e0a66e51ae04b88
author The Android Open Source Project <initial-contribution@android.com> Mon May 21 14:28:10 2012 -0700
committer Android Git Automerger <android-git-automerger@android.com> Mon May 21 14:28:10 2012 -0700
tree 351ba8238c80234f198ab8bd3d0f00e6c0741acd
parent d4deed466a5276f711b3f9bd52003ac70bc91285
parent c26e6bc560f7a34e26795c63c0178f88dd493b50

am c26e6bc5: Reconcile with jb-release

* commit 'c26e6bc560f7a34e26795c63c0178f88dd493b50':
  Handle (T1) SMMUL{R}.

main/VEX/priv/guest_arm_toIR.c

diff --git a/main/VEX/priv/guest_arm_toIR.c b/main/VEX/priv/guest_arm_toIR.c
index 4fd47db..d6be839 100644
--- a/main/VEX/priv/guest_arm_toIR.c
+++ b/main/VEX/priv/guest_arm_toIR.c
@@ -15936,6 +15936,29 @@
    vassert(dres.continueAt == 0);
    dres.len = 4;
 
+   /* ------------------- (T1) SMMUL{R} ------------------ */
+   if (INSN0(15,7) == BITS9(1,1,1,1,1,0,1,1,0)
+       && INSN0(6,4) == BITS3(1,0,1)
+       && INSN1(15,12) == BITS4(1,1,1,1)
+       && INSN1(7,5) == BITS3(0,0,0)) {
+      UInt bitR = INSN1(4,4);
+      UInt rD = INSN1(11,8);
+      UInt rM = INSN1(3,0);
+      UInt rN = INSN0(3,0);
+      if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
+        IRExpr* res = newTemp(Ity_I32);
+        assign(res, unop(Iop_64HIto32,
+                binop(Iop_Add64,
+                      binop(Iop_MullS32, getIRegT(rN), getIRegT(rM)),
+                    mkU64(bitR ? 0x80000000ULL : 0ULL))));
+         putIRegT(rD, mkexpr(res), condT);
+         DIP("smmul%s r%u, r%u, r%u\n",
+             bitR ? "r" : "", rD, rN, rM);
+         goto decode_success;
+      }
+   }
+
+
    /* ---------------- BL/BLX simm26 ---------------- */
    if (BITS5(1,1,1,1,0) == INSN0(15,11) && BITS2(1,1) == INSN1(15,14)) {
       UInt isBL = INSN1(12,12);