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/*
* Copyright (C) 2012 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <i2c.h>
#include <netdev.h>
#include <asm/arch/cpu.h>
#include <asm/arch/gpio.h>
#include <asm/arch/dwmmc.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/sromc.h>
#include "setup.h"
unsigned int OmPin;
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SMC911X
static int smc9115_pre_init(void)
{
u32 smc_bw_conf, smc_bc_conf;
int err;
/* Ethernet needs data bus width of 16 bits */
smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK)
| SROMC_BYTE_ENABLE(CONFIG_ENV_SROM_BANK);
smc_bc_conf = SROMC_BC_TACS(0x01) | SROMC_BC_TCOS(0x01)
| SROMC_BC_TACC(0x06) | SROMC_BC_TCOH(0x01)
| SROMC_BC_TAH(0x0C) | SROMC_BC_TACP(0x09)
| SROMC_BC_PMC(0x01);
/* Select and configure the SROMC bank */
err = exynos_pinmux_config(PERIPH_ID_SROMC,
CONFIG_ENV_SROM_BANK | PINMUX_FLAG_16BIT);
if (err) {
debug("SROMC not configured\n");
return err;
}
s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
return 0;
}
#endif
int board_init(void)
{
gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
OmPin = readl(EXYNOS5_POWER_BASE + INFORM3_OFFSET);
printf("\nChecking Boot Mode ...");
if (OmPin == BOOT_MMCSD) {
printf(" SDMMC\n");
} else if (OmPin == BOOT_EMMC_4_4) {
printf(" EMMC4.41\n");
} else {
printf(" Please check OM_pin\n");
}
return 0;
}
int dram_init(void)
{
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
+ get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
+ get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)
+ get_ram_size((long *)PHYS_SDRAM_5, PHYS_SDRAM_7_SIZE)
+ get_ram_size((long *)PHYS_SDRAM_6, PHYS_SDRAM_7_SIZE)
+ get_ram_size((long *)PHYS_SDRAM_7, PHYS_SDRAM_7_SIZE)
+ get_ram_size((long *)PHYS_SDRAM_8, PHYS_SDRAM_8_SIZE);
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE);
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
PHYS_SDRAM_2_SIZE);
gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3,
PHYS_SDRAM_3_SIZE);
gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4,
PHYS_SDRAM_4_SIZE);
gd->bd->bi_dram[4].start = PHYS_SDRAM_5;
gd->bd->bi_dram[4].size = get_ram_size((long *)PHYS_SDRAM_5,
PHYS_SDRAM_5_SIZE);
gd->bd->bi_dram[5].start = PHYS_SDRAM_6;
gd->bd->bi_dram[5].size = get_ram_size((long *)PHYS_SDRAM_6,
PHYS_SDRAM_6_SIZE);
gd->bd->bi_dram[6].start = PHYS_SDRAM_7;
gd->bd->bi_dram[6].size = get_ram_size((long *)PHYS_SDRAM_7,
PHYS_SDRAM_7_SIZE);
gd->bd->bi_dram[7].start = PHYS_SDRAM_8;
gd->bd->bi_dram[7].size = get_ram_size((long *)PHYS_SDRAM_8,
PHYS_SDRAM_8_SIZE);
}
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_SMC911X
if (smc9115_pre_init())
return -1;
return smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
return 0;
}
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
printf("\nBoard: %s\n",CONFIG_IDENT_STRING);
return 0;
}
#endif
#ifdef CONFIG_GENERIC_MMC
int board_mmc_init(bd_t *bis)
{
int err;
err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
if (err) {
debug("SDMMC0 not configured\n");
return err;
}
err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
if (err) {
debug("SDMMC2 not configured\n");
return err;
}
if (OmPin == BOOT_EMMC_4_4) {
err = exynos_dwmmc_init(0, 8);
err = exynos_dwmmc_init(2, 4);
} else {
err = exynos_dwmmc_init(2, 4);
err = exynos_dwmmc_init(0, 8);
}
err = exynos_dwmmc_init(0, 8);
return err;
}
#endif
static int board_uart_init(void)
{
int err;
err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE);
if (err) {
debug("UART0 not configured\n");
return err;
}
err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE);
if (err) {
debug("UART1 not configured\n");
return err;
}
err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE);
if (err) {
debug("UART2 not configured\n");
return err;
}
err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
if (err) {
debug("UART3 not configured\n");
return err;
}
return 0;
}
#ifdef CONFIG_SYS_I2C_INIT_BOARD
static int board_i2c_init(void)
{
int i, err;
for (i = 0; i < CONFIG_MAX_I2C_NUM; i++) {
err = exynos_pinmux_config((PERIPH_ID_I2C0 + i),
PINMUX_FLAG_NONE);
if (err) {
debug("I2C%d not configured\n", (PERIPH_ID_I2C0 + i));
return err;
}
}
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
return 0;
}
#endif
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
int i;
uchar mac[6];
unsigned int guid_high = readl(EXYNOS5_GUID_HIGH);
unsigned int guid_low = readl(EXYNOS5_GUID_LOW);
for (i = 0; i < 2; i++)
mac[i] = (guid_high >> (8 * (1 - i))) & 0xFF;
for (i = 0; i < 4; i++)
mac[i+2] = (guid_low >> (8 * (3 - i))) & 0xFF;
/* mark it as not multicast and outside official 80211 MAC namespace */
mac[0] = (mac[0] & ~0x1) | 0x2;
eth_setenv_enetaddr("ethaddr", mac);
eth_setenv_enetaddr("usbethaddr", mac);
#ifdef CONFIG_PREBOOT
setenv("preboot", CONFIG_PREBOOT);
#endif
}
#endif
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
int err;
err = board_uart_init();
if (err) {
debug("UART init failed\n");
return err;
}
#ifdef CONFIG_SYS_I2C_INIT_BOARD
err = board_i2c_init();
#endif
return err;
}
#endif
void arch_preboot_os(void)
{
/*
* We should now long be done with accessing any peripherals or
* setting up any other hardware state that needs to be set up from
* the secure mode (TrustZone), so we can switch to non-secure mode
* and we rely on board-specific logic to put a board-specific monitor
* in place for stuff like L2 cache maintenance and power management.
*/
enter_ns();
/*
* Enter Hyp mode immediately before booting the kernel to allow
* the first Linux kernel access to and control of Hyp mode so that
* modules like KVM can run VMs.
*
* Without further ado...
*/
enter_hyp();
}