arch/arm/cpu/arm926ejs/mxs/mxs.c - boot/u-boot-linaro-stable - Git at Google

 /*
  * Freescale i.MX28 common code
  *
  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  * on behalf of DENX Software Engineering GmbH
  *
  * Based on code from LTIB:
  * Copyright (C) 2010 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */

 #include <common.h>
 #include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/dma.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/sys_proto.h>

 DECLARE_GLOBAL_DATA_PTR;

 /* 1 second delay should be plenty of time for block reset. */
 #define	RESET_MAX_TIMEOUT	1000000

 #define	MXS_BLOCK_SFTRST	(1 << 31)
 #define	MXS_BLOCK_CLKGATE	(1 << 30)

 /* Lowlevel init isn't used on i.MX28, so just have a dummy here */
 inline void lowlevel_init(void) {}

 void reset_cpu(ulong ignored) __attribute__((noreturn));

 void reset_cpu(ulong ignored)
 {
 	struct mxs_rtc_regs *rtc_regs =
 		(struct mxs_rtc_regs *)MXS_RTC_BASE;
 	struct mxs_lcdif_regs *lcdif_regs =
 		(struct mxs_lcdif_regs *)MXS_LCDIF_BASE;

 	/*
 	 * Shut down the LCD controller as it interferes with BootROM boot mode
 	 * pads sampling.
 	 */
 	writel(LCDIF_CTRL_RUN, &lcdif_regs->hw_lcdif_ctrl_clr);

 	/* Wait 1 uS before doing the actual watchdog reset */
 	writel(1, &rtc_regs->hw_rtc_watchdog);
 	writel(RTC_CTRL_WATCHDOGEN, &rtc_regs->hw_rtc_ctrl_set);

 	/* Endless loop, reset will exit from here */
 	for (;;)
 		;
 }

 void enable_caches(void)
 {
 #ifndef CONFIG_SYS_ICACHE_OFF
 	icache_enable();
 #endif
 #ifndef CONFIG_SYS_DCACHE_OFF
 	dcache_enable();
 #endif
 }

 int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned
 								int timeout)
 {
 	while (--timeout) {
 		if ((readl(&reg->reg) & mask) == mask)
 			break;
 		udelay(1);
 	}

 	return !timeout;
 }

 int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned
 								int timeout)
 {
 	while (--timeout) {
 		if ((readl(&reg->reg) & mask) == 0)
 			break;
 		udelay(1);
 	}

 	return !timeout;
 }

 int mxs_reset_block(struct mxs_register_32 *reg)
 {
 	/* Clear SFTRST */
 	writel(MXS_BLOCK_SFTRST, &reg->reg_clr);

 	if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
 		return 1;

 	/* Clear CLKGATE */
 	writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);

 	/* Set SFTRST */
 	writel(MXS_BLOCK_SFTRST, &reg->reg_set);

 	/* Wait for CLKGATE being set */
 	if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
 		return 1;

 	/* Clear SFTRST */
 	writel(MXS_BLOCK_SFTRST, &reg->reg_clr);

 	if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
 		return 1;

 	/* Clear CLKGATE */
 	writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);

 	if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
 		return 1;

 	return 0;
 }

 void mx28_fixup_vt(uint32_t start_addr)
 {
 	uint32_t *vt = (uint32_t *)0x20;
 	int i;

 	for (i = 0; i < 8; i++)
 		vt[i] = start_addr + (4 * i);
 }

 #ifdef	CONFIG_ARCH_MISC_INIT
 int arch_misc_init(void)
 {
 	mx28_fixup_vt(gd->relocaddr);
 	return 0;
 }
 #endif

 int arch_cpu_init(void)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 	extern uint32_t _start;

 	mx28_fixup_vt((uint32_t)&_start);

 	/*
 	 * Enable NAND clock
 	 */
 	/* Clear bypass bit */
 	writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
 		&clkctrl_regs->hw_clkctrl_clkseq_set);

 	/* Set GPMI clock to ref_gpmi / 12 */
 	clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi,
 		CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1);

 	udelay(1000);

 	/*
 	 * Configure GPIO unit
 	 */
 	mxs_gpio_init();

 #ifdef	CONFIG_APBH_DMA
 	/* Start APBH DMA */
 	mxs_dma_init();
 #endif

 	return 0;
 }

 #if defined(CONFIG_DISPLAY_CPUINFO)
 static const char *get_cpu_type(void)
 {
 	struct mxs_digctl_regs *digctl_regs =
 		(struct mxs_digctl_regs *)MXS_DIGCTL_BASE;

 	switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
 	case HW_DIGCTL_CHIPID_MX28:
 		return "28";
 	default:
 		return "??";
 	}
 }

 static const char *get_cpu_rev(void)
 {
 	struct mxs_digctl_regs *digctl_regs =
 		(struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
 	uint8_t rev = readl(&digctl_regs->hw_digctl_chipid) & 0x000000FF;

 	switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
 	case HW_DIGCTL_CHIPID_MX28:
 		switch (rev) {
 		case 0x1:
 			return "1.2";
 		default:
 			return "??";
 		}
 	default:
 		return "??";
 	}
 }

 int print_cpuinfo(void)
 {
 	struct mxs_spl_data *data = (struct mxs_spl_data *)
 		((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);

 	printf("CPU:   Freescale i.MX%s rev%s at %d MHz\n",
 		get_cpu_type(),
 		get_cpu_rev(),
 		mxc_get_clock(MXC_ARM_CLK) / 1000000);
 	printf("BOOT:  %s\n", mxs_boot_modes[data->boot_mode_idx].mode);
 	return 0;
 }
 #endif

 int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 {
 	printf("CPU:   %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
 	printf("BUS:   %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000);
 	printf("EMI:   %3d MHz\n", mxc_get_clock(MXC_EMI_CLK));
 	printf("GPMI:  %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK) / 1000000);
 	return 0;
 }

 /*
  * Initializes on-chip ethernet controllers.
  */
 #if defined(CONFIG_MX28) && defined(CONFIG_CMD_NET)
 int cpu_eth_init(bd_t *bis)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;

 	/* Turn on ENET clocks */
 	clrbits_le32(&clkctrl_regs->hw_clkctrl_enet,
 		CLKCTRL_ENET_SLEEP | CLKCTRL_ENET_DISABLE);

 	/* Set up ENET PLL for 50 MHz */
 	/* Power on ENET PLL */
 	writel(CLKCTRL_PLL2CTRL0_POWER,
 		&clkctrl_regs->hw_clkctrl_pll2ctrl0_set);

 	udelay(10);

 	/* Gate on ENET PLL */
 	writel(CLKCTRL_PLL2CTRL0_CLKGATE,
 		&clkctrl_regs->hw_clkctrl_pll2ctrl0_clr);

 	/* Enable pad output */
 	setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN);

 	return 0;
 }
 #endif

 static void __mx28_adjust_mac(int dev_id, unsigned char *mac)
 {
 	mac[0] = 0x00;
 	mac[1] = 0x04; /* Use FSL vendor MAC address by default */

 	if (dev_id == 1) /* Let MAC1 be MAC0 + 1 by default */
 		mac[5] += 1;
 }

 void mx28_adjust_mac(int dev_id, unsigned char *mac)
 	__attribute__((weak, alias("__mx28_adjust_mac")));

 #ifdef	CONFIG_MX28_FEC_MAC_IN_OCOTP

 #define	MXS_OCOTP_MAX_TIMEOUT	1000000
 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 {
 	struct mxs_ocotp_regs *ocotp_regs =
 		(struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
 	uint32_t data;

 	memset(mac, 0, 6);

 	writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);

 	if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
 				MXS_OCOTP_MAX_TIMEOUT)) {
 		printf("MXS FEC: Can't get MAC from OCOTP\n");
 		return;
 	}

 	data = readl(&ocotp_regs->hw_ocotp_cust0);

 	mac[2] = (data >> 24) & 0xff;
 	mac[3] = (data >> 16) & 0xff;
 	mac[4] = (data >> 8) & 0xff;
 	mac[5] = data & 0xff;
 	mx28_adjust_mac(dev_id, mac);
 }
 #else
 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 {
 	memset(mac, 0, 6);
 }
 #endif

 int mxs_dram_init(void)
 {
 	struct mxs_spl_data *data = (struct mxs_spl_data *)
 		((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);

 	if (data->mem_dram_size == 0) {
 		printf("MXS:\n"
 			"Error, the RAM size passed up from SPL is 0!\n");
 		hang();
 	}

 	gd->ram_size = data->mem_dram_size;
 	return 0;
 }

 U_BOOT_CMD(
 	clocks,	CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks,
 	"display clocks",
 	""
 );
	/*
	* Freescale i.MX28 common code
	*
	* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
	* on behalf of DENX Software Engineering GmbH
	*
	* Based on code from LTIB:
	* Copyright (C) 2010 Freescale Semiconductor, Inc.
	*
	* See file CREDITS for list of people who contributed to this
	* project.
	*
	* This program is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License as
	* published by the Free Software Foundation; either version 2 of
	* the License, or (at your option) any later version.
	*
	* This program is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* You should have received a copy of the GNU General Public License
	* along with this program; if not, write to the Free Software
	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	* MA 02111-1307 USA
	*/

	#include <common.h>
	#include <asm/errno.h>
	#include <asm/io.h>
	#include <asm/arch/clock.h>
	#include <asm/arch/dma.h>
	#include <asm/arch/gpio.h>
	#include <asm/arch/iomux.h>
	#include <asm/arch/imx-regs.h>
	#include <asm/arch/sys_proto.h>

	DECLARE_GLOBAL_DATA_PTR;

	/* 1 second delay should be plenty of time for block reset. */
	#define RESET_MAX_TIMEOUT 1000000

	#define MXS_BLOCK_SFTRST (1 << 31)
	#define MXS_BLOCK_CLKGATE (1 << 30)

	/* Lowlevel init isn't used on i.MX28, so just have a dummy here */
	inline void lowlevel_init(void) {}

	void reset_cpu(ulong ignored) __attribute__((noreturn));

	void reset_cpu(ulong ignored)
	{
	struct mxs_rtc_regs *rtc_regs =
	(struct mxs_rtc_regs *)MXS_RTC_BASE;
	struct mxs_lcdif_regs *lcdif_regs =
	(struct mxs_lcdif_regs *)MXS_LCDIF_BASE;

	/*
	* Shut down the LCD controller as it interferes with BootROM boot mode
	* pads sampling.
	*/
	writel(LCDIF_CTRL_RUN, &lcdif_regs->hw_lcdif_ctrl_clr);

	/* Wait 1 uS before doing the actual watchdog reset */
	writel(1, &rtc_regs->hw_rtc_watchdog);
	writel(RTC_CTRL_WATCHDOGEN, &rtc_regs->hw_rtc_ctrl_set);

	/* Endless loop, reset will exit from here */
	for (;;)
	;
	}

	void enable_caches(void)
	{
	#ifndef CONFIG_SYS_ICACHE_OFF
	icache_enable();
	#endif
	#ifndef CONFIG_SYS_DCACHE_OFF
	dcache_enable();
	#endif
	}

	int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned
	int timeout)
	{
	while (--timeout) {
	if ((readl(&reg->reg) & mask) == mask)
	break;
	udelay(1);
	}

	return !timeout;
	}

	int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned
	int timeout)
	{
	while (--timeout) {
	if ((readl(&reg->reg) & mask) == 0)
	break;
	udelay(1);
	}

	return !timeout;
	}

	int mxs_reset_block(struct mxs_register_32 *reg)
	{
	/* Clear SFTRST */
	writel(MXS_BLOCK_SFTRST, &reg->reg_clr);

	if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
	return 1;

	/* Clear CLKGATE */
	writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);

	/* Set SFTRST */
	writel(MXS_BLOCK_SFTRST, &reg->reg_set);

	/* Wait for CLKGATE being set */
	if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
	return 1;

	/* Clear SFTRST */
	writel(MXS_BLOCK_SFTRST, &reg->reg_clr);

	if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
	return 1;

	/* Clear CLKGATE */
	writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);

	if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
	return 1;

	return 0;
	}

	void mx28_fixup_vt(uint32_t start_addr)
	{
	uint32_t vt = (uint32_t )0x20;
	int i;

	for (i = 0; i < 8; i++)
	vt[i] = start_addr + (4 * i);
	}

	#ifdef CONFIG_ARCH_MISC_INIT
	int arch_misc_init(void)
	{
	mx28_fixup_vt(gd->relocaddr);
	return 0;
	}
	#endif

	int arch_cpu_init(void)
	{
	struct mxs_clkctrl_regs *clkctrl_regs =
	(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
	extern uint32_t _start;

	mx28_fixup_vt((uint32_t)&_start);

	/*
	* Enable NAND clock
	*/
	/* Clear bypass bit */
	writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
	&clkctrl_regs->hw_clkctrl_clkseq_set);

	/* Set GPMI clock to ref_gpmi / 12 */
	clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi,
	CLKCTRL_GPMI_CLKGATE \| CLKCTRL_GPMI_DIV_MASK, 1);

	udelay(1000);

	/*
	* Configure GPIO unit
	*/
	mxs_gpio_init();

	#ifdef CONFIG_APBH_DMA
	/* Start APBH DMA */
	mxs_dma_init();
	#endif

	return 0;
	}

	#if defined(CONFIG_DISPLAY_CPUINFO)
	static const char *get_cpu_type(void)
	{
	struct mxs_digctl_regs *digctl_regs =
	(struct mxs_digctl_regs *)MXS_DIGCTL_BASE;

	switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
	case HW_DIGCTL_CHIPID_MX28:
	return "28";
	default:
	return "??";
	}
	}

	static const char *get_cpu_rev(void)
	{
	struct mxs_digctl_regs *digctl_regs =
	(struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
	uint8_t rev = readl(&digctl_regs->hw_digctl_chipid) & 0x000000FF;

	switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
	case HW_DIGCTL_CHIPID_MX28:
	switch (rev) {
	case 0x1:
	return "1.2";
	default:
	return "??";
	}
	default:
	return "??";
	}
	}

	int print_cpuinfo(void)
	{
	struct mxs_spl_data data = (struct mxs_spl_data )
	((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);

	printf("CPU: Freescale i.MX%s rev%s at %d MHz\n",
	get_cpu_type(),
	get_cpu_rev(),
	mxc_get_clock(MXC_ARM_CLK) / 1000000);
	printf("BOOT: %s\n", mxs_boot_modes[data->boot_mode_idx].mode);
	return 0;
	}
	#endif

	int do_mx28_showclocks(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
	{
	printf("CPU: %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
	printf("BUS: %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000);
	printf("EMI: %3d MHz\n", mxc_get_clock(MXC_EMI_CLK));
	printf("GPMI: %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK) / 1000000);
	return 0;
	}

	/*
	* Initializes on-chip ethernet controllers.
	*/
	#if defined(CONFIG_MX28) && defined(CONFIG_CMD_NET)
	int cpu_eth_init(bd_t *bis)
	{
	struct mxs_clkctrl_regs *clkctrl_regs =
	(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;

	/* Turn on ENET clocks */
	clrbits_le32(&clkctrl_regs->hw_clkctrl_enet,
	CLKCTRL_ENET_SLEEP \| CLKCTRL_ENET_DISABLE);

	/* Set up ENET PLL for 50 MHz */
	/* Power on ENET PLL */
	writel(CLKCTRL_PLL2CTRL0_POWER,
	&clkctrl_regs->hw_clkctrl_pll2ctrl0_set);

	udelay(10);

	/* Gate on ENET PLL */
	writel(CLKCTRL_PLL2CTRL0_CLKGATE,
	&clkctrl_regs->hw_clkctrl_pll2ctrl0_clr);

	/* Enable pad output */
	setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN);

	return 0;
	}
	#endif

	static void __mx28_adjust_mac(int dev_id, unsigned char *mac)
	{
	mac[0] = 0x00;
	mac[1] = 0x04; /* Use FSL vendor MAC address by default */

	if (dev_id == 1) /* Let MAC1 be MAC0 + 1 by default */
	mac[5] += 1;
	}

	void mx28_adjust_mac(int dev_id, unsigned char *mac)
	__attribute__((weak, alias("__mx28_adjust_mac")));

	#ifdef CONFIG_MX28_FEC_MAC_IN_OCOTP

	#define MXS_OCOTP_MAX_TIMEOUT 1000000
	void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
	{
	struct mxs_ocotp_regs *ocotp_regs =
	(struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
	uint32_t data;

	memset(mac, 0, 6);

	writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);

	if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
	MXS_OCOTP_MAX_TIMEOUT)) {
	printf("MXS FEC: Can't get MAC from OCOTP\n");
	return;
	}

	data = readl(&ocotp_regs->hw_ocotp_cust0);

	mac[2] = (data >> 24) & 0xff;
	mac[3] = (data >> 16) & 0xff;
	mac[4] = (data >> 8) & 0xff;
	mac[5] = data & 0xff;
	mx28_adjust_mac(dev_id, mac);
	}
	#else
	void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
	{
	memset(mac, 0, 6);
	}
	#endif

	int mxs_dram_init(void)
	{
	struct mxs_spl_data data = (struct mxs_spl_data )
	((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);

	if (data->mem_dram_size == 0) {
	printf("MXS:\n"
	"Error, the RAM size passed up from SPL is 0!\n");
	hang();
	}

	gd->ram_size = data->mem_dram_size;
	return 0;
	}

	U_BOOT_CMD(
	clocks, CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks,
	"display clocks",
	""
	);