| #ifndef __LINUX_MFD_TIMPANI_AUDIO_H |
| #define __LINUX_MFD_TIMPANI_AUDIO_H |
| |
| /* |
| * MREF |
| */ |
| #define TIMPANI_A_MREF (0x3) |
| #define TIMPANI_MREF_RWC "RW" |
| #define TIMPANI_MREF_POR 0xe2 |
| #define TIMPANI_MREF_S 0 |
| #define TIMPANI_MREF_M 0xFF |
| |
| #define TIMPANI_MREF_MREF_BG_EN_S 7 |
| #define TIMPANI_MREF_MREF_BG_EN_M 0x80 |
| #define TIMPANI_MREF_MREF_BG_EN_ENABLE 0x0 |
| #define TIMPANI_MREF_MREF_BG_EN_DISABLE 0x1 |
| |
| #define TIMPANI_MREF_MREF_BG_REF_CUR_EN_S 6 |
| #define TIMPANI_MREF_MREF_BG_REF_CUR_EN_M 0x40 |
| #define TIMPANI_MREF_MREF_BG_REF_CUR_EN_ENABLE_NORMAL_OP 0x0 |
| #define TIMPANI_MREF_MREF_BG_REF_CUR_EN_DISABLE 0x1 |
| |
| #define TIMPANI_MREF_MREF_200K_MODE_EN_S 5 |
| #define TIMPANI_MREF_MREF_200K_MODE_EN_M 0x20 |
| #define TIMPANI_MREF_MREF_200K_MODE_EN_ENABLE 0x0 |
| #define TIMPANI_MREF_MREF_200K_MODE_EN_DISABLE 0x1 |
| |
| #define TIMPANI_MREF_MREF_PRE_CHARGE_EN_S 4 |
| #define TIMPANI_MREF_MREF_PRE_CHARGE_EN_M 0x10 |
| #define TIMPANI_MREF_MREF_PRE_CHARGE_EN_DISABLE 0x0 |
| #define TIMPANI_MREF_MREF_PRE_CHARGE_EN_ENABLE 0x1 |
| |
| #define TIMPANI_MREF_MREF_100UA_CUR_CONN_S 3 |
| #define TIMPANI_MREF_MREF_100UA_CUR_CONN_M 0x8 |
| #define TIMPANI_MREF_MREF_100UA_CUR_CONN_ON_CHIP_RESISTOR_NORMAL_OP 0x0 |
| #define TIMPANI_MREF_MREF_100UA_CUR_CONN_ATEST 0x1 |
| |
| #define TIMPANI_MREF_MREF_PTAT_CURRENT_S 2 |
| #define TIMPANI_MREF_MREF_PTAT_CURRENT_M 0x4 |
| #define TIMPANI_MREF_MREF_PTAT_CURRENT_V_10UA_PTAT_NORMAL_OP 0x0 |
| #define TIMPANI_MREF_MREF_PTAT_CURRENT_V_5UA_PTAT_BIAS_CURRENT 0x1 |
| |
| #define TIMPANI_MREF_MREF_400K_MODE_EN_S 1 |
| #define TIMPANI_MREF_MREF_400K_MODE_EN_M 0x2 |
| #define TIMPANI_MREF_MREF_400K_MODE_EN_ENABLE 0x0 |
| #define TIMPANI_MREF_MREF_400K_MODE_EN_DISABLE 0x1 |
| |
| #define TIMPANI_MREF_RESERVED_S 0 |
| #define TIMPANI_MREF_RESERVED_M 0x1 |
| |
| |
| /* For CDAC_IDAC_REF_CUR */ |
| #define TIMPANI_A_CDAC_IDAC_REF_CUR (0x4) |
| #define TIMPANI_CDAC_IDAC_REF_CUR_RWC "RW" |
| #define TIMPANI_CDAC_IDAC_REF_CUR_POR 0x8c |
| #define TIMPANI_CDAC_IDAC_REF_CUR_S 0 |
| #define TIMPANI_CDAC_IDAC_REF_CUR_M 0xFF |
| |
| |
| #define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_S 5 |
| #define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_M 0xE0 |
| #define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_4UA 0x0 |
| #define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_6UA 0x1 |
| #define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_8UA 0x2 |
| #define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_9UA 0x3 |
| #define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_10UA_NORMAL_OP 0x4 |
| #define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_11UA 0x5 |
| #define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_13UA 0x6 |
| #define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_15UA 0x7 |
| |
| #define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_S 2 |
| #define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_M 0x1C |
| #define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_8_5UA 0x0 |
| #define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_9_0UA 0x1 |
| #define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_9_5UA 0x2 |
| #define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_10_0UA_NORMAL_OP 0x3 |
| #define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_10_5UA 0x4 |
| #define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_11_0UA 0x5 |
| #define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_11_5UA 0x6 |
| #define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_12_0UA 0x7 |
| |
| #define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_S 0 |
| #define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_M 0x3 |
| #define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_2UA 0x0 |
| #define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_3UA 0x1 |
| #define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_5UA_NORMAL_OP 0x2 |
| #define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_8UA 0x3 |
| |
| |
| /* -- For TXADC12_REF_CURR */ |
| #define TIMPANI_A_TXADC12_REF_CURR (0x5) |
| #define TIMPANI_TXADC12_REF_CURR_RWC "RW" |
| #define TIMPANI_TXADC12_REF_CURR_POR 0xa0 |
| #define TIMPANI_TXADC12_REF_CURR_S 0 |
| #define TIMPANI_TXADC12_REF_CURR_M 0xFF |
| |
| |
| #define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_S 6 |
| #define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_M 0xC0 |
| #define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_50UA 0x0 |
| #define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_45UA 0x1 |
| #define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_40UA_NORMAL_OP 0x2 |
| #define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_35UA 0x3 |
| |
| #define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_S 4 |
| #define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_M 0x30 |
| #define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_50UA 0x0 |
| #define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_45UA 0x1 |
| #define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_40UA_NORMAL_OP 0x2 |
| #define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_35UA 0x3 |
| |
| #define TIMPANI_TXADC12_REF_CURR_RESERVED_S 0 |
| #define TIMPANI_TXADC12_REF_CURR_RESERVED_M 0xF |
| |
| |
| /* -- For TXADC3_EN */ |
| #define TIMPANI_A_TXADC3_EN (0x9) |
| #define TIMPANI_TXADC3_EN_RWC "RW" |
| #define TIMPANI_TXADC3_EN_POR 0 |
| #define TIMPANI_TXADC3_EN_S 0 |
| #define TIMPANI_TXADC3_EN_M 0xFF |
| |
| |
| #define TIMPANI_TXADC3_EN_TXADC3_REF_EN_S 7 |
| #define TIMPANI_TXADC3_EN_TXADC3_REF_EN_M 0x80 |
| #define TIMPANI_TXADC3_EN_TXADC3_REF_EN_DISABLE 0x0 |
| #define TIMPANI_TXADC3_EN_TXADC3_REF_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXADC3_EN_TXADC3_DAC_REF_CUR_COMPENSATION_EN_S 6 |
| #define TIMPANI_TXADC3_EN_TXADC3_DAC_REF_CUR_COMPENSATION_EN_M 0x40 |
| #define TIMPANI_TXADC3_EN_TXADC3_DAC_REF_CUR_COMPENSATION_EN_DISABLE 0x0 |
| #define TIMPANI_TXADC3_EN_TXADC3_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_S 5 |
| #define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_M 0x20 |
| #define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_DISABLE 0x0 |
| #define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXADC3_EN_TXADC3_OTA2_EN_S 4 |
| #define TIMPANI_TXADC3_EN_TXADC3_OTA2_EN_M 0x10 |
| #define TIMPANI_TXADC3_EN_TXADC3_OTA2_EN_DISABLE 0x0 |
| #define TIMPANI_TXADC3_EN_TXADC3_OTA2_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_S 3 |
| #define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_M 0x8 |
| #define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_DISABLE 0x0 |
| #define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_S 2 |
| #define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_M 0x4 |
| #define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_DISABLE 0x0 |
| #define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_S 1 |
| #define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_M 0x2 |
| #define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_DISABLE 0x0 |
| #define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXADC3_EN_RESERVED_S 0 |
| #define TIMPANI_TXADC3_EN_RESERVED_M 0x1 |
| |
| |
| /* -- For TXADC4_EN */ |
| #define TIMPANI_A_TXADC4_EN (0xA) |
| #define TIMPANI_TXADC4_EN_RWC "RW" |
| #define TIMPANI_TXADC4_EN_POR 0 |
| #define TIMPANI_TXADC4_EN_S 0 |
| #define TIMPANI_TXADC4_EN_M 0xFF |
| |
| |
| #define TIMPANI_TXADC4_EN_TXADC4_REF_EN_S 7 |
| #define TIMPANI_TXADC4_EN_TXADC4_REF_EN_M 0x80 |
| #define TIMPANI_TXADC4_EN_TXADC4_REF_EN_DISABLE 0x0 |
| #define TIMPANI_TXADC4_EN_TXADC4_REF_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXADC4_EN_TXADC4_DAC_REF_CUR_COMPENSATION_EN_S 6 |
| #define TIMPANI_TXADC4_EN_TXADC4_DAC_REF_CUR_COMPENSATION_EN_M 0x40 |
| #define TIMPANI_TXADC4_EN_TXADC4_DAC_REF_CUR_COMPENSATION_EN_DISABLE 0x0 |
| #define TIMPANI_TXADC4_EN_TXADC4_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_S 5 |
| #define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_M 0x20 |
| #define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_DISABLE 0x0 |
| #define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXADC4_EN_TXADC4_OTA2_EN_S 4 |
| #define TIMPANI_TXADC4_EN_TXADC4_OTA2_EN_M 0x10 |
| #define TIMPANI_TXADC4_EN_TXADC4_OTA2_EN_DISABLE 0x0 |
| #define TIMPANI_TXADC4_EN_TXADC4_OTA2_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_S 3 |
| #define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_M 0x8 |
| #define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_DISABLE 0x0 |
| #define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_S 2 |
| #define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_M 0x4 |
| #define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_DISABLE 0x0 |
| #define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_S 1 |
| #define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_M 0x2 |
| #define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_DISABLE 0x0 |
| #define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXADC4_EN_RESERVED_S 0 |
| #define TIMPANI_TXADC4_EN_RESERVED_M 0x1 |
| |
| |
| /* -- For CODEC_TXADC_STATUS_REGISTER_1 */ |
| #define TIMPANI_A_CODEC_TXADC_STATUS_REGISTER_1 (0xB) |
| #define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_RWC "R" |
| #define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_POR 0 |
| #define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_S 0 |
| #define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_M 0xFF |
| |
| |
| #define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC1_DEM_ERROR_S 7 |
| #define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC1_DEM_ERROR_M 0x80 |
| |
| #define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC2_DEM_ERROR_S 6 |
| #define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC2_DEM_ERROR_M 0x40 |
| |
| #define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC3_DEM_ERROR_S 5 |
| #define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC3_DEM_ERROR_M 0x20 |
| |
| #define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC4_DEM_ERROR_S 4 |
| #define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC4_DEM_ERROR_M 0x10 |
| |
| #define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_RESERVED_S 0 |
| #define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_RESERVED_M 0xF |
| |
| |
| /* -- For TXFE1 */ |
| #define TIMPANI_A_TXFE1 (0xD) |
| #define TIMPANI_TXFE1_RWC "RW" |
| #define TIMPANI_TXFE1_POR 0 |
| #define TIMPANI_TXFE1_S 0 |
| #define TIMPANI_TXFE1_M 0xFF |
| |
| |
| #define TIMPANI_TXFE1_TXFE1_EN_S 7 |
| #define TIMPANI_TXFE1_TXFE1_EN_M 0x80 |
| #define TIMPANI_TXFE1_TXFE1_EN_DISABLE 0x0 |
| #define TIMPANI_TXFE1_TXFE1_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXFE1_TXFE1_GAIN_S 5 |
| #define TIMPANI_TXFE1_TXFE1_GAIN_M 0x60 |
| #define TIMPANI_TXFE1_TXFE1_GAIN_V_0DB 0x0 |
| #define TIMPANI_TXFE1_TXFE1_GAIN_V_4_5DB 0x1 |
| #define TIMPANI_TXFE1_TXFE1_GAIN_V_24DB_1 0x2 |
| #define TIMPANI_TXFE1_TXFE1_GAIN_V_24DB_2 0x3 |
| |
| #define TIMPANI_TXFE1_TXFE1_IN_MIC1_CONN_S 4 |
| #define TIMPANI_TXFE1_TXFE1_IN_MIC1_CONN_M 0x10 |
| #define TIMPANI_TXFE1_TXFE1_IN_MIC1_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_TXFE1_TXFE1_IN_MIC1_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_S 3 |
| #define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_M 0x8 |
| #define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_S 2 |
| #define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_M 0x4 |
| #define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_S 1 |
| #define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_M 0x2 |
| #define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_S 0 |
| #define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_M 0x1 |
| #define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_CONNECT 0x1 |
| |
| |
| /* -- For TXFE2 */ |
| #define TIMPANI_A_TXFE2 (0xE) |
| #define TIMPANI_TXFE2_RWC "RW" |
| #define TIMPANI_TXFE2_POR 0 |
| #define TIMPANI_TXFE2_S 0 |
| #define TIMPANI_TXFE2_M 0xFF |
| |
| |
| #define TIMPANI_TXFE2_TXFE2_EN_S 7 |
| #define TIMPANI_TXFE2_TXFE2_EN_M 0x80 |
| #define TIMPANI_TXFE2_TXFE2_EN_DISABLE 0x0 |
| #define TIMPANI_TXFE2_TXFE2_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXFE2_TXFE2_GAIN_S 5 |
| #define TIMPANI_TXFE2_TXFE2_GAIN_M 0x60 |
| #define TIMPANI_TXFE2_TXFE2_GAIN_V_0DB 0x0 |
| #define TIMPANI_TXFE2_TXFE2_GAIN_V_4_5DB 0x1 |
| #define TIMPANI_TXFE2_TXFE2_GAIN_V_24DB_1 0x2 |
| #define TIMPANI_TXFE2_TXFE2_GAIN_V_24DB_2 0x3 |
| |
| #define TIMPANI_TXFE2_TXFE2_IN_MIC1_CONN_S 4 |
| #define TIMPANI_TXFE2_TXFE2_IN_MIC1_CONN_M 0x10 |
| #define TIMPANI_TXFE2_TXFE2_IN_MIC1_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_TXFE2_TXFE2_IN_MIC1_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_S 3 |
| #define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_M 0x8 |
| #define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_S 2 |
| #define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_M 0x4 |
| #define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_S 1 |
| #define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_M 0x2 |
| #define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_S 0 |
| #define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_M 0x1 |
| #define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_CONNECT 0x1 |
| |
| |
| /* -- For TXFE12_ATEST */ |
| #define TIMPANI_A_TXFE12_ATEST (0xF) |
| #define TIMPANI_TXFE12_ATEST_RWC "RW" |
| #define TIMPANI_TXFE12_ATEST_POR 0 |
| #define TIMPANI_TXFE12_ATEST_S 0 |
| #define TIMPANI_TXFE12_ATEST_M 0xFF |
| |
| |
| #define TIMPANI_TXFE12_ATEST_TXFE1_OUT_SHORT_TO_VICM_EN_S 7 |
| #define TIMPANI_TXFE12_ATEST_TXFE1_OUT_SHORT_TO_VICM_EN_M 0x80 |
| #define TIMPANI_TXFE12_ATEST_TXFE1_OUT_SHORT_TO_VICM_EN_DISABLE 0x0 |
| #define TIMPANI_TXFE12_ATEST_TXFE1_OUT_SHORT_TO_VICM_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXFE12_ATEST_TXFE1_BYPASS_EN_S 6 |
| #define TIMPANI_TXFE12_ATEST_TXFE1_BYPASS_EN_M 0x40 |
| #define TIMPANI_TXFE12_ATEST_TXFE1_BYPASS_EN_DISABLE 0x0 |
| #define TIMPANI_TXFE12_ATEST_TXFE1_BYPASS_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_S 5 |
| #define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_M 0x20 |
| #define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_TXFE12_ATEST_TXFE1_OUT_ATEST_CONN_S 4 |
| #define TIMPANI_TXFE12_ATEST_TXFE1_OUT_ATEST_CONN_M 0x10 |
| #define TIMPANI_TXFE12_ATEST_TXFE1_OUT_ATEST_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_TXFE12_ATEST_TXFE1_OUT_ATEST_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_S 3 |
| #define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_M 0x8 |
| #define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_DISABLE 0x0 |
| #define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_S 2 |
| #define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_M 0x4 |
| #define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_DISABLE 0x0 |
| #define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_S 1 |
| #define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_M 0x2 |
| #define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_S 0 |
| #define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_M 0x1 |
| #define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_CONNECT 0x1 |
| |
| |
| /* -- For TXFE_CLT */ |
| #define TIMPANI_A_TXFE_CLT (0x10) |
| #define TIMPANI_TXFE_CLT_RWC "RW" |
| #define TIMPANI_TXFE_CLT_POR 0x68 |
| #define TIMPANI_TXFE_CLT_S 0 |
| #define TIMPANI_TXFE_CLT_M 0xFF |
| |
| |
| #define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_S 5 |
| #define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_M 0xE0 |
| #define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_125V 0x0 |
| #define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_100V 0x1 |
| #define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_075V 0x2 |
| #define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_050V_NORMAL_OP 0x3 |
| #define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_025V 0x4 |
| #define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_000V 0x5 |
| #define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_0_975V 0x6 |
| #define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_0_950V 0x7 |
| |
| #define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_S 3 |
| #define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_M 0x18 |
| #define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_3UA 0x0 |
| #define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_4UA_NORMAL_OP 0x1 |
| #define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_6UA 0x2 |
| #define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_8UA 0x3 |
| |
| #define TIMPANI_TXFE_CLT_RESERVED_S 0 |
| #define TIMPANI_TXFE_CLT_RESERVED_M 0x7 |
| |
| |
| /* -- For TXADC1_EN */ |
| #define TIMPANI_A_TXADC1_EN (0x11) |
| #define TIMPANI_TXADC1_EN_RWC "RW" |
| #define TIMPANI_TXADC1_EN_POR 0 |
| #define TIMPANI_TXADC1_EN_S 0 |
| #define TIMPANI_TXADC1_EN_M 0xFF |
| |
| |
| #define TIMPANI_TXADC1_EN_TXADC1_REF_EN_S 7 |
| #define TIMPANI_TXADC1_EN_TXADC1_REF_EN_M 0x80 |
| #define TIMPANI_TXADC1_EN_TXADC1_REF_EN_DISABLE 0x0 |
| #define TIMPANI_TXADC1_EN_TXADC1_REF_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXADC1_EN_TXADC1_DAC_REF_CUR_COMPENSATION_EN_S 6 |
| #define TIMPANI_TXADC1_EN_TXADC1_DAC_REF_CUR_COMPENSATION_EN_M 0x40 |
| #define TIMPANI_TXADC1_EN_TXADC1_DAC_REF_CUR_COMPENSATION_EN_DISABLE 0x0 |
| #define TIMPANI_TXADC1_EN_TXADC1_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_S 5 |
| #define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_M 0x20 |
| #define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_DISABLE 0x0 |
| #define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXADC1_EN_TXADC1_OTA2_EN_S 4 |
| #define TIMPANI_TXADC1_EN_TXADC1_OTA2_EN_M 0x10 |
| #define TIMPANI_TXADC1_EN_TXADC1_OTA2_EN_DISABLE 0x0 |
| #define TIMPANI_TXADC1_EN_TXADC1_OTA2_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_S 3 |
| #define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_M 0x8 |
| #define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_DISABLE 0x0 |
| #define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_S 2 |
| #define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_M 0x4 |
| #define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_DISABLE 0x0 |
| #define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_S 1 |
| #define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_M 0x2 |
| #define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_DISABLE 0x0 |
| #define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXADC1_EN_RESERVED_S 0 |
| #define TIMPANI_TXADC1_EN_RESERVED_M 0x1 |
| |
| |
| /* -- For TXADC2_EN */ |
| #define TIMPANI_A_TXADC2_EN (0x12) |
| #define TIMPANI_TXADC2_EN_RWC "RW" |
| #define TIMPANI_TXADC2_EN_POR 0 |
| #define TIMPANI_TXADC2_EN_S 0 |
| #define TIMPANI_TXADC2_EN_M 0xFF |
| |
| |
| #define TIMPANI_TXADC2_EN_TXADC2_REF_EN_S 7 |
| #define TIMPANI_TXADC2_EN_TXADC2_REF_EN_M 0x80 |
| #define TIMPANI_TXADC2_EN_TXADC2_REF_EN_DISABLE 0x0 |
| #define TIMPANI_TXADC2_EN_TXADC2_REF_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXADC2_EN_TXADC2_DAC_REF_CUR_COMPENSATION_EN_S 6 |
| #define TIMPANI_TXADC2_EN_TXADC2_DAC_REF_CUR_COMPENSATION_EN_M 0x40 |
| #define TIMPANI_TXADC2_EN_TXADC2_DAC_REF_CUR_COMPENSATION_EN_DISABLE 0x0 |
| #define TIMPANI_TXADC2_EN_TXADC2_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_S 5 |
| #define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_M 0x20 |
| #define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_DISABLE 0x0 |
| #define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXADC2_EN_TXADC2_OTA2_EN_S 4 |
| #define TIMPANI_TXADC2_EN_TXADC2_OTA2_EN_M 0x10 |
| #define TIMPANI_TXADC2_EN_TXADC2_OTA2_EN_DISABLE 0x0 |
| #define TIMPANI_TXADC2_EN_TXADC2_OTA2_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_S 3 |
| #define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_M 0x8 |
| #define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_DISABLE 0x0 |
| #define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_S 2 |
| #define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_M 0x4 |
| #define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_DISABLE 0x0 |
| #define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_S 1 |
| #define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_M 0x2 |
| #define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_DISABLE 0x0 |
| #define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXADC2_EN_RESERVED_S 0 |
| #define TIMPANI_TXADC2_EN_RESERVED_M 0x1 |
| |
| |
| /* -- For TXADC_CTL */ |
| #define TIMPANI_A_TXADC_CTL (0x13) |
| #define TIMPANI_TXADC_CTL_RWC "RW" |
| #define TIMPANI_TXADC_CTL_POR 0x58 |
| #define TIMPANI_TXADC_CTL_S 0 |
| #define TIMPANI_TXADC_CTL_M 0xFF |
| |
| |
| #define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_S 6 |
| #define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_M 0xC0 |
| #define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_5UA 0x0 |
| #define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_10UA_NORMAL_OP 0x1 |
| #define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_15UA 0x2 |
| #define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_20UA 0x3 |
| |
| #define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_S 4 |
| #define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_M 0x30 |
| #define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_40UA 0x0 |
| #define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_80UA 0x1 |
| #define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_120UA 0x2 |
| #define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_160UA 0x3 |
| |
| #define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_S 2 |
| #define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_M 0xC |
| #define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_8V 0x0 |
| #define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_7V 0x1 |
| #define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_6V_NORMAL_OP 0x2 |
| #define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_5V 0x3 |
| |
| #define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_S 0 |
| #define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_M 0x3 |
| #define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_20UA_NORMAL_OP 0x0 |
| #define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_40UA 0x1 |
| #define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_80UA 0x2 |
| #define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_160UA 0x3 |
| |
| |
| /* -- For TXADC_CTL2 */ |
| #define TIMPANI_A_TXADC_CTL2 (0x14) |
| #define TIMPANI_TXADC_CTL2_RWC "RW" |
| #define TIMPANI_TXADC_CTL2_POR 0x64 |
| #define TIMPANI_TXADC_CTL2_S 0 |
| #define TIMPANI_TXADC_CTL2_M 0xFF |
| |
| |
| #define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_S 6 |
| #define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_M 0xC0 |
| #define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_333MV 0x0 |
| #define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_356MV_NORMAL_OP 0x1 |
| #define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_378MV 0x2 |
| #define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_400MV 0x3 |
| |
| #define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_S 4 |
| #define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_M 0x30 |
| #define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_50UA 0x0 |
| #define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_100UA 0x1 |
| #define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_200UA_NORMAL_OP 0x2 |
| #define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_400UA 0x3 |
| |
| #define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_S 2 |
| #define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_M 0xC |
| #define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_1V 0x0 |
| #define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_15V_NORMAL_OP 0x1 |
| #define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_2V 0x2 |
| #define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_25V 0x3 |
| |
| #define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_S 1 |
| #define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_M 0x2 |
| #define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_V_50UA_NORMAL_OP 0x0 |
| #define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_V_100UA 0x1 |
| |
| #define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_S 0 |
| #define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_M 0x1 |
| #define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_DISABLE 0x0 |
| #define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_ENABLE_NORMAL_OP 0x1 |
| |
| |
| /* -- For TXADC_CTL3 */ |
| #define TIMPANI_A_TXADC_CTL3 (0x15) |
| #define TIMPANI_TXADC_CTL3_RWC "RW" |
| #define TIMPANI_TXADC_CTL3_POR 0x64 |
| #define TIMPANI_TXADC_CTL3_S 0 |
| #define TIMPANI_TXADC_CTL3_M 0xFF |
| |
| |
| #define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_S 6 |
| #define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_M 0xC0 |
| #define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_0_85V 0x0 |
| #define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_0_90V_NORMAL_OP 0x1 |
| #define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_0_95V 0x2 |
| #define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_1_00V 0x3 |
| |
| #define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_S 4 |
| #define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_M 0x30 |
| #define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_10UA 0x0 |
| #define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_15UA 0x1 |
| #define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_20UA_NORMAL_OP 0x2 |
| #define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_25UA 0x3 |
| |
| #define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_S 2 |
| #define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_M 0xC |
| #define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_5UA 0x0 |
| #define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_10UA_NORMAL_OP 0x1 |
| #define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_15UA 0x2 |
| #define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_20UA 0x3 |
| |
| #define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_S 1 |
| #define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_M 0x2 |
| #define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_V_5UA_NORMAL_OP 0x0 |
| #define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_V_10UA 0x1 |
| |
| #define TIMPANI_TXADC_CTL3_RESERVED_S 0 |
| #define TIMPANI_TXADC_CTL3_RESERVED_M 0x1 |
| |
| |
| /* -- For TXADC_CHOP_CTL */ |
| #define TIMPANI_A_TXADC_CHOP_CTL (0x16) |
| #define TIMPANI_TXADC_CHOP_CTL_RWC "RW" |
| #define TIMPANI_TXADC_CHOP_CTL_POR 0 |
| #define TIMPANI_TXADC_CHOP_CTL_S 0 |
| #define TIMPANI_TXADC_CHOP_CTL_M 0xFF |
| |
| |
| #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_EN_S 7 |
| #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_EN_M 0x80 |
| #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_EN_DISABLE 0x0 |
| #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_S 4 |
| #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_M 0x70 |
| #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_2_NORMAL_OP 0x0 |
| #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_4 0x1 |
| #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_8 0x2 |
| #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_16 0x3 |
| #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_32 0x4 |
| #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_64 0x5 |
| #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_128 0x6 |
| #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_256 0x7 |
| |
| #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_S 3 |
| #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_M 0x8 |
| #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_NORMAL_OP 0x0 |
| #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_RESET_CHOP 0x1 |
| |
| #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_S 2 |
| #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_M 0x4 |
| #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_FALLING_EDGE_CK1 0x0 |
| #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_FALLING_EDGE_CK2 0x1 |
| |
| #define TIMPANI_TXADC_CHOP_CTL_RESERVED_S 0 |
| #define TIMPANI_TXADC_CHOP_CTL_RESERVED_M 0x3 |
| |
| |
| /* -- For TXFE3 */ |
| #define TIMPANI_A_TXFE3 (0x18) |
| #define TIMPANI_TXFE3_RWC "RW" |
| #define TIMPANI_TXFE3_POR 0 |
| #define TIMPANI_TXFE3_S 0 |
| #define TIMPANI_TXFE3_M 0xFF |
| |
| |
| #define TIMPANI_TXFE3_TXFE3_EN_S 7 |
| #define TIMPANI_TXFE3_TXFE3_EN_M 0x80 |
| #define TIMPANI_TXFE3_TXFE3_EN_DISABLE 0x0 |
| #define TIMPANI_TXFE3_TXFE3_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXFE3_TXFE3_GAIN_S 5 |
| #define TIMPANI_TXFE3_TXFE3_GAIN_M 0x60 |
| #define TIMPANI_TXFE3_TXFE3_GAIN_V_0DB 0x0 |
| #define TIMPANI_TXFE3_TXFE3_GAIN_V_4_5DB 0x1 |
| #define TIMPANI_TXFE3_TXFE3_GAIN_V_24DB_1 0x2 |
| #define TIMPANI_TXFE3_TXFE3_GAIN_V_24DB_2 0x3 |
| |
| #define TIMPANI_TXFE3_RESERVED_1_S 2 |
| #define TIMPANI_TXFE3_RESERVED_1_M 0x1C |
| |
| #define TIMPANI_TXFE3_TXFE3_IN_CONN_S 1 |
| #define TIMPANI_TXFE3_TXFE3_IN_CONN_M 0x2 |
| #define TIMPANI_TXFE3_TXFE3_IN_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_TXFE3_TXFE3_IN_CONN_LINE_IN_L 0x1 |
| |
| #define TIMPANI_TXFE3_RESERVED_2_S 0 |
| #define TIMPANI_TXFE3_RESERVED_2_M 0x1 |
| |
| |
| /* -- For TXFE4 */ |
| #define TIMPANI_A_TXFE4 (0x19) |
| #define TIMPANI_TXFE4_RWC "RW" |
| #define TIMPANI_TXFE4_POR 0 |
| #define TIMPANI_TXFE4_S 0 |
| #define TIMPANI_TXFE4_M 0xFF |
| |
| |
| #define TIMPANI_TXFE4_TXFE4_EN_S 7 |
| #define TIMPANI_TXFE4_TXFE4_EN_M 0x80 |
| #define TIMPANI_TXFE4_TXFE4_EN_DISABLE 0x0 |
| #define TIMPANI_TXFE4_TXFE4_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXFE4_TXFE4_GAIN_S 5 |
| #define TIMPANI_TXFE4_TXFE4_GAIN_M 0x60 |
| #define TIMPANI_TXFE4_TXFE4_GAIN_V_0DB 0x0 |
| #define TIMPANI_TXFE4_TXFE4_GAIN_V_4_5DB 0x1 |
| #define TIMPANI_TXFE4_TXFE4_GAIN_V_24DB_1 0x2 |
| #define TIMPANI_TXFE4_TXFE4_GAIN_V_24DB_2 0x3 |
| |
| #define TIMPANI_TXFE4_RESERVED_1_S 2 |
| #define TIMPANI_TXFE4_RESERVED_1_M 0x1C |
| |
| #define TIMPANI_TXFE4_TXFE4_IN_CONN_S 1 |
| #define TIMPANI_TXFE4_TXFE4_IN_CONN_M 0x2 |
| #define TIMPANI_TXFE4_TXFE4_IN_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_TXFE4_TXFE4_IN_CONN_LINE_IN_R 0x1 |
| |
| #define TIMPANI_TXFE4_RESERVED_2_S 0 |
| #define TIMPANI_TXFE4_RESERVED_2_M 0x1 |
| |
| |
| /* -- For TXFE3_ATEST */ |
| #define TIMPANI_A_TXFE3_ATEST (0x1A) |
| #define TIMPANI_TXFE3_ATEST_RWC "RW" |
| #define TIMPANI_TXFE3_ATEST_POR 0 |
| #define TIMPANI_TXFE3_ATEST_S 0 |
| #define TIMPANI_TXFE3_ATEST_M 0xFF |
| |
| |
| #define TIMPANI_TXFE3_ATEST_TXFE3_OUT_SHORT_TO_VICM_EN_S 7 |
| #define TIMPANI_TXFE3_ATEST_TXFE3_OUT_SHORT_TO_VICM_EN_M 0x80 |
| #define TIMPANI_TXFE3_ATEST_TXFE3_OUT_SHORT_TO_VICM_EN_DISABLE 0x0 |
| #define TIMPANI_TXFE3_ATEST_TXFE3_OUT_SHORT_TO_VICM_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXFE3_ATEST_TXFE3_BYPASS_EN_S 6 |
| #define TIMPANI_TXFE3_ATEST_TXFE3_BYPASS_EN_M 0x40 |
| #define TIMPANI_TXFE3_ATEST_TXFE3_BYPASS_EN_DISABLE 0x0 |
| #define TIMPANI_TXFE3_ATEST_TXFE3_BYPASS_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_S 5 |
| #define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_M 0x20 |
| #define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_TXFE3_ATEST_TXFE3_OUT_ATEST_CONN_S 4 |
| #define TIMPANI_TXFE3_ATEST_TXFE3_OUT_ATEST_CONN_M 0x10 |
| #define TIMPANI_TXFE3_ATEST_TXFE3_OUT_ATEST_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_TXFE3_ATEST_TXFE3_OUT_ATEST_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_S 3 |
| #define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_M 0x8 |
| #define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_DISABLE 0x0 |
| #define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_S 2 |
| #define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_M 0x4 |
| #define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_DISABLE 0x0 |
| #define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_ENABLE 0x1 |
| |
| #define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_S 1 |
| #define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_M 0x2 |
| #define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_S 0 |
| #define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_M 0x1 |
| #define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_CONNECT 0x1 |
| |
| |
| /* -- For TXFE_DIFF_SE */ |
| #define TIMPANI_A_TXFE_DIFF_SE (0x1B) |
| #define TIMPANI_TXFE_DIFF_SE_RWC "RW" |
| #define TIMPANI_TXFE_DIFF_SE_POR 0 |
| #define TIMPANI_TXFE_DIFF_SE_S 0 |
| #define TIMPANI_TXFE_DIFF_SE_M 0xFF |
| |
| |
| #define TIMPANI_TXFE_DIFF_SE_RESERVED_S 4 |
| #define TIMPANI_TXFE_DIFF_SE_RESERVED_M 0xF0 |
| |
| #define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_S 3 |
| #define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_M 0x8 |
| #define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_DIFF 0x0 |
| #define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_SINGLE_ENDED 0x1 |
| |
| #define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_S 2 |
| #define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_M 0x4 |
| #define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_DIFF 0x0 |
| #define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_SINGLE_ENDED 0x1 |
| |
| #define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_S 1 |
| #define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_M 0x2 |
| #define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_DIFF 0x0 |
| #define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_SINGLE_ENDED 0x1 |
| |
| #define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_S 0 |
| #define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_M 0x1 |
| #define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_DIFF 0x0 |
| #define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_SINGLE_ENDED 0x1 |
| |
| |
| /* -- For CDAC_RX_CLK_CTL */ |
| #define TIMPANI_A_CDAC_RX_CLK_CTL (0x20) |
| #define TIMPANI_CDAC_RX_CLK_CTL_RWC "RW" |
| #define TIMPANI_CDAC_RX_CLK_CTL_POR 0x98 |
| #define TIMPANI_CDAC_RX_CLK_CTL_S 0 |
| #define TIMPANI_CDAC_RX_CLK_CTL_M 0xFF |
| |
| |
| #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_EN_S 7 |
| #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_EN_M 0x80 |
| #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_EN_DISABLE 0x0 |
| #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_EN_ENABLE_NORMAL_OP 0x1 |
| |
| #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_CTRL_EN_S 6 |
| #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_CTRL_EN_M 0x40 |
| #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_CTRL_EN_DISABLE_NORMAL_OP 0x0 |
| #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_CTRL_EN_ENABLE 0x1 |
| |
| #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_S 2 |
| #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_M 0x3C |
| #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_6NS 0x0 |
| #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_8_4NS 0x1 |
| #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_10_8NS 0x2 |
| #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_13_2NS 0x3 |
| #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_15_6NS 0x4 |
| #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_18NS 0x5 |
| #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_20_4NS_NORMAL_OP 0x6 |
| #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_22_8NS 0x7 |
| #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_25_2NS 0x8 |
| #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_27_6NS 0x9 |
| #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_30NS 0xA |
| #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_32_4NS 0xB |
| #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_34_8NS 0xC |
| #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_37_2NS 0xD |
| #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_39_6NS 0xE |
| #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_42NS 0xF |
| |
| #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_S 1 |
| #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_M 0x2 |
| #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_ENABLE 0x1 |
| #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_DISABLE 0x0 |
| |
| #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_S 0 |
| #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_M 0x1 |
| #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_CONNECT 0x1 |
| |
| |
| /* -- For CDAC_BUFF_CTL */ |
| #define TIMPANI_A_CDAC_BUFF_CTL (0x21) |
| #define TIMPANI_CDAC_BUFF_CTL_RWC "RW" |
| #define TIMPANI_CDAC_BUFF_CTL_POR 0x60 |
| #define TIMPANI_CDAC_BUFF_CTL_S 0 |
| #define TIMPANI_CDAC_BUFF_CTL_M 0xFF |
| |
| |
| #define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_S 5 |
| #define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_M 0xE0 |
| #define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_40UA 0x0 |
| #define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_60UA_NORMAL_OP 0x1 |
| #define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_80UA 0x2 |
| #define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_100UA 0x3 |
| #define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_120UA 0x4 |
| #define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_140UA 0x5 |
| #define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_160UA 0x6 |
| #define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_180UA 0x7 |
| |
| #define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_S 3 |
| #define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_M 0x18 |
| #define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_20UA 0x0 |
| #define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_30UA_NORMAL_OP 0x1 |
| #define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_40UA 0x2 |
| #define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_50UA 0x3 |
| |
| #define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_S 1 |
| #define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_M 0x6 |
| #define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_5UA_5UA 0x0 |
| #define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_5UA_10UA 0x1 |
| #define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_10UA_5UA 0x2 |
| #define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_10UA_10UA 0x3 |
| |
| #define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_S 0 |
| #define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_M 0x1 |
| #define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_CURRENT_TO_VCOM_NORMAL_OP 0x0 |
| #define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_MASTER_BIAS_TO_VCOM 0x1 |
| |
| |
| /* -- For CDAC_REF_CTL1 */ |
| #define TIMPANI_A_CDAC_REF_CTL1 (0x22) |
| #define TIMPANI_CDAC_REF_CTL1_RWC "RW" |
| #define TIMPANI_CDAC_REF_CTL1_POR 0xe1 |
| #define TIMPANI_CDAC_REF_CTL1_S 0 |
| #define TIMPANI_CDAC_REF_CTL1_M 0xFF |
| |
| |
| #define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_S 5 |
| #define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_M 0xE0 |
| #define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_8V 0x0 |
| #define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_825V 0x1 |
| #define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_85V 0x2 |
| #define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_9V 0x3 |
| #define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_925V 0x4 |
| #define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_95V_NORMAL_OP 0x5 |
| #define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_975 0x6 |
| #define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_2_0V 0x7 |
| |
| #define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_S 2 |
| #define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_M 0x1C |
| #define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_1V 0x0 |
| #define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_125V 0x1 |
| #define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_15V_NORMAL_OP 0x2 |
| #define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_175V 0x3 |
| #define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_2V 0x4 |
| #define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_25V 0x5 |
| #define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_275V 0x6 |
| #define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_3V 0x7 |
| |
| #define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_S 0 |
| #define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_M 0x3 |
| #define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_025V 0x0 |
| #define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_05V_NORMAL_OP 0x1 |
| #define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_075V 0x2 |
| #define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_1V 0x3 |
| |
| |
| /* -- For IDAC_DWA_FIR_CTL */ |
| #define TIMPANI_A_IDAC_DWA_FIR_CTL (0x23) |
| #define TIMPANI_IDAC_DWA_FIR_CTL_RWC "RW" |
| #define TIMPANI_IDAC_DWA_FIR_CTL_POR 0x28 |
| #define TIMPANI_IDAC_DWA_FIR_CTL_S 0 |
| #define TIMPANI_IDAC_DWA_FIR_CTL_M 0xFF |
| |
| |
| #define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_CLK_NON_OL_TIME_S 7 |
| #define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_CLK_NON_OL_TIME_M 0x80 |
| #define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_CLK_NON_OL_TIME_NORMAL_OP 0x0 |
| #define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_CLK_NON_OL_TIME_V_150PSEC_REDUCTION 0x1 |
| |
| #define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_S 4 |
| #define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_M 0x70 |
| #define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR0 0x0 |
| #define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR1 0x1 |
| #define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR2 0x2 |
| #define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR3 0x3 |
| #define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR4 0x4 |
| |
| #define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_S 3 |
| #define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_M 0x8 |
| #define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_INTERNAL_NORMAL_OP 0x1 |
| #define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_EXTERNAL 0x0 |
| |
| #define TIMPANI_IDAC_DWA_FIR_CTL_RESERVED_S 0 |
| #define TIMPANI_IDAC_DWA_FIR_CTL_RESERVED_M 0x7 |
| |
| |
| /* -- For CDAC_REF_CTL2 */ |
| #define TIMPANI_A_CDAC_REF_CTL2 (0x24) |
| #define TIMPANI_CDAC_REF_CTL2_RWC "RW" |
| #define TIMPANI_CDAC_REF_CTL2_POR 0xc |
| #define TIMPANI_CDAC_REF_CTL2_S 0 |
| #define TIMPANI_CDAC_REF_CTL2_M 0xFF |
| |
| |
| #define TIMPANI_CDAC_REF_CTL2_RESERVED_1_S 7 |
| #define TIMPANI_CDAC_REF_CTL2_RESERVED_1_M 0x80 |
| |
| #define TIMPANI_CDAC_REF_CTL2_CDAC_L_EN_S 6 |
| #define TIMPANI_CDAC_REF_CTL2_CDAC_L_EN_M 0x40 |
| #define TIMPANI_CDAC_REF_CTL2_CDAC_L_EN_DISABLE 0x0 |
| #define TIMPANI_CDAC_REF_CTL2_CDAC_L_EN_ENABLE 0x1 |
| |
| #define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_S 5 |
| #define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_M 0x20 |
| #define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_DISABLE 0x0 |
| #define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_ENABLE 0x1 |
| |
| #define TIMPANI_CDAC_REF_CTL2_RESERVED_2_S 4 |
| #define TIMPANI_CDAC_REF_CTL2_RESERVED_2_M 0x10 |
| |
| #define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_S 2 |
| #define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_M 0xC |
| #define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_CLK_SYNC_CK11DBAR 0x1 |
| #define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_CLK_SYNC_CK21 0x3 |
| |
| #define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_S 0 |
| #define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_M 0x3 |
| #define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_V_256 0x0 |
| #define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_V_128 0x1 |
| #define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_V_64 0x3 |
| |
| |
| /* -- For CDAC_CTL1 */ |
| #define TIMPANI_A_CDAC_CTL1 (0x25) |
| #define TIMPANI_CDAC_CTL1_RWC "RW" |
| #define TIMPANI_CDAC_CTL1_POR 0xb |
| #define TIMPANI_CDAC_CTL1_S 0 |
| #define TIMPANI_CDAC_CTL1_M 0xFF |
| |
| |
| #define TIMPANI_CDAC_CTL1_RESERVED_S 6 |
| #define TIMPANI_CDAC_CTL1_RESERVED_M 0xC0 |
| |
| #define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_S 5 |
| #define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_M 0x20 |
| #define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_DISABLE 0x0 |
| #define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_ENABLE 0x1 |
| |
| #define TIMPANI_CDAC_CTL1_CDAC_R_OUT_SHORT_EN_S 4 |
| #define TIMPANI_CDAC_CTL1_CDAC_R_OUT_SHORT_EN_M 0x10 |
| #define TIMPANI_CDAC_CTL1_CDAC_R_OUT_SHORT_EN_DISABLE 0x0 |
| #define TIMPANI_CDAC_CTL1_CDAC_R_OUT_SHORT_EN_ENABLE 0x1 |
| |
| #define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_S 2 |
| #define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_M 0xC |
| #define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_0V 0x0 |
| #define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_025V 0x1 |
| #define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_05V_NORMAL_OP 0x2 |
| #define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_0752V 0x3 |
| |
| #define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_S 1 |
| #define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_M 0x2 |
| #define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_DISABLE 0x0 |
| #define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_ENABLE_NORMAL_OP 0x1 |
| |
| #define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_S 0 |
| #define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_M 0x1 |
| #define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_INTERNAL_NORMAL_OP 0x1 |
| #define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_EXTERNAL_REGISTER_RESET 0x0 |
| |
| |
| /* -- For CDAC_CTL2 */ |
| #define TIMPANI_A_CDAC_CTL2 (0x26) |
| #define TIMPANI_CDAC_CTL2_RWC "RW" |
| #define TIMPANI_CDAC_CTL2_POR 0xd0 |
| #define TIMPANI_CDAC_CTL2_S 0 |
| #define TIMPANI_CDAC_CTL2_M 0xFF |
| |
| |
| #define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_S 5 |
| #define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_M 0xE0 |
| #define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_10UA 0x0 |
| #define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_8_75UA 0x1 |
| #define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_7_5UA 0x2 |
| #define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_6_25UA 0x3 |
| #define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_5UA 0x4 |
| #define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_3_75UA 0x5 |
| #define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_2_5UA_NORMAL_OP 0x6 |
| #define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_1_25UA 0x7 |
| |
| #define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_S 2 |
| #define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_M 0x1C |
| #define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_10UA 0x0 |
| #define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_8_75UA 0x1 |
| #define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_7_5UA 0x2 |
| #define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_6_25UA 0x3 |
| #define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_5UA_NORMAL_OP 0x4 |
| #define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_3_75UA 0x5 |
| #define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_2_5UA 0x6 |
| #define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_1_25UA 0x7 |
| |
| #define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_S 0 |
| #define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_M 0x3 |
| #define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_FS 0x0 |
| #define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_FS_BY_8 0x1 |
| #define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_FS_BY_16 0x2 |
| |
| |
| /* -- For IDAC_L_CTL */ |
| #define TIMPANI_A_IDAC_L_CTL (0x28) |
| #define TIMPANI_IDAC_L_CTL_RWC "RW" |
| #define TIMPANI_IDAC_L_CTL_POR 0xe |
| #define TIMPANI_IDAC_L_CTL_S 0 |
| #define TIMPANI_IDAC_L_CTL_M 0xFF |
| |
| |
| #define TIMPANI_IDAC_L_CTL_IDAC_L_EN_S 7 |
| #define TIMPANI_IDAC_L_CTL_IDAC_L_EN_M 0x80 |
| #define TIMPANI_IDAC_L_CTL_IDAC_L_EN_DISABLE 0x0 |
| #define TIMPANI_IDAC_L_CTL_IDAC_L_EN_ENABLE 0x1 |
| |
| #define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_S 5 |
| #define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_M 0x60 |
| #define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_GROUND 0x0 |
| #define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_IBIAS_X_R_REF 0x1 |
| #define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_BG_VOLTAGE_NORMAL_OP 0x2 |
| #define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_VDD_BY_2 0x3 |
| |
| #define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_S 3 |
| #define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_M 0x18 |
| #define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_NEG_1_5DB 0x0 |
| #define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_V_0_0DB_NORMAL_OP 0x1 |
| #define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_POS_1_5DB 0x2 |
| #define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_POS_3_0DB 0x3 |
| |
| #define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_S 2 |
| #define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_M 0x4 |
| #define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_V_30K 0x0 |
| #define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_V_10K_NORMAL_OP 0x1 |
| |
| #define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_S 1 |
| #define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_M 0x2 |
| #define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_ASYNCHRONOUSLY 0x0 |
| #define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_ENABLE_NORMAL_OP 0x1 |
| |
| #define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_S 0 |
| #define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_M 0x1 |
| #define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_REPLICA_BIAS_NORMAL_OP 0x0 |
| #define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_SERVO_LOOP_BIAS 0x1 |
| |
| |
| /* -- For IDAC_R_CTL */ |
| #define TIMPANI_A_IDAC_R_CTL (0x29) |
| #define TIMPANI_IDAC_R_CTL_RWC "RW" |
| #define TIMPANI_IDAC_R_CTL_POR 0xe |
| #define TIMPANI_IDAC_R_CTL_S 0 |
| #define TIMPANI_IDAC_R_CTL_M 0xFF |
| |
| |
| #define TIMPANI_IDAC_R_CTL_IDAC_R_EN_S 7 |
| #define TIMPANI_IDAC_R_CTL_IDAC_R_EN_M 0x80 |
| #define TIMPANI_IDAC_R_CTL_IDAC_R_EN_DISABLED 0x0 |
| #define TIMPANI_IDAC_R_CTL_IDAC_R_EN_ENABLED 0x1 |
| |
| #define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_S 5 |
| #define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_M 0x60 |
| #define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_GROUND 0x0 |
| #define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_IBIAS_X_R_REF 0x1 |
| #define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_BG_VOLTAGE_NORMAL_OP 0x2 |
| #define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_VDD_BY_2 0x3 |
| |
| #define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_S 3 |
| #define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_M 0x18 |
| #define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_NEG_1_5DB 0x0 |
| #define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_V_0_0DB_NORMAL_OP 0x1 |
| #define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_POS_1_5DB 0x2 |
| #define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_POS_3_0DB 0x3 |
| |
| #define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_S 2 |
| #define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_M 0x4 |
| #define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_V_30K 0x0 |
| #define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_V_10K_NORMAL_OP 0x1 |
| |
| #define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_S 1 |
| #define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_M 0x2 |
| #define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_ASYNCHRONOUSLY 0x0 |
| #define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_ENABLE_NORMAL_OP 0x1 |
| |
| #define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_S 0 |
| #define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_M 0x1 |
| #define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_REPLICA_BIAS_NORMAL_OP 0x0 |
| #define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_SERVO_LOOP_BIAS 0x1 |
| |
| |
| /* -- For PA_MASTER_BIAS */ |
| #define TIMPANI_A_PA_MASTER_BIAS (0x2D) |
| #define TIMPANI_PA_MASTER_BIAS_RWC "RW" |
| #define TIMPANI_PA_MASTER_BIAS_POR 0x6f |
| #define TIMPANI_PA_MASTER_BIAS_S 0 |
| #define TIMPANI_PA_MASTER_BIAS_M 0xFF |
| |
| |
| #define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_S 5 |
| #define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_M 0xE0 |
| #define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_17_5UA 0x0 |
| #define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_15_0UA 0x1 |
| #define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_12_5UA 0x2 |
| #define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_10_0UA 0x3 |
| #define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_7_5UA 0x4 |
| #define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_5_0UA 0x5 |
| #define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_2_5UA 0x6 |
| #define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_0_0UA 0x7 |
| |
| #define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_S 2 |
| #define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_M 0x1C |
| #define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_17_5UA 0x0 |
| #define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_15_0UA 0x1 |
| #define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_12_5UA 0x2 |
| #define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_10_0UA 0x3 |
| #define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_7_5UA 0x4 |
| #define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_5_0UA 0x5 |
| #define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_2_5UA 0x6 |
| #define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_0_0UA 0x7 |
| |
| #define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_S 0 |
| #define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_M 0x3 |
| #define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_6_25UA 0x0 |
| #define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_5_0UA 0x1 |
| #define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_3_75UA 0x2 |
| #define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_2_5UA 0x3 |
| |
| |
| /* -- For PA_CLASSD_BIAS */ |
| #define TIMPANI_A_PA_CLASSD_BIAS (0x2E) |
| #define TIMPANI_PA_CLASSD_BIAS_RWC "RW" |
| #define TIMPANI_PA_CLASSD_BIAS_POR 0x55 |
| #define TIMPANI_PA_CLASSD_BIAS_S 0 |
| #define TIMPANI_PA_CLASSD_BIAS_M 0xFF |
| |
| |
| #define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_S 6 |
| #define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_M 0xC0 |
| #define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_V_6_25UA 0x0 |
| #define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_V_5_0UA 0x1 |
| #define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_V_3_75UA 0x2 |
| #define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_V_2_5UA 0x3 |
| |
| #define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_S 4 |
| #define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_M 0x30 |
| #define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_6_25UA 0x0 |
| #define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_5_0U 0x1 |
| #define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_3_75UA 0x2 |
| #define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_2_5UA 0x3 |
| |
| #define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_S 2 |
| #define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_M 0xC |
| #define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_6_25UA 0x0 |
| #define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_5_0UA 0x1 |
| #define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_3_75UA 0x2 |
| #define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_2_5UA 0x3 |
| |
| #define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_S 0 |
| #define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_M 0x3 |
| #define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_6_25UA 0x0 |
| #define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_5_0UA 0x1 |
| #define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_3_75UA 0x2 |
| #define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_2_5UA 0x3 |
| |
| |
| /* -- For AUXPGA_CUR */ |
| #define TIMPANI_A_AUXPGA_CUR (0x2F) |
| #define TIMPANI_AUXPGA_CUR_RWC "RW" |
| #define TIMPANI_AUXPGA_CUR_POR 0x44 |
| #define TIMPANI_AUXPGA_CUR_S 0 |
| #define TIMPANI_AUXPGA_CUR_M 0xFF |
| |
| |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_S 4 |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_M 0xF0 |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0UA 0x0 |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0_3125UA 0x1 |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0_625UA 0x2 |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0_9375UA 0x3 |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_1_25UA 0x4 |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_1_5625UA 0x5 |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_1_875UA 0x6 |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_2_1875UA 0x7 |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_2_5UA 0x8 |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_2_8125UA 0x9 |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_3_125UA 0xA |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_3_4375UA 0xB |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_3_75UA 0xC |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_4_0625UA 0xD |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_4_375UA 0xE |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_4_6875UA 0xF |
| |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_S 0 |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_M 0xF |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0UA 0x0 |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0_3125UA 0x1 |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0_625UA 0x2 |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0_9375UA 0x3 |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_1_25UA 0x4 |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_1_5625UA 0x5 |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_1_875UA 0x6 |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_2_1875UA 0x7 |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_2_5UA 0x8 |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_2_8125UA 0x9 |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_3_125UA 0xA |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_3_4375UA 0xB |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_3_75UA 0xC |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_4_0625UA 0xD |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_4_375UA 0xE |
| #define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_4_6875UA 0xF |
| |
| |
| /* -- For AUXPGA_CM */ |
| #define TIMPANI_A_AUXPGA_CM (0x30) |
| #define TIMPANI_AUXPGA_CM_RWC "RW" |
| #define TIMPANI_AUXPGA_CM_POR 0x92 |
| #define TIMPANI_AUXPGA_CM_S 0 |
| #define TIMPANI_AUXPGA_CM_M 0xFF |
| |
| |
| #define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_S 5 |
| #define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_M 0xE0 |
| #define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_7_5UA 0x0 |
| #define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_7_925UA 0x1 |
| #define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_8_75UA 0x2 |
| #define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_9_375UA 0x3 |
| #define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_10UA 0x4 |
| #define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_10_625UA 0x5 |
| #define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_11_25UA 0x6 |
| #define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_11_875UA 0x7 |
| |
| #define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_S 2 |
| #define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_M 0x1C |
| #define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_7_5UA 0x0 |
| #define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_7_925UA 0x1 |
| #define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_8_75UA 0x2 |
| #define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_9_375UA 0x3 |
| #define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_10UA 0x4 |
| #define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_10_625UA 0x5 |
| #define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_11_25UA 0x6 |
| #define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_11_875UA 0x7 |
| |
| #define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_S 1 |
| #define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_M 0x2 |
| #define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_VCMI_TO_R2R_CM 0x1 |
| #define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_R2R_CM_FLOATING 0x0 |
| |
| #define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_S 0 |
| #define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_M 0x1 |
| #define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_GEN_VCM_LOCALLY 0x1 |
| #define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_BG_VCM 0x0 |
| |
| |
| /* -- For PA_HPH_EARPA_MSTB_EN */ |
| #define TIMPANI_A_PA_HPH_EARPA_MSTB_EN (0x31) |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_RWC "RW" |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_POR 0x4 |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_S 0 |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_M 0xFF |
| |
| |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_EN_S 7 |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_EN_M 0x80 |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_EN_ENABLE 0x1 |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_EN_DISABLE 0x0 |
| |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_BIAS_EN_S 6 |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_BIAS_EN_M 0x40 |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_BIAS_EN_ENABLE 0x1 |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_BIAS_EN_DISABLE 0x0 |
| |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_S 5 |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_M 0x20 |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_ENABLE 0x1 |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_DISABLE 0x0 |
| |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_BIAS_EN_S 4 |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_BIAS_EN_M 0x10 |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_BIAS_EN_ENABLE 0x1 |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_BIAS_EN_DISABLE 0x0 |
| |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_S 3 |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_M 0x8 |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_ENABLE 0x1 |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_DISABLE 0x0 |
| |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_S 2 |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_M 0x4 |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_CAPLESS 0x1 |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_LEGACY 0x0 |
| |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_S 1 |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_M 0x2 |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_ENABLE 0x1 |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_DISABLE 0x0 |
| |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_S 0 |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_M 0x1 |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_ENABLE 0x1 |
| #define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_DISABLE 0x0 |
| |
| |
| /* -- For PA_LINE_AUXO_EN */ |
| #define TIMPANI_A_PA_LINE_AUXO_EN (0x32) |
| #define TIMPANI_PA_LINE_AUXO_EN_RWC "RW" |
| #define TIMPANI_PA_LINE_AUXO_EN_POR 0 |
| #define TIMPANI_PA_LINE_AUXO_EN_S 0 |
| #define TIMPANI_PA_LINE_AUXO_EN_M 0xFF |
| |
| |
| #define TIMPANI_PA_LINE_AUXO_EN_LINE_L_EN_S 7 |
| #define TIMPANI_PA_LINE_AUXO_EN_LINE_L_EN_M 0x80 |
| #define TIMPANI_PA_LINE_AUXO_EN_LINE_L_EN_ENABLE 0x1 |
| #define TIMPANI_PA_LINE_AUXO_EN_LINE_L_EN_DISABLE 0x0 |
| |
| #define TIMPANI_PA_LINE_AUXO_EN_LINE_L_BIAS_EN_S 6 |
| #define TIMPANI_PA_LINE_AUXO_EN_LINE_L_BIAS_EN_M 0x40 |
| #define TIMPANI_PA_LINE_AUXO_EN_LINE_L_BIAS_EN_ENABLE 0x1 |
| #define TIMPANI_PA_LINE_AUXO_EN_LINE_L_BIAS_EN_DISABLE 0x0 |
| |
| #define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_S 5 |
| #define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_M 0x20 |
| #define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_ENABLE 0x1 |
| #define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_DISABLE 0x0 |
| |
| #define TIMPANI_PA_LINE_AUXO_EN_LINE_R_BIAS_EN_S 4 |
| #define TIMPANI_PA_LINE_AUXO_EN_LINE_R_BIAS_EN_M 0x10 |
| #define TIMPANI_PA_LINE_AUXO_EN_LINE_R_BIAS_EN_ENABLE 0x1 |
| #define TIMPANI_PA_LINE_AUXO_EN_LINE_R_BIAS_EN_DISABLE 0x0 |
| |
| #define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_S 3 |
| #define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_M 0x8 |
| #define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_ENABLE 0x1 |
| #define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_DISABLE 0x0 |
| |
| #define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_S 2 |
| #define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_M 0x4 |
| #define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_ENABLE 0x1 |
| #define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_DISABLE 0x0 |
| |
| #define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_S 1 |
| #define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_M 0x2 |
| #define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_ENABLE 0x1 |
| #define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_DISABLE 0x0 |
| |
| #define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_S 0 |
| #define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_M 0x1 |
| #define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_ENABLE 0x1 |
| #define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_DISABLE 0x0 |
| |
| |
| /* -- For PA_CLASSD_AUXPGA_EN */ |
| #define TIMPANI_A_PA_CLASSD_AUXPGA_EN (0x33) |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_RWC "RW" |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_POR 0 |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_S 0 |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_M 0xFF |
| |
| |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_MUTE_S 7 |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_MUTE_M 0x80 |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_MUTE_MUTE 0x1 |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_MUTE_UNMUTE 0x0 |
| |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_MUTE_S 6 |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_MUTE_M 0x40 |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_MUTE_MUTE 0x1 |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_MUTE_UNMUTE 0x0 |
| |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_S 5 |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_M 0x20 |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_DISABLE 0x0 |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_ENABLE 0x1 |
| |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_EN_S 4 |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_EN_M 0x10 |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_EN_DISABLE 0x0 |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_EN_ENABLE 0x1 |
| |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_S 3 |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_M 0x8 |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_DISABLE 0x0 |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_ENABLE 0x1 |
| |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_S 2 |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_M 0x4 |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_DISABLE 0x0 |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_ENABLE 0x1 |
| |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_S 1 |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_M 0x2 |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_DISABLE 0x0 |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_ENABLE 0x1 |
| |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_S 0 |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_M 0x1 |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_DISABLE 0x0 |
| #define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_ENABLE 0x1 |
| |
| |
| /* -- For PA_LINE_L_GAIN */ |
| #define TIMPANI_A_PA_LINE_L_GAIN (0x34) |
| #define TIMPANI_PA_LINE_L_GAIN_RWC "RW" |
| #define TIMPANI_PA_LINE_L_GAIN_POR 0xac |
| #define TIMPANI_PA_LINE_L_GAIN_S 0 |
| #define TIMPANI_PA_LINE_L_GAIN_M 0xFF |
| |
| |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_S 2 |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_M 0xFC |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_POS_1_5 0x0 |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_POS_0_0 0x1 |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_1_5 0x2 |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_3_0 0x3 |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_4_5 0x4 |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_6_0 0x5 |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_7_5 0x6 |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_9_0 0x7 |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_10_5 0x8 |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_12_0 0x9 |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_13_5 0xA |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_15_0 0xB |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_16_5 0xC |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_18_0 0xD |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_19_5 0xE |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_21_0 0xF |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_22_5 0x10 |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_24_0 0x11 |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_25_5 0x12 |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_27_0 0x13 |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_28_5 0x14 |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_30_0 0x15 |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_31_5 0x16 |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_33_0 0x17 |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_34_5 0x18 |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_36_0 0x19 |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_37_5 0x1A |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_39_0 0x1B |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_40_5 0x1C |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_42_0 0x1D |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_43_5 0x1E |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_45_0 0x1F |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_46_5 0x20 |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_48_0 0x21 |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_49_5 0x22 |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_51_0 0x23 |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_52_5 0x24 |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_54_0 0x25 |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_55_5 0x26 |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_57_0 0x27 |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_58_5 0x28 |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_60_0 0x29 |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_61_5 0x2A |
| #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_63_0 0x2B |
| |
| #define TIMPANI_PA_LINE_L_GAIN_RESERVED_S 0 |
| #define TIMPANI_PA_LINE_L_GAIN_RESERVED_M 0x3 |
| |
| |
| /* -- For PA_LINE_R_GAIN */ |
| #define TIMPANI_A_PA_LINE_R_GAIN (0x35) |
| #define TIMPANI_PA_LINE_R_GAIN_RWC "RW" |
| #define TIMPANI_PA_LINE_R_GAIN_POR 0xac |
| #define TIMPANI_PA_LINE_R_GAIN_S 0 |
| #define TIMPANI_PA_LINE_R_GAIN_M 0xFF |
| |
| |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_S 2 |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_M 0xFC |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_POS_1_5 0x0 |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_POS_0_0 0x1 |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_1_5 0x2 |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_3_0 0x3 |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_4_5 0x4 |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_6_0 0x5 |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_7_5 0x6 |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_9_0 0x7 |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_10_5 0x8 |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_12_0 0x9 |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_13_5 0xA |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_15_0 0xB |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_16_5 0xC |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_18_0 0xD |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_19_5 0xE |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_21_0 0xF |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_22_5 0x10 |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_24_0 0x11 |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_25_5 0x12 |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_27_0 0x13 |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_28_5 0x14 |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_30_0 0x15 |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_31_5 0x16 |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_33_0 0x17 |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_34_5 0x18 |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_36_0 0x19 |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_37_5 0x1A |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_39_0 0x1B |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_40_5 0x1C |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_42_0 0x1D |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_43_5 0x1E |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_45_0 0x1F |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_46_5 0x20 |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_48_0 0x21 |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_49_5 0x22 |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_51_0 0x23 |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_52_5 0x24 |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_54_0 0x25 |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_55_5 0x26 |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_57_0 0x27 |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_58_5 0x28 |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_60_0 0x29 |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_61_5 0x2A |
| #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_63_0 0x2B |
| |
| #define TIMPANI_PA_LINE_R_GAIN_RESERVED_S 0 |
| #define TIMPANI_PA_LINE_R_GAIN_RESERVED_M 0x3 |
| |
| |
| /* -- For PA_HPH_L_GAIN */ |
| #define TIMPANI_A_PA_HPH_L_GAIN (0x36) |
| #define TIMPANI_PA_HPH_L_GAIN_RWC "RW" |
| #define TIMPANI_PA_HPH_L_GAIN_POR 0xae |
| #define TIMPANI_PA_HPH_L_GAIN_S 0 |
| #define TIMPANI_PA_HPH_L_GAIN_M 0xFF |
| |
| |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_S 2 |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_M 0xFC |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_POS_1_5 0x0 |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_POS_0_0 0x1 |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_1_5 0x2 |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_3_0 0x3 |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_4_5 0x4 |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_6_0 0x5 |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_7_5 0x6 |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_9_0 0x7 |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_10_5 0x8 |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_12_0 0x9 |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_13_5 0xA |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_15_0 0xB |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_16_5 0xC |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_18_0 0xD |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_19_5 0xE |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_21_0 0xF |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_22_5 0x10 |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_24_0 0x11 |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_25_5 0x12 |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_27_0 0x13 |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_28_5 0x14 |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_30_0 0x15 |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_31_5 0x16 |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_33_0 0x17 |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_34_5 0x18 |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_36_0 0x19 |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_37_5 0x1A |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_39_0 0x1B |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_40_5 0x1C |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_42_0 0x1D |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_43_5 0x1E |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_45_0 0x1F |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_46_5 0x20 |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_48_0 0x21 |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_49_5 0x22 |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_51_0 0x23 |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_52_5 0x24 |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_54_0 0x25 |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_55_5 0x26 |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_57_0 0x27 |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_58_5 0x28 |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_60_0 0x29 |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_61_5 0x2A |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_63_0 0x2B |
| |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_S 1 |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_M 0x2 |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_MUTE 0x1 |
| #define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_UNMUTE 0x0 |
| |
| #define TIMPANI_PA_HPH_L_GAIN_RESERVED_S 0 |
| #define TIMPANI_PA_HPH_L_GAIN_RESERVED_M 0x1 |
| |
| |
| /* -- For PA_HPH_R_GAIN */ |
| #define TIMPANI_A_PA_HPH_R_GAIN (0x37) |
| #define TIMPANI_PA_HPH_R_GAIN_RWC "RW" |
| #define TIMPANI_PA_HPH_R_GAIN_POR 0xae |
| #define TIMPANI_PA_HPH_R_GAIN_S 0 |
| #define TIMPANI_PA_HPH_R_GAIN_M 0xFF |
| |
| |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_S 2 |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_M 0xFC |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_POS_1_5 0x0 |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_POS_0_0 0x1 |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_1_5 0x2 |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_3_0 0x3 |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_4_5 0x4 |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_6_0 0x5 |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_7_5 0x6 |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_9_0 0x7 |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_10_5 0x8 |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_12_0 0x9 |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_13_5 0xA |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_15_0 0xB |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_16_5 0xC |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_18_0 0xD |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_19_5 0xE |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_21_0 0xF |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_22_5 0x10 |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_24_0 0x11 |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_25_5 0x12 |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_27_0 0x13 |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_28_5 0x14 |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_30_0 0x15 |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_31_5 0x16 |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_33_0 0x17 |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_34_5 0x18 |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_36_0 0x19 |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_37_5 0x1A |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_39_0 0x1B |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_40_5 0x1C |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_42_0 0x1D |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_43_5 0x1E |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_45_0 0x1F |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_46_5 0x20 |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_48_0 0x21 |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_49_5 0x22 |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_51_0 0x23 |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_52_5 0x24 |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_54_0 0x25 |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_55_5 0x26 |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_57_0 0x27 |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_58_5 0x28 |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_60_0 0x29 |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_61_5 0x2A |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_63_0 0x2B |
| |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_S 1 |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_M 0x2 |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_MUTE 0x1 |
| #define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_UNMUTE 0x0 |
| |
| #define TIMPANI_PA_HPH_R_GAIN_RESERVED_S 0 |
| #define TIMPANI_PA_HPH_R_GAIN_RESERVED_M 0x1 |
| |
| |
| /* -- For AUXPGA_LR_GAIN */ |
| #define TIMPANI_A_AUXPGA_LR_GAIN (0x38) |
| #define TIMPANI_AUXPGA_LR_GAIN_RWC "RW" |
| #define TIMPANI_AUXPGA_LR_GAIN_POR 0xaa |
| #define TIMPANI_AUXPGA_LR_GAIN_S 0 |
| #define TIMPANI_AUXPGA_LR_GAIN_M 0xFF |
| |
| |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_S 4 |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_M 0xF0 |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_30DB 0x0 |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_27DB 0x1 |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_24DB 0x2 |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_21DB 0x3 |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_18DB 0x4 |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_15DB 0x5 |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_12DB 0x6 |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_9_0DB 0x7 |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_6_0DB 0x8 |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_3_0DB 0x9 |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_0_0DB 0xA |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_3_0DB 0xB |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_6_0DB 0xC |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_9_0DB 0xD |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_12_0DB_1 0xE |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_12_0DB_2 0xF |
| |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_S 0 |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_M 0xF |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_30DB 0x0 |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_27DB 0x1 |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_24DB 0x2 |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_21DB 0x3 |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_18DB 0x4 |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_15DB 0x5 |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_12DB 0x6 |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_9_0DB 0x7 |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_6_0DB 0x8 |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_3_0DB 0x9 |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_0_0DB 0xA |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_3_0DB 0xB |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_6_0DB 0xC |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_9_0DB 0xD |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_12_0DB_1 0xE |
| #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_12_0DB_2 0xF |
| |
| |
| /* -- For PA_AUXO_EARPA_CONN */ |
| #define TIMPANI_A_PA_AUXO_EARPA_CONN (0x39) |
| #define TIMPANI_PA_AUXO_EARPA_CONN_RWC "RW" |
| #define TIMPANI_PA_AUXO_EARPA_CONN_POR 0 |
| #define TIMPANI_PA_AUXO_EARPA_CONN_S 0 |
| #define TIMPANI_PA_AUXO_EARPA_CONN_M 0xFF |
| |
| |
| #define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_AUXPGA_L_CONN_S 7 |
| #define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_AUXPGA_L_CONN_M 0x80 |
| #define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_AUXPGA_L_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_AUXPGA_L_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_IDAC_L_CONN_S 6 |
| #define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_IDAC_L_CONN_M 0x40 |
| #define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_IDAC_L_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_IDAC_L_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_S 5 |
| #define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_M 0x20 |
| #define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_PA_AUXO_EARPA_CONN_RESERVED_S 4 |
| #define TIMPANI_PA_AUXO_EARPA_CONN_RESERVED_M 0x10 |
| |
| #define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_S 3 |
| #define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_M 0x8 |
| #define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_V_3_52DB 0x1 |
| #define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_V_2_02DB 0x0 |
| |
| #define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_S 2 |
| #define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_M 0x4 |
| #define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_S 1 |
| #define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_M 0x2 |
| #define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_S 0 |
| #define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_M 0x1 |
| #define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_CONNECT 0x1 |
| |
| |
| /* -- For PA_LINE_ST_CONN */ |
| #define TIMPANI_A_PA_LINE_ST_CONN (0x3A) |
| #define TIMPANI_PA_LINE_ST_CONN_RWC "RW" |
| #define TIMPANI_PA_LINE_ST_CONN_POR 0 |
| #define TIMPANI_PA_LINE_ST_CONN_S 0 |
| #define TIMPANI_PA_LINE_ST_CONN_M 0xFF |
| |
| |
| #define TIMPANI_PA_LINE_ST_CONN_LINE_L_AUXPGA_L_CONN_S 7 |
| #define TIMPANI_PA_LINE_ST_CONN_LINE_L_AUXPGA_L_CONN_M 0x80 |
| #define TIMPANI_PA_LINE_ST_CONN_LINE_L_AUXPGA_L_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_PA_LINE_ST_CONN_LINE_L_AUXPGA_L_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_PA_LINE_ST_CONN_LINE_L_IDAC_L_CONN_S 6 |
| #define TIMPANI_PA_LINE_ST_CONN_LINE_L_IDAC_L_CONN_M 0x40 |
| #define TIMPANI_PA_LINE_ST_CONN_LINE_L_IDAC_L_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_PA_LINE_ST_CONN_LINE_L_IDAC_L_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_S 5 |
| #define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_M 0x20 |
| #define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_PA_LINE_ST_CONN_LINE_R_AUXPGA_R_CONN_S 4 |
| #define TIMPANI_PA_LINE_ST_CONN_LINE_R_AUXPGA_R_CONN_M 0x10 |
| #define TIMPANI_PA_LINE_ST_CONN_LINE_R_AUXPGA_R_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_PA_LINE_ST_CONN_LINE_R_AUXPGA_R_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_S 3 |
| #define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_M 0x8 |
| #define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_S 2 |
| #define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_M 0x4 |
| #define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_S 0 |
| #define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_M 0x3 |
| #define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_NONE 0x0 |
| #define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_V_1_25UA 0x1 |
| #define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_V_2_5UA 0x2 |
| #define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_V_3_75UA 0x3 |
| |
| |
| /* -- For PA_LINE_MONO_CONN */ |
| #define TIMPANI_A_PA_LINE_MONO_CONN (0x3B) |
| #define TIMPANI_PA_LINE_MONO_CONN_RWC "RW" |
| #define TIMPANI_PA_LINE_MONO_CONN_POR 0 |
| #define TIMPANI_PA_LINE_MONO_CONN_S 0 |
| #define TIMPANI_PA_LINE_MONO_CONN_M 0xFF |
| |
| |
| #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_CONN_S 7 |
| #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_CONN_M 0x80 |
| #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_CONN_S 6 |
| #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_CONN_M 0x40 |
| #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_S 5 |
| #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_M 0x20 |
| #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_INV_CONN_S 4 |
| #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_INV_CONN_M 0x10 |
| #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_INV_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_INV_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_S 3 |
| #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_M 0x8 |
| #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_S 2 |
| #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_M 0x4 |
| #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_S 0 |
| #define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_M 0x3 |
| #define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_NONE 0x0 |
| #define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_V_1_25UA 0x1 |
| #define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_V_2_5UA 0x2 |
| #define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_V_3_75UA 0x3 |
| |
| |
| /* -- For PA_HPH_ST_CONN */ |
| #define TIMPANI_A_PA_HPH_ST_CONN (0x3C) |
| #define TIMPANI_PA_HPH_ST_CONN_RWC "RW" |
| #define TIMPANI_PA_HPH_ST_CONN_POR 0 |
| #define TIMPANI_PA_HPH_ST_CONN_S 0 |
| #define TIMPANI_PA_HPH_ST_CONN_M 0xFF |
| |
| |
| #define TIMPANI_PA_HPH_ST_CONN_HPH_L_AUXPGA_L_CONN_S 7 |
| #define TIMPANI_PA_HPH_ST_CONN_HPH_L_AUXPGA_L_CONN_M 0x80 |
| #define TIMPANI_PA_HPH_ST_CONN_HPH_L_AUXPGA_L_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_PA_HPH_ST_CONN_HPH_L_AUXPGA_L_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_PA_HPH_ST_CONN_HPH_L_IDAC_L_CONN_S 6 |
| #define TIMPANI_PA_HPH_ST_CONN_HPH_L_IDAC_L_CONN_M 0x40 |
| #define TIMPANI_PA_HPH_ST_CONN_HPH_L_IDAC_L_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_PA_HPH_ST_CONN_HPH_L_IDAC_L_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_S 5 |
| #define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_M 0x20 |
| #define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_PA_HPH_ST_CONN_HPH_R_AUXPGA_R_CONN_S 4 |
| #define TIMPANI_PA_HPH_ST_CONN_HPH_R_AUXPGA_R_CONN_M 0x10 |
| #define TIMPANI_PA_HPH_ST_CONN_HPH_R_AUXPGA_R_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_PA_HPH_ST_CONN_HPH_R_AUXPGA_R_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_S 3 |
| #define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_M 0x8 |
| #define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_S 2 |
| #define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_M 0x4 |
| #define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_S 1 |
| #define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_M 0x2 |
| #define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_DISABLE 0x1 |
| #define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_ENABLE 0x0 |
| |
| #define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_S 0 |
| #define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_M 0x1 |
| #define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_DISABLE 0x1 |
| #define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_ENABLE 0x0 |
| |
| |
| /* -- For PA_HPH_MONO_CONN */ |
| #define TIMPANI_A_PA_HPH_MONO_CONN (0x3D) |
| #define TIMPANI_PA_HPH_MONO_CONN_RWC "RW" |
| #define TIMPANI_PA_HPH_MONO_CONN_POR 0 |
| #define TIMPANI_PA_HPH_MONO_CONN_S 0 |
| #define TIMPANI_PA_HPH_MONO_CONN_M 0xFF |
| |
| |
| #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_CONN_S 7 |
| #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_CONN_M 0x80 |
| #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_CONN_S 6 |
| #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_CONN_M 0x40 |
| #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_S 5 |
| #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_M 0x20 |
| #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_INV_CONN_S 4 |
| #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_INV_CONN_M 0x10 |
| #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_INV_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_INV_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_S 3 |
| #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_M 0x8 |
| #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_S 2 |
| #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_M 0x4 |
| #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_PA_HPH_MONO_CONN_RESERVED_S 0 |
| #define TIMPANI_PA_HPH_MONO_CONN_RESERVED_M 0x3 |
| |
| |
| /* -- For PA_CLASSD_CONN */ |
| #define TIMPANI_A_PA_CLASSD_CONN (0x3E) |
| #define TIMPANI_PA_CLASSD_CONN_RWC "RW" |
| #define TIMPANI_PA_CLASSD_CONN_POR 0 |
| #define TIMPANI_PA_CLASSD_CONN_S 0 |
| #define TIMPANI_PA_CLASSD_CONN_M 0xFF |
| |
| |
| #define TIMPANI_PA_CLASSD_CONN_CLASSD_CDAC_CONN_S 7 |
| #define TIMPANI_PA_CLASSD_CONN_CLASSD_CDAC_CONN_M 0x80 |
| #define TIMPANI_PA_CLASSD_CONN_CLASSD_CDAC_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_PA_CLASSD_CONN_CLASSD_CDAC_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_PA_CLASSD_CONN_CLASSD_IDAC_CONN_S 6 |
| #define TIMPANI_PA_CLASSD_CONN_CLASSD_IDAC_CONN_M 0x40 |
| #define TIMPANI_PA_CLASSD_CONN_CLASSD_IDAC_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_PA_CLASSD_CONN_CLASSD_IDAC_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_S 5 |
| #define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_M 0x20 |
| #define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_PA_CLASSD_CONN_CLASSD_PA_MODE_S 4 |
| #define TIMPANI_PA_CLASSD_CONN_CLASSD_PA_MODE_M 0x10 |
| #define TIMPANI_PA_CLASSD_CONN_CLASSD_PA_MODE_MONO_DIFF 0x1 |
| #define TIMPANI_PA_CLASSD_CONN_CLASSD_PA_MODE_STEREO 0x0 |
| |
| #define TIMPANI_PA_CLASSD_CONN_RESERVED_S 0 |
| #define TIMPANI_PA_CLASSD_CONN_RESERVED_M 0xF |
| |
| |
| /* -- For PA_CNP_CTL */ |
| #define TIMPANI_A_PA_CNP_CTL (0x3F) |
| #define TIMPANI_PA_CNP_CTL_RWC "RW" |
| #define TIMPANI_PA_CNP_CTL_POR 0x07 |
| #define TIMPANI_PA_CNP_CTL_S 0 |
| #define TIMPANI_PA_CNP_CTL_M 0xFF |
| |
| |
| #define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_S 6 |
| #define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_M 0xC0 |
| #define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_1_75_NA 0x0 |
| #define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_3_5_NA_NORMAL_OP 0x1 |
| #define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_5_25_NA 0x2 |
| #define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_10_NA 0x3 |
| |
| #define TIMPANI_PA_CNP_CTL_RESERVED_S 4 |
| #define TIMPANI_PA_CNP_CTL_RESERVED_M 0x30 |
| |
| #define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_S 3 |
| #define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_M 0x8 |
| #define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_DISABLE 0x0 |
| #define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_ENABLE 0x1 |
| |
| #define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_S 0 |
| #define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_M 0x7 |
| #define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_220_V 0x0 |
| #define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_243_V 0x1 |
| #define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_266_V 0x2 |
| #define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_290_V 0x3 |
| #define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_341_V 0x4 |
| #define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_339_V 0x5 |
| #define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_365_V 0x6 |
| #define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_391_V 0x7 |
| |
| |
| /* -- For PA_CLASSD_L_CTL */ |
| #define TIMPANI_A_PA_CLASSD_L_CTL (0x40) |
| #define TIMPANI_PA_CLASSD_L_CTL_RWC "RW" |
| #define TIMPANI_PA_CLASSD_L_CTL_POR 0x08 |
| #define TIMPANI_PA_CLASSD_L_CTL_S 0 |
| #define TIMPANI_PA_CLASSD_L_CTL_M 0xFF |
| |
| |
| #define TIMPANI_PA_CLASSD_L_CTL_RESERVED_S 6 |
| #define TIMPANI_PA_CLASSD_L_CTL_RESERVED_M 0xC0 |
| |
| #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_S 5 |
| #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_M 0x20 |
| #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_NORMAL_OP 0x0 |
| #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_RESET_PA_LOGIC 0x1 |
| |
| #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_INT_RESET_S 4 |
| #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_INT_RESET_M 0x10 |
| #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_INT_RESET_NORMAL_OP 0x0 |
| #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_INT_RESET_DISCHARGE_CAPS 0x1 |
| |
| #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_S 2 |
| #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_M 0xC |
| #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_GND 0x0 |
| #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_IBIAS_X_R_REF 0x1 |
| #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_BG_VOLTAGE 0x2 |
| #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_VDD_BY_2 0x3 |
| |
| #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_S 1 |
| #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_M 0x2 |
| #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_NORMAL_OP 0x0 |
| #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_PA_OUT_TO_VDD 0x1 |
| |
| #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_S 0 |
| #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_M 0x1 |
| #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_NORMAL_OP 0x0 |
| #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_PA_OUT_TO_GND 0x1 |
| |
| |
| /* -- For PA_CLASSD_R_CTL */ |
| #define TIMPANI_A_PA_CLASSD_R_CTL (0x41) |
| #define TIMPANI_PA_CLASSD_R_CTL_RWC "RW" |
| #define TIMPANI_PA_CLASSD_R_CTL_POR 0x08 |
| #define TIMPANI_PA_CLASSD_R_CTL_S 0 |
| #define TIMPANI_PA_CLASSD_R_CTL_M 0xFF |
| |
| |
| #define TIMPANI_PA_CLASSD_R_CTL_RESERVED_S 6 |
| #define TIMPANI_PA_CLASSD_R_CTL_RESERVED_M 0xC0 |
| |
| #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_S 5 |
| #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_M 0x20 |
| #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_NORMAL_OP 0x0 |
| #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_RESET_PA_LOGIC 0x1 |
| |
| #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_INT_RESET_S 4 |
| #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_INT_RESET_M 0x10 |
| #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_INT_RESET_NORMAL_OP 0x0 |
| #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_INT_RESET_DISCHARGE_CAPS 0x1 |
| |
| #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_S 2 |
| #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_M 0xC |
| #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_GND 0x0 |
| #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_IBIAS_X_R_REF 0x1 |
| #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_BG_VOLTAGE 0x2 |
| #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_VDD_BY_2 0x3 |
| |
| #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_S 1 |
| #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_M 0x2 |
| #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_NORMAL_OP 0x0 |
| #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_PA_OUT_TO_VDD 0x1 |
| |
| #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_S 0 |
| #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_M 0x1 |
| #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_NORMAL_OP 0x0 |
| #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_PA_OUT_TO_GND 0x1 |
| |
| |
| /* -- For PA_CLASSD_INT2_CTL */ |
| #define TIMPANI_A_PA_CLASSD_INT2_CTL (0x42) |
| #define TIMPANI_PA_CLASSD_INT2_CTL_RWC "RW" |
| #define TIMPANI_PA_CLASSD_INT2_CTL_POR 0xb0 |
| #define TIMPANI_PA_CLASSD_INT2_CTL_S 0 |
| #define TIMPANI_PA_CLASSD_INT2_CTL_M 0xFF |
| |
| |
| #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_S 6 |
| #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_M 0xC0 |
| #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_5_0PF 0x0 |
| #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_7_5PF 0x1 |
| #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_10PF 0x2 |
| #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_15PF 0x3 |
| |
| #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_S 4 |
| #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_M 0x30 |
| #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_100K 0x0 |
| #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_150K 0x1 |
| #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_175K 0x2 |
| #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_200K 0x3 |
| |
| #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_S 2 |
| #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_M 0xC |
| #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_5_0PF 0x0 |
| #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_7_5PF 0x1 |
| #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_10PF 0x2 |
| #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_15PF 0x3 |
| |
| #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_S 0 |
| #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_M 0x3 |
| #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_100K 0x0 |
| #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_150K 0x1 |
| #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_175K 0x2 |
| #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_200K 0x3 |
| |
| |
| /* -- For PA_HPH_L_OCP_CLK_CTL */ |
| #define TIMPANI_A_PA_HPH_L_OCP_CLK_CTL (0x43) |
| #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_RWC "RW" |
| #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_POR 0xf2 |
| #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_S 0 |
| #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_M 0xFF |
| |
| |
| #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_DIV_2_EN_S 7 |
| #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_DIV_2_EN_M 0x80 |
| #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_DIV_2_EN_ENABLE 0x1 |
| #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_DIV_2_EN_DISABLE 0x0 |
| |
| #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_EN_S 6 |
| #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_EN_M 0x40 |
| #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_EN_ENABLE 0x1 |
| #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_EN_DISABLE 0x0 |
| |
| #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_S 4 |
| #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_M 0x30 |
| #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV2 0x0 |
| #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV4 0x1 |
| #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV6 0x2 |
| #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV8 0x3 |
| |
| #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_S 3 |
| #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_M 0x8 |
| #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_CLK_FROM_CH_2 0x1 |
| #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_CLK_FROM_CH_1 0x0 |
| |
| #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_S 2 |
| #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_M 0x4 |
| #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_ENABLE 0x1 |
| #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_DISABLE 0x0 |
| |
| #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_S 0 |
| #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_M 0x3 |
| #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_4 0x0 |
| #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_8 0x1 |
| #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_12 0x2 |
| #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_16 0x3 |
| |
| |
| /* -- For PA_CLASSD_L_SW_CTL */ |
| #define TIMPANI_A_PA_CLASSD_L_SW_CTL (0x44) |
| #define TIMPANI_PA_CLASSD_L_SW_CTL_RWC "RW" |
| #define TIMPANI_PA_CLASSD_L_SW_CTL_POR 0x37 |
| #define TIMPANI_PA_CLASSD_L_SW_CTL_S 0 |
| #define TIMPANI_PA_CLASSD_L_SW_CTL_M 0xFF |
| |
| |
| #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_S 6 |
| #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_M 0xC0 |
| #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_1 0x0 |
| #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_2 0x1 |
| #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_3 0x2 |
| #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_4 0x3 |
| |
| #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_S 4 |
| #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_M 0x30 |
| #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_3_OF_6_UNITS 0x0 |
| #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_4_OF_6_UNITS 0x1 |
| #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_5_OF_6_UNITS 0x2 |
| #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_6_OF_6_UNITS 0x3 |
| |
| #define TIMPANI_PA_CLASSD_L_SW_CTL_RESERVED_S 3 |
| #define TIMPANI_PA_CLASSD_L_SW_CTL_RESERVED_M 0x8 |
| |
| #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_S 2 |
| #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_M 0x4 |
| #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_DISABLE 0x0 |
| #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_ENABLE 0x1 |
| |
| #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_S 1 |
| #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_M 0x2 |
| #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_DISABLE 0x0 |
| #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_ENABLE 0x1 |
| |
| #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_S 0 |
| #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_M 0x1 |
| #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_POWER_GROUND 0x0 |
| #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_RST_MIDPOINT 0x1 |
| |
| /* -- For PA_CLASSD_L_OCP1 */ |
| #define TIMPANI_A_PA_CLASSD_L_OCP1 (0x45) |
| #define TIMPANI_PA_CLASSD_L_OCP1_RWC "RW" |
| #define TIMPANI_PA_CLASSD_L_OCP1_POR 0xff |
| #define TIMPANI_PA_CLASSD_L_OCP1_S 0 |
| #define TIMPANI_PA_CLASSD_L_OCP1_M 0xFF |
| |
| |
| #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_EN_S 7 |
| #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_EN_M 0x80 |
| #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_EN_DISABLE 0x0 |
| #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_EN_ENABLE 0x1 |
| |
| #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_LOCK_S 6 |
| #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_LOCK_M 0x40 |
| #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_LOCK_NEVER_LOCKS 0x0 |
| #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_LOCK_LOCKS 0x1 |
| |
| #define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_S 4 |
| #define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_M 0x30 |
| #define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_100MA_83_3MA_66_7MA_50MA 0x0 |
| #define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_133MA_111MA_88_7MA_66_7MA 0x1 |
| #define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_166MA_138MA_111MA_83_3MA 0x2 |
| #define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_200MA_166MA_133MA_100MA 0x3 |
| |
| #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_S 0 |
| #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_M 0xF |
| #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_1 0x1 |
| #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_2 0x2 |
| #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_3 0x3 |
| #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_4 0x4 |
| #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_5 0x5 |
| #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_6 0x6 |
| #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_7 0x7 |
| #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_8 0x8 |
| #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_9 0x9 |
| #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_10 0xA |
| #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_11 0xB |
| #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_12 0xC |
| #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_13 0xD |
| #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_14 0xE |
| #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_15 0xF |
| |
| /* -- For PA_CLASSD_L_OCP2 */ |
| #define TIMPANI_A_PA_CLASSD_L_OCP2 (0x46) |
| #define TIMPANI_PA_CLASSD_L_OCP2_RWC "RW" |
| #define TIMPANI_PA_CLASSD_L_OCP2_POR 0x77 |
| #define TIMPANI_PA_CLASSD_L_OCP2_S 0 |
| #define TIMPANI_PA_CLASSD_L_OCP2_M 0xFF |
| |
| |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_S 4 |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_M 0xF0 |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_255 0x0 |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_511 0x1 |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_767 0x2 |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_1023 0x3 |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_1279 0x4 |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_1535 0x5 |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_1791 0x6 |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_2047 0x7 |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_2303 0x8 |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_2559 0x9 |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_2815 0xA |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_3071 0xB |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_3327 0xC |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_3583 0xD |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_3839 0xE |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_4095 0xF |
| |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_S 0 |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_M 0xF |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_255 0x0 |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_511 0x1 |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_767 0x2 |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_1023 0x3 |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_1279 0x4 |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_1535 0x5 |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_1791 0x6 |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_2047 0x7 |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_2303 0x8 |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_2559 0x9 |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_2815 0xA |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_3071 0xB |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_3327 0xC |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_3583 0xD |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_3839 0xE |
| #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_4095 0xF |
| |
| |
| /* -- For PA_HPH_R_OCP_CLK_CTL */ |
| #define TIMPANI_A_PA_HPH_R_OCP_CLK_CTL (0x47) |
| #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_RWC "RW" |
| #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_POR 0xf2 |
| #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_S 0 |
| #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_M 0xFF |
| |
| |
| #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_DIV_2_EN_S 7 |
| #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_DIV_2_EN_M 0x80 |
| #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_DIV_2_EN_ENABLE 0x1 |
| #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_DIV_2_EN_DISABLE 0x0 |
| |
| #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_EN_S 6 |
| #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_EN_M 0x40 |
| #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_EN_ENABLE 0x1 |
| #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_EN_DISABLE 0x0 |
| |
| #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_S 4 |
| #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_M 0x30 |
| #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV2 0x0 |
| #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV4 0x1 |
| #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV6 0x2 |
| #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV8 0x3 |
| |
| #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_S 3 |
| #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_M 0x8 |
| #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_CLK_FROM_CH_2 0x1 |
| #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_CLK_FROM_CH_1 0x0 |
| |
| #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_S 2 |
| #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_M 0x4 |
| #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_ENABLE 0x1 |
| #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_DISABLE 0x0 |
| |
| #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_S 0 |
| #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_M 0x3 |
| #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_4 0x0 |
| #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_8 0x1 |
| #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_12 0x2 |
| #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_16 0x3 |
| |
| |
| /* -- For PA_CLASSD_R_SW_CTL */ |
| #define TIMPANI_A_PA_CLASSD_R_SW_CTL (0x48) |
| #define TIMPANI_PA_CLASSD_R_SW_CTL_RWC "RW" |
| #define TIMPANI_PA_CLASSD_R_SW_CTL_POR 0x37 |
| #define TIMPANI_PA_CLASSD_R_SW_CTL_S 0 |
| #define TIMPANI_PA_CLASSD_R_SW_CTL_M 0xFF |
| |
| |
| #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_S 6 |
| #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_M 0xC0 |
| #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_1 0x0 |
| #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_2 0x1 |
| #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_3 0x2 |
| #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_4 0x3 |
| |
| #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_S 4 |
| #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_M 0x30 |
| #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_3_OF_6_UNITS 0x0 |
| #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_4_OF_6_UNITS 0x1 |
| #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_5_OF_6_UNITS 0x2 |
| #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_6_OF_6_UNITS 0x3 |
| |
| #define TIMPANI_PA_CLASSD_R_SW_CTL_RESERVED_S 3 |
| #define TIMPANI_PA_CLASSD_R_SW_CTL_RESERVED_M 0x8 |
| |
| #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_S 2 |
| #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_M 0x4 |
| #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_DISABLE 0x0 |
| #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_ENABLE 0x1 |
| |
| #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_S 1 |
| #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_M 0x2 |
| #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_DISABLE 0x0 |
| #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_ENABLE 0x1 |
| |
| #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_S 0 |
| #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_M 0x1 |
| #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_POWER_GROUND 0x0 |
| #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_RST_MIDPOINT 0x1 |
| |
| |
| /* -- For PA_CLASSD_R_OCP1 */ |
| #define TIMPANI_A_PA_CLASSD_R_OCP1 (0x49) |
| #define TIMPANI_PA_CLASSD_R_OCP1_RWC "RW" |
| #define TIMPANI_PA_CLASSD_R_OCP1_POR 0xff |
| #define TIMPANI_PA_CLASSD_R_OCP1_S 0 |
| #define TIMPANI_PA_CLASSD_R_OCP1_M 0xFF |
| |
| |
| #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_EN_S 7 |
| #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_EN_M 0x80 |
| #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_EN_DISABLE 0x0 |
| #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_EN_ENABLE 0x1 |
| |
| #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_LOCK_S 6 |
| #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_LOCK_M 0x40 |
| #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_LOCK_NEVER_LOCKS 0x0 |
| #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_LOCK_LOCKS 0x1 |
| |
| #define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_S 4 |
| #define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_M 0x30 |
| #define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_100MA_83_3MA_66_7MA_50MA 0x0 |
| #define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_133MA_111MA_88_7MA_66_7MA 0x1 |
| #define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_166MA_138MA_111MA_83_3MA 0x2 |
| #define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_200MA_166MA_133MA_100MA 0x3 |
| |
| #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_S 0 |
| #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_M 0xF |
| #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_1 0x1 |
| #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_2 0x2 |
| #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_3 0x3 |
| #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_4 0x4 |
| #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_5 0x5 |
| #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_6 0x6 |
| #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_7 0x7 |
| #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_8 0x8 |
| #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_9 0x9 |
| #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_10 0xA |
| #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_11 0xB |
| #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_12 0xC |
| #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_13 0xD |
| #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_14 0xE |
| #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_15 0xF |
| |
| |
| /* -- For PA_CLASSD_R_OCP2 */ |
| #define TIMPANI_A_PA_CLASSD_R_OCP2 (0x4A) |
| #define TIMPANI_PA_CLASSD_R_OCP2_RWC "RW" |
| #define TIMPANI_PA_CLASSD_R_OCP2_POR 0x77 |
| #define TIMPANI_PA_CLASSD_R_OCP2_S 0 |
| #define TIMPANI_PA_CLASSD_R_OCP2_M 0xFF |
| |
| |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_S 4 |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_M 0xF0 |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_255 0x0 |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_511 0x1 |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_767 0x2 |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_1023 0x3 |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_1279 0x4 |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_1535 0x5 |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_1791 0x6 |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_2047 0x7 |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_2303 0x8 |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_2559 0x9 |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_2815 0xA |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_3071 0xB |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_3327 0xC |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_3583 0xD |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_3839 0xE |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_4095 0xF |
| |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_S 0 |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_M 0xF |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_255 0x0 |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_511 0x1 |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_767 0x2 |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_1023 0x3 |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_1279 0x4 |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_1535 0x5 |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_1791 0x6 |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_2047 0x7 |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_2303 0x8 |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_2559 0x9 |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_2815 0xA |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_3071 0xB |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_3327 0xC |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_3583 0xD |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_3839 0xE |
| #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_4095 0xF |
| |
| |
| /* -- For PA_HPH_CTL1 */ |
| #define TIMPANI_A_PA_HPH_CTL1 (0x4B) |
| #define TIMPANI_PA_HPH_CTL1_RWC "RW" |
| #define TIMPANI_PA_HPH_CTL1_POR 0x44 |
| #define TIMPANI_PA_HPH_CTL1_S 0 |
| #define TIMPANI_PA_HPH_CTL1_M 0xFF |
| |
| |
| #define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_S 4 |
| #define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_M 0xF0 |
| #define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_400PER 0x1 |
| #define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_200PER 0x2 |
| #define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_133PER 0x3 |
| #define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_100PER 0x4 |
| #define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_66PER 0x6 |
| #define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_50PER 0x8 |
| #define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_33PER 0xC |
| |
| #define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_S 3 |
| #define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_M 0x8 |
| #define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_DISABLE 0x0 |
| #define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_ENABLE 0x1 |
| |
| #define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_S 0 |
| #define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_M 0x7 |
| #define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_300MA 0x0 |
| #define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_350MA 0x2 |
| #define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_365MA 0x3 |
| #define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_150MA 0x4 |
| #define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_190MA 0x6 |
| #define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_220MA 0x7 |
| |
| |
| /* -- For PA_HPH_CTL2 */ |
| #define TIMPANI_A_PA_HPH_CTL2 (0x4C) |
| #define TIMPANI_PA_HPH_CTL2_RWC "RW" |
| #define TIMPANI_PA_HPH_CTL2_POR 0xC8 |
| #define TIMPANI_PA_HPH_CTL2_S 0 |
| #define TIMPANI_PA_HPH_CTL2_M 0xFF |
| |
| |
| #define TIMPANI_PA_HPH_CTL2_HPH_SW_VNEG_CTL_S 7 |
| #define TIMPANI_PA_HPH_CTL2_HPH_SW_VNEG_CTL_M 0x80 |
| #define TIMPANI_PA_HPH_CTL2_HPH_SW_VNEG_CTL_VNEG 0x1 |
| #define TIMPANI_PA_HPH_CTL2_HPH_SW_VNEG_CTL_VSS 0x0 |
| |
| #define TIMPANI_PA_HPH_CTL2_HPH_VNEG_PS_GAIN_S 6 |
| #define TIMPANI_PA_HPH_CTL2_HPH_VNEG_PS_GAIN_M 0x40 |
| #define TIMPANI_PA_HPH_CTL2_HPH_VNEG_PS_GAIN_V_1_5 0x1 |
| #define TIMPANI_PA_HPH_CTL2_HPH_VNEG_PS_GAIN_V_2_5 0x0 |
| |
| #define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_S 5 |
| #define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_M 0x20 |
| #define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_ENABLE 0x1 |
| #define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_DISABLE 0x0 |
| |
| #define TIMPANI_PA_HPH_CTL2_HPH_OCP_EN_S 4 |
| #define TIMPANI_PA_HPH_CTL2_HPH_OCP_EN_M 0x10 |
| #define TIMPANI_PA_HPH_CTL2_HPH_OCP_EN_ENABLE 0x1 |
| #define TIMPANI_PA_HPH_CTL2_HPH_OCP_EN_DISABLE 0x0 |
| |
| #define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_S 2 |
| #define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_M 0xC |
| #define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_GROUND 0x0 |
| #define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_IBIAS_ON_RESISTOR 0x1 |
| #define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_BG 0x2 |
| #define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_AVDD_BY_2 0x3 |
| |
| #define TIMPANI_PA_HPH_CTL2_HPH_OUT_SHUNT_EN_S 1 |
| #define TIMPANI_PA_HPH_CTL2_HPH_OUT_SHUNT_EN_M 0x2 |
| #define TIMPANI_PA_HPH_CTL2_HPH_OUT_SHUNT_EN_DISABLE 0x0 |
| #define TIMPANI_PA_HPH_CTL2_HPH_OUT_SHUNT_EN_ENABLE 0x1 |
| |
| #define TIMPANI_PA_HPH_CTL2_RESERVED_S 0 |
| #define TIMPANI_PA_HPH_CTL2_RESERVED_M 0x1 |
| |
| |
| /* -- For PA_LINE_AUXO_CTL */ |
| #define TIMPANI_A_PA_LINE_AUXO_CTL (0x4D) |
| #define TIMPANI_PA_LINE_AUXO_CTL_RWC "RW" |
| #define TIMPANI_PA_LINE_AUXO_CTL_POR 0x2 |
| #define TIMPANI_PA_LINE_AUXO_CTL_S 0 |
| #define TIMPANI_PA_LINE_AUXO_CTL_M 0xFF |
| |
| |
| #define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_S 6 |
| #define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_M 0xC0 |
| #define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_1_75NA 0x0 |
| #define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_3_5NA 0x1 |
| #define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_5_25NA 0x2 |
| #define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_10NA 0x3 |
| |
| #define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_S 4 |
| #define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_M 0x30 |
| #define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_60UA 0x0 |
| #define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_30UA_1 0x1 |
| #define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_30UA_2 0x2 |
| #define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_15UA 0x3 |
| |
| #define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_S 2 |
| #define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_M 0xC |
| #define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_60UA 0x0 |
| #define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_30UA_1 0x1 |
| #define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_30UA_2 0x2 |
| #define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_15UA 0x3 |
| |
| #define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_S 0 |
| #define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_M 0x3 |
| #define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_VSSA 0x0 |
| #define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_BG 0x2 |
| #define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_VDDA_BY_2 0x3 |
| |
| |
| /* -- For PA_AUXO_EARPA_CTL */ |
| #define TIMPANI_A_PA_AUXO_EARPA_CTL (0x4E) |
| #define TIMPANI_PA_AUXO_EARPA_CTL_RWC "RW" |
| #define TIMPANI_PA_AUXO_EARPA_CTL_POR 0xe |
| #define TIMPANI_PA_AUXO_EARPA_CTL_S 0 |
| #define TIMPANI_PA_AUXO_EARPA_CTL_M 0xFF |
| |
| |
| #define TIMPANI_PA_AUXO_EARPA_CTL_RESERVED_S 6 |
| #define TIMPANI_PA_AUXO_EARPA_CTL_RESERVED_M 0xC0 |
| |
| #define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_S 4 |
| #define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_M 0x30 |
| #define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_60UA 0x0 |
| #define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_30UA 0x1 |
| #define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_30UA_SAME_AS_01 0x2 |
| #define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_15UA 0x3 |
| |
| #define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_S 3 |
| #define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_M 0x8 |
| #define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_NEG_4_5DB 0x1 |
| #define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_NEG_3_0DB 0x0 |
| |
| #define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_S 1 |
| #define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_M 0x6 |
| #define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_12_5UA 0x0 |
| #define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_10_0UA 0x1 |
| #define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_7_5UA 0x2 |
| #define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_5_0UA 0x3 |
| |
| #define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_S 0 |
| #define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_M 0x1 |
| #define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_BG 0x1 |
| #define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_LOCAL_VCM 0x0 |
| |
| |
| /* -- For PA_EARO_CTL */ |
| #define TIMPANI_A_PA_EARO_CTL (0x4F) |
| #define TIMPANI_PA_EARO_CTL_RWC "RW" |
| #define TIMPANI_PA_EARO_CTL_POR 0x0 |
| #define TIMPANI_PA_EARO_CTL_S 0 |
| #define TIMPANI_PA_EARO_CTL_M 0xFF |
| |
| |
| #define TIMPANI_PA_EARO_CTL_EARPA_STARTUP_S 7 |
| #define TIMPANI_PA_EARO_CTL_EARPA_STARTUP_M 0x80 |
| #define TIMPANI_PA_EARO_CTL_EARPA_STARTUP_NORMAL_OP 0x0 |
| #define TIMPANI_PA_EARO_CTL_EARPA_STARTUP_CONNECT_INPUTS_TO_GROUND 0x1 |
| |
| #define TIMPANI_PA_EARO_CTL_EARPA_BYPASS_INPUT_CM_S 6 |
| #define TIMPANI_PA_EARO_CTL_EARPA_BYPASS_INPUT_CM_M 0x40 |
| #define TIMPANI_PA_EARO_CTL_EARPA_BYPASS_INPUT_CM_NO_BYPASS 0x0 |
| #define TIMPANI_PA_EARO_CTL_EARPA_BYPASS_INPUT_CM_BYPASS 0x1 |
| |
| #define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_S 3 |
| #define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_M 0x38 |
| #define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_213UA 0x0 |
| #define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_280UA 0x1 |
| #define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_408UA_1 0x2 |
| #define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_780UA_1 0x3 |
| #define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_408UA_2 0x4 |
| #define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_530UA 0x5 |
| #define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_780UA_2 0x6 |
| #define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_1480UA 0x7 |
| |
| #define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_S 0 |
| #define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_M 0x7 |
| #define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_213UA 0x0 |
| #define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_280UA 0x1 |
| #define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_408UA_1 0x2 |
| #define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_780UA_1 0x3 |
| #define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_408UA_2 0x4 |
| #define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_530UA 0x5 |
| #define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_780UA_2 0x6 |
| #define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_1480UA 0x7 |
| |
| |
| /* -- For PA_MASTER_BIAS_CUR */ |
| #define TIMPANI_A_PA_MASTER_BIAS_CUR (0x50) |
| #define TIMPANI_PA_MASTER_BIAS_CUR_RWC "RW" |
| #define TIMPANI_PA_MASTER_BIAS_CUR_POR 0xea |
| #define TIMPANI_PA_MASTER_BIAS_CUR_S 0 |
| #define TIMPANI_PA_MASTER_BIAS_CUR_M 0xFF |
| |
| |
| #define TIMPANI_PA_MASTER_BIAS_CUR_RAMPGEN_MASTER_BIAS_CUR_S 7 |
| #define TIMPANI_PA_MASTER_BIAS_CUR_RAMPGEN_MASTER_BIAS_CUR_M 0x80 |
| #define TIMPANI_PA_MASTER_BIAS_CUR_RAMPGEN_MASTER_BIAS_CUR_V_2_5UA 0x1 |
| #define TIMPANI_PA_MASTER_BIAS_CUR_RAMPGEN_MASTER_BIAS_CUR_V_5UA 0x0 |
| |
| #define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_S 5 |
| #define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_M 0x60 |
| #define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_10UA 0x0 |
| #define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_7_5UA 0x1 |
| #define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_5_0UA 0x2 |
| #define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_2_5UA 0x3 |
| |
| #define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_S 3 |
| #define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_M 0x18 |
| #define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_6_25UA 0x0 |
| #define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_5_0UA 0x1 |
| #define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_3_75UA 0x2 |
| #define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_2_5UA 0x3 |
| |
| #define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_S 1 |
| #define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_M 0x6 |
| #define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_6_25UA 0x0 |
| #define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_5_0UA 0x1 |
| #define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_3_75UA 0x2 |
| #define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_2_5UA 0x3 |
| |
| #define TIMPANI_PA_MASTER_BIAS_CUR_RESERVED_S 0 |
| #define TIMPANI_PA_MASTER_BIAS_CUR_RESERVED_M 0x1 |
| |
| |
| /* -- For PA_CLASSD_SC_STATUS */ |
| #define TIMPANI_A_PA_CLASSD_SC_STATUS (0x51) |
| #define TIMPANI_PA_CLASSD_SC_STATUS_RWC "R" |
| #define TIMPANI_PA_CLASSD_SC_STATUS_POR 0 |
| #define TIMPANI_PA_CLASSD_SC_STATUS_S 0 |
| #define TIMPANI_PA_CLASSD_SC_STATUS_M 0xFF |
| |
| |
| #define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_SC_DET_S 7 |
| #define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_SC_DET_M 0x80 |
| #define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_SC_DET_NORMAL_OP 0x0 |
| #define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_SC_DET_SC_DET 0x1 |
| |
| #define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_PWR_STAGE_HI_Z_S 6 |
| #define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_PWR_STAGE_HI_Z_M 0x40 |
| #define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_PWR_STAGE_HI_Z_NORMAL_OP 0x0 |
| #define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_PWR_STAGE_HI_Z_POWER_STAGE_OFF 0x1 |
| |
| #define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_1_S 4 |
| #define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_1_M 0x30 |
| |
| #define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_S 3 |
| #define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_M 0x8 |
| #define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_NORMAL_OP 0x0 |
| #define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_SC_DET 0x1 |
| |
| #define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_S 2 |
| #define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_M 0x4 |
| #define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_NORMAL_OP 0x0 |
| #define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_POWER_STAGE_OFF 0x1 |
| |
| #define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_2_S 1 |
| #define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_2_M 0x2 |
| |
| #define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_S 0 |
| #define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_M 0x1 |
| |
| |
| /* -- For PA_HPH_SC_STATUS */ |
| #define TIMPANI_A_PA_HPH_SC_STATUS (0x52) |
| #define TIMPANI_PA_HPH_SC_STATUS_RWC "R" |
| #define TIMPANI_PA_HPH_SC_STATUS_POR 0 |
| #define TIMPANI_PA_HPH_SC_STATUS_S 0 |
| #define TIMPANI_PA_HPH_SC_STATUS_M 0xFF |
| |
| |
| #define TIMPANI_PA_HPH_SC_STATUS_HPH_L_SC_DET_S 7 |
| #define TIMPANI_PA_HPH_SC_STATUS_HPH_L_SC_DET_M 0x80 |
| #define TIMPANI_PA_HPH_SC_STATUS_HPH_L_SC_DET_NORMAL_OP 0x0 |
| #define TIMPANI_PA_HPH_SC_STATUS_HPH_L_SC_DET_SC_DET 0x1 |
| |
| #define TIMPANI_PA_HPH_SC_STATUS_RESERVED_1_S 4 |
| #define TIMPANI_PA_HPH_SC_STATUS_RESERVED_1_M 0x70 |
| |
| #define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_S 3 |
| #define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_M 0x8 |
| #define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_NORMAL_OP 0x0 |
| #define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_SC_DET 0x1 |
| |
| #define TIMPANI_PA_HPH_SC_STATUS_RESERVED_2_S 2 |
| #define TIMPANI_PA_HPH_SC_STATUS_RESERVED_2_M 0x4 |
| |
| #define TIMPANI_PA_HPH_SC_STATUS_RESERVED_S 0 |
| #define TIMPANI_PA_HPH_SC_STATUS_RESERVED_M 0x3 |
| |
| |
| /* -- For ATEST_EN */ |
| #define TIMPANI_A_ATEST_EN (0x53) |
| #define TIMPANI_ATEST_EN_RWC "RW" |
| #define TIMPANI_ATEST_EN_POR 0 |
| #define TIMPANI_ATEST_EN_S 0 |
| #define TIMPANI_ATEST_EN_M 0xFF |
| |
| |
| #define TIMPANI_ATEST_EN_ATEST_EN_S 7 |
| #define TIMPANI_ATEST_EN_ATEST_EN_M 0x80 |
| #define TIMPANI_ATEST_EN_ATEST_EN_DISABLE 0x0 |
| #define TIMPANI_ATEST_EN_ATEST_EN_ENABLE 0x1 |
| |
| #define TIMPANI_ATEST_EN_RESERVED_S 0 |
| #define TIMPANI_ATEST_EN_RESERVED_M 0x7F |
| |
| |
| /* -- For ATEST_TSHKADC */ |
| #define TIMPANI_A_ATEST_TSHKADC (0x54) |
| #define TIMPANI_ATEST_TSHKADC_RWC "RW" |
| #define TIMPANI_ATEST_TSHKADC_POR 0 |
| #define TIMPANI_ATEST_TSHKADC_S 0 |
| #define TIMPANI_ATEST_TSHKADC_M 0xFF |
| |
| |
| #define TIMPANI_ATEST_TSHKADC_RESERVED_S 4 |
| #define TIMPANI_ATEST_TSHKADC_RESERVED_M 0xF0 |
| |
| #define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_S 2 |
| #define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_M 0xC |
| #define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_MUX1 0x1 |
| #define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_MUX2 0x2 |
| #define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_MUX3 0x3 |
| |
| #define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_S 0 |
| #define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_M 0x3 |
| #define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_MUX1 0x1 |
| #define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_MUX2 0x2 |
| #define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_MUX3 0x3 |
| |
| |
| /* -- For ATEST_TXADC13 */ |
| #define TIMPANI_A_ATEST_TXADC13 (0x55) |
| #define TIMPANI_ATEST_TXADC13_RWC "RW" |
| #define TIMPANI_ATEST_TXADC13_POR 0 |
| #define TIMPANI_ATEST_TXADC13_S 0 |
| #define TIMPANI_ATEST_TXADC13_M 0xFF |
| |
| |
| #define TIMPANI_ATEST_TXADC13_RESERVED_S 7 |
| #define TIMPANI_ATEST_TXADC13_RESERVED_M 0x80 |
| |
| #define TIMPANI_ATEST_TXADC13_ATEST_SEL_L_S 6 |
| #define TIMPANI_ATEST_TXADC13_ATEST_SEL_L_M 0x40 |
| #define TIMPANI_ATEST_TXADC13_ATEST_SEL_L_TXADC1 0x0 |
| #define TIMPANI_ATEST_TXADC13_ATEST_SEL_L_TXADC3 0x1 |
| |
| #define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_S 3 |
| #define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_M 0x38 |
| #define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_ICMP1_TO_ATEST1 0x1 |
| #define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_IOTA2_TO_ATEST1 0x2 |
| #define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_IOTA1_TO_ATEST1 0x3 |
| #define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_VICM_TO_ATEST1 0x4 |
| #define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_VTH_P_TO_ATEST1 0x5 |
| #define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_VREFP_TO_ATEST1 0x6 |
| |
| #define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_S 0 |
| #define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_M 0x7 |
| #define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_IDACREF_TO_ATEST2 0x1 |
| #define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_IB_10U_TO_ATEST2 0x2 |
| #define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_VREFMID_TO_ATEST2 0x3 |
| #define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_VOCM_TO_ATEST2 0x4 |
| #define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_VTH_N_TO_ATEST2 0x5 |
| #define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_VREFN_TO_ATEST2 0x6 |
| |
| |
| /* -- For ATEST_TXADC24 */ |
| #define TIMPANI_A_ATEST_TXADC24 (0x56) |
| #define TIMPANI_ATEST_TXADC24_RWC "RW" |
| #define TIMPANI_ATEST_TXADC24_POR 0 |
| #define TIMPANI_ATEST_TXADC24_S 0 |
| #define TIMPANI_ATEST_TXADC24_M 0xFF |
| |
| |
| #define TIMPANI_ATEST_TXADC24_RESERVED_S 7 |
| #define TIMPANI_ATEST_TXADC24_RESERVED_M 0x80 |
| |
| #define TIMPANI_ATEST_TXADC24_ATEST_SEL_R_S 6 |
| #define TIMPANI_ATEST_TXADC24_ATEST_SEL_R_M 0x40 |
| #define TIMPANI_ATEST_TXADC24_ATEST_SEL_R_TXADC1 0x0 |
| #define TIMPANI_ATEST_TXADC24_ATEST_SEL_R_TXADC3 0x1 |
| |
| #define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_S 3 |
| #define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_M 0x38 |
| #define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_ICMP1_TO_ATEST1 0x1 |
| #define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_IOTA2_TO_ATEST1 0x2 |
| #define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_IOTA1_TO_ATEST1 0x3 |
| #define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_VICM_TO_ATEST1 0x4 |
| #define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_VTH_P_TO_ATEST1 0x5 |
| #define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_VREFP_TO_ATEST1 0x6 |
| |
| #define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_S 0 |
| #define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_M 0x7 |
| #define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_IDACREF_TO_ATEST2 0x1 |
| #define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_IB_10U_TO_ATEST2 0x2 |
| #define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_VREFMID_TO_ATEST2 0x3 |
| #define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_VOCM_TO_ATEST2 0x4 |
| #define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_VTH_N_TO_ATEST2 0x5 |
| #define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_VREFN_TO_ATEST2 0x6 |
| |
| |
| /* -- For ATEST_AUXPGA */ |
| #define TIMPANI_A_ATEST_AUXPGA (0x57) |
| #define TIMPANI_ATEST_AUXPGA_RWC "RW" |
| #define TIMPANI_ATEST_AUXPGA_POR 0 |
| #define TIMPANI_ATEST_AUXPGA_S 0 |
| #define TIMPANI_ATEST_AUXPGA_M 0xFF |
| |
| |
| #define TIMPANI_ATEST_AUXPGA_ATEST1_AUXPGA_INT_VCM_CONN_S 7 |
| #define TIMPANI_ATEST_AUXPGA_ATEST1_AUXPGA_INT_VCM_CONN_M 0x80 |
| #define TIMPANI_ATEST_AUXPGA_ATEST1_AUXPGA_INT_VCM_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_ATEST_AUXPGA_ATEST1_AUXPGA_INT_VCM_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMI_VDD_CONN_S 6 |
| #define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMI_VDD_CONN_M 0x40 |
| #define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMI_VDD_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMI_VDD_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_S 5 |
| #define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_M 0x20 |
| #define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_R_CONN_S 4 |
| #define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_R_CONN_M 0x10 |
| #define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_R_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_R_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_S 3 |
| #define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_M 0x8 |
| #define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_ATEST_AUXPGA_RESERVED_S 0 |
| #define TIMPANI_ATEST_AUXPGA_RESERVED_M 0x7 |
| |
| |
| /* -- For ATEST_CDAC */ |
| #define TIMPANI_A_ATEST_CDAC (0x58) |
| #define TIMPANI_ATEST_CDAC_RWC "RW" |
| #define TIMPANI_ATEST_CDAC_POR 0 |
| #define TIMPANI_ATEST_CDAC_S 0 |
| #define TIMPANI_ATEST_CDAC_M 0xFF |
| |
| |
| #define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_IN_CONN_S 7 |
| #define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_IN_CONN_M 0x80 |
| #define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_IN_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_IN_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_OUT_CONN_S 6 |
| #define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_OUT_CONN_M 0x40 |
| #define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_OUT_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_OUT_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_S 5 |
| #define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_M 0x20 |
| #define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_ATEST_CDAC_ATEST_FILTER_R_OUT_CONN_S 4 |
| #define TIMPANI_ATEST_CDAC_ATEST_FILTER_R_OUT_CONN_M 0x10 |
| #define TIMPANI_ATEST_CDAC_ATEST_FILTER_R_OUT_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_ATEST_CDAC_ATEST_FILTER_R_OUT_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_S 2 |
| #define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_M 0xC |
| #define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_TEST1 0x1 |
| #define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_TEST2 0x2 |
| #define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_TEST3 0x3 |
| |
| #define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_S 0 |
| #define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_M 0x3 |
| #define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_TEST1 0x1 |
| #define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_TEST2 0x2 |
| #define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_TEST3 0x3 |
| |
| |
| /* -- For ATEST_IDAC */ |
| #define TIMPANI_A_ATEST_IDAC (0x59) |
| #define TIMPANI_ATEST_IDAC_RWC "RW" |
| #define TIMPANI_ATEST_IDAC_POR 0 |
| #define TIMPANI_ATEST_IDAC_S 0 |
| #define TIMPANI_ATEST_IDAC_M 0xFF |
| |
| |
| #define TIMPANI_ATEST_IDAC_ATEST1_LR_CONN_S 7 |
| #define TIMPANI_ATEST_IDAC_ATEST1_LR_CONN_M 0x80 |
| #define TIMPANI_ATEST_IDAC_ATEST1_LR_CONN_RIGHT 0x1 |
| #define TIMPANI_ATEST_IDAC_ATEST1_LR_CONN_LEFT 0x0 |
| |
| #define TIMPANI_ATEST_IDAC_ATEST1_CONN_S 4 |
| #define TIMPANI_ATEST_IDAC_ATEST1_CONN_M 0x70 |
| #define TIMPANI_ATEST_IDAC_ATEST1_CONN_IDAC_NEG_OUT 0x7 |
| #define TIMPANI_ATEST_IDAC_ATEST1_CONN_CT_FILTER_POS_OUT 0x6 |
| #define TIMPANI_ATEST_IDAC_ATEST1_CONN_CT_FILTER_IBIAS 0x5 |
| #define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_1 0x4 |
| #define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_2 0x3 |
| #define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_3 0x2 |
| #define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_4 0x1 |
| #define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_5 0x0 |
| |
| #define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_S 3 |
| #define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_M 0x8 |
| #define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_RIGHT 0x1 |
| #define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_LEFT 0x0 |
| |
| #define TIMPANI_ATEST_IDAC_ATEST2_CONN_S 0 |
| #define TIMPANI_ATEST_IDAC_ATEST2_CONN_M 0x7 |
| #define TIMPANI_ATEST_IDAC_ATEST2_CONN_IDAC_POS_OUT 0x7 |
| #define TIMPANI_ATEST_IDAC_ATEST2_CONN_CT_FILTER_NEG_OUT 0x6 |
| #define TIMPANI_ATEST_IDAC_ATEST2_CONN_IDAC_IBIAS 0x5 |
| #define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_1 0x4 |
| #define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_2 0x3 |
| #define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_3 0x2 |
| #define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_4 0x1 |
| #define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_5 0x0 |
| |
| |
| /* -- For ATEST_PA1 */ |
| #define TIMPANI_A_ATEST_PA1 (0x5A) |
| #define TIMPANI_ATEST_PA1_RWC "RW" |
| #define TIMPANI_ATEST_PA1_POR 0 |
| #define TIMPANI_ATEST_PA1_S 0 |
| #define TIMPANI_ATEST_PA1_M 0xFF |
| |
| |
| #define TIMPANI_ATEST_PA1_ATEST_EARPA_FSV_NP_CONN_S 7 |
| #define TIMPANI_ATEST_PA1_ATEST_EARPA_FSV_NP_CONN_M 0x80 |
| #define TIMPANI_ATEST_PA1_ATEST_EARPA_FSV_NP_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_ATEST_PA1_ATEST_EARPA_FSV_NP_CONN_EN 0x1 |
| |
| #define TIMPANI_ATEST_PA1_ATEST_EARPA_NCASC_NMIRR_CONN_S 6 |
| #define TIMPANI_ATEST_PA1_ATEST_EARPA_NCASC_NMIRR_CONN_M 0x40 |
| #define TIMPANI_ATEST_PA1_ATEST_EARPA_NCASC_NMIRR_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_ATEST_PA1_ATEST_EARPA_NCASC_NMIRR_CONN_EN 0x1 |
| |
| #define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_S 5 |
| #define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_M 0x20 |
| #define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_EN 0x1 |
| |
| #define TIMPANI_ATEST_PA1_ATEST_EARPA_VCM_PTAIL1_CONN_S 4 |
| #define TIMPANI_ATEST_PA1_ATEST_EARPA_VCM_PTAIL1_CONN_M 0x10 |
| #define TIMPANI_ATEST_PA1_ATEST_EARPA_VCM_PTAIL1_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_ATEST_PA1_ATEST_EARPA_VCM_PTAIL1_CONN_EN 0x1 |
| |
| #define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_S 3 |
| #define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_M 0x8 |
| #define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_EN 0x1 |
| |
| #define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_S 2 |
| #define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_M 0x4 |
| #define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_EN 0x1 |
| |
| #define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_S 1 |
| #define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_M 0x2 |
| #define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_PASS 0x0 |
| #define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_GATE 0x1 |
| |
| #define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_S 0 |
| #define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_M 0x1 |
| #define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_CONNECT 0x1 |
| |
| |
| /* -- For ATEST_CLASSD */ |
| #define TIMPANI_A_ATEST_CLASSD (0x5B) |
| #define TIMPANI_ATEST_CLASSD_RWC "RW" |
| #define TIMPANI_ATEST_CLASSD_POR 0 |
| #define TIMPANI_ATEST_CLASSD_S 0 |
| #define TIMPANI_ATEST_CLASSD_M 0xFF |
| |
| |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_S 4 |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_M 0xF0 |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_NO_CONNECT_1 0x0 |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_SC_OCP 0x1 |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_CDAC_CLK 0x2 |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_POS_CDAC 0x3 |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_BREAK_BEFORE_MAKE_OUT_CP 0x4 |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_COMP_OUT 0x5 |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_INT2_POS_OUT 0x6 |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_INT1_POS_OUT 0x7 |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_NO_CONNECT_2 0x8 |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_SC_OCP_SIGNAL 0x9 |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_CDAC_CLK 0xA |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_POS_CDAC 0xB |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_BREAK_BEFORE_MAKE_OUT_CP 0xC |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_COMP_OUT 0xD |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_INT2_POS_OUT 0xE |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_INT1_POS_OUT 0xF |
| |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_S 0 |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_M 0xF |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_NO_CONNECT_1 0x0 |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_HI_Z_OCP 0x1 |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_OCP_CLOCK 0x2 |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_NEG_CDAC 0x3 |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_BREAK_BEFORE_MAKE_OUT_CN 0x4 |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_CM_BUFF_OUT 0x5 |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_INT2_NEG_OUT 0x6 |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_INT1_NEG_OUT 0x7 |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_NO_CONNECT_2 0x8 |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_HI_Z_OCP 0x9 |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_OCP_CLOCK 0xA |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_NEGATIVE_CDAC 0xB |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_BREAK_BEFORE_MAKE_OUT_CN 0xC |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_CM_BUFF_OUT 0xD |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_INTR2_NEG_OUT 0xE |
| #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_INT1_NEG_OUT 0xF |
| |
| |
| /* -- For ATEST_LINEO_AUXO */ |
| #define TIMPANI_A_ATEST_LINEO_AUXO (0x5C) |
| #define TIMPANI_ATEST_LINEO_AUXO_RWC "RW" |
| #define TIMPANI_ATEST_LINEO_AUXO_POR 0 |
| #define TIMPANI_ATEST_LINEO_AUXO_S 0 |
| #define TIMPANI_ATEST_LINEO_AUXO_M 0xFF |
| |
| |
| #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_EN_S 7 |
| #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_EN_M 0x80 |
| #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_EN_DISABLE 0x0 |
| #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_EN_ENABLE 0x1 |
| |
| #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_VCM_CONN_S 6 |
| #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_VCM_CONN_M 0x40 |
| #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_VCM_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_VCM_CONN_CONNECT 0x1 |
| |
| #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_S 5 |
| #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_M 0x20 |
| #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_EN 0x1 |
| |
| #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NMOS_PMOS_CONN_S 4 |
| #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NMOS_PMOS_CONN_M 0x10 |
| #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NMOS_PMOS_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NMOS_PMOS_CONN_EN 01 |
| |
| #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NREFIN_STG1OP_CONN_S 3 |
| #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NREFIN_STG1OP_CONN_M 0x8 |
| #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NREFIN_STG1OP_CONN_NO_CONNECT 0x0 |
| #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NREFIN_STG1OP_CONN_EN 01 |
| |
| #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_S 2 |
| #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_M 0x4 |
| #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_DISABLE 0x0 |
| #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_EN 0x1 |
| |
| #define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_S 1 |
| #define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_M 0x2 |
| #define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_DISABLE 0x0 |
| #define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_EN 0x1 |
| |
| #define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_S 0 |
| #define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_M 0x1 |
| #define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_DISABLE 0x0 |
| #define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_EN 0x1 |
| |
| |
| /* -- For CDC_RESET_CTL */ |
| #define TIMPANI_A_CDC_RESET_CTL (0x80) |
| #define TIMPANI_CDC_RESET_CTL_RWC "RW" |
| #define TIMPANI_CDC_RESET_CTL_POR 0 |
| #define TIMPANI_CDC_RESET_CTL_S 0 |
| #define TIMPANI_CDC_RESET_CTL_M 0x7F |
| |
| |
| #define TIMPANI_CDC_RESET_CTL_ARB_SOFT_RESET_S 6 |
| #define TIMPANI_CDC_RESET_CTL_ARB_SOFT_RESET_M 0x40 |
| |
| #define TIMPANI_CDC_RESET_CTL_TX2_SOFT_RESET_R_S 5 |
| #define TIMPANI_CDC_RESET_CTL_TX2_SOFT_RESET_R_M 0x20 |
| |
| #define TIMPANI_CDC_RESET_CTL_TX2_SOFT_RESET_L_S 4 |
| #define TIMPANI_CDC_RESET_CTL_TX2_SOFT_RESET_L_M 0x10 |
| |
| #define TIMPANI_CDC_RESET_CTL_RX2_SOFT_RESET_S 3 |
| #define TIMPANI_CDC_RESET_CTL_RX2_SOFT_RESET_M 0x8 |
| |
| #define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_R_S 2 |
| #define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_R_M 0x4 |
| |
| #define TIMPANI_CDC_RESET_CTL_RX1_SOFT_RESET_S 1 |
| #define TIMPANI_CDC_RESET_CTL_RX1_SOFT_RESET_M 0x2 |
| |
| #define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_L_S 0 |
| #define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_L_M 0x1 |
| |
| |
| /* -- For CDC_RX1_CTL */ |
| #define TIMPANI_A_CDC_RX1_CTL (0x81) |
| #define TIMPANI_CDC_RX1_CTL_RWC "RW" |
| #define TIMPANI_CDC_RX1_CTL_POR 0xc |
| #define TIMPANI_CDC_RX1_CTL_S 0 |
| #define TIMPANI_CDC_RX1_CTL_M 0x3F |
| |
| |
| #define TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_R_S 5 |
| #define TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_R_M 0x20 |
| |
| #define TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_L_S 4 |
| #define TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_L_M 0x10 |
| |
| #define TIMPANI_CDC_RX1_CTL_RX1_RATE_S 2 |
| #define TIMPANI_CDC_RX1_CTL_RX1_RATE_M 0xC |
| #define TIMPANI_CDC_RX1_CTL_RX1_RATE_OSR_256 0x3 |
| #define TIMPANI_CDC_RX1_CTL_RX1_RATE_OSR_128 0x1 |
| #define TIMPANI_CDC_RX1_CTL_RX1_RATE_OSR_64 0x0 |
| |
| #define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_S 1 |
| #define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_M 0x2 |
| #define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_BR_32 0x1 |
| #define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_BR_64 0x0 |
| |
| #define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_S 0 |
| #define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_M 0x1 |
| #define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_MASTER 0x1 |
| #define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_SLAVE 0x0 |
| |
| |
| /* -- For CDC_TX_I2S_CTL */ |
| #define TIMPANI_A_CDC_TX_I2S_CTL (0x82) |
| #define TIMPANI_CDC_TX_I2S_CTL_RWC "RW" |
| #define TIMPANI_CDC_TX_I2S_CTL_POR 0xc |
| #define TIMPANI_CDC_TX_I2S_CTL_S 0 |
| #define TIMPANI_CDC_TX_I2S_CTL_M 0x3F |
| |
| |
| #define TIMPANI_CDC_TX_I2S_CTL_TX2_I2S_SD_OE_S 5 |
| #define TIMPANI_CDC_TX_I2S_CTL_TX2_I2S_SD_OE_M 0x20 |
| |
| #define TIMPANI_CDC_TX_I2S_CTL_TX1_I2S_SD_OE_S 4 |
| #define TIMPANI_CDC_TX_I2S_CTL_TX1_I2S_SD_OE_M 0x10 |
| |
| #define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_S 2 |
| #define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_M 0xC |
| #define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_OSR_256 0x3 |
| #define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_OSR_128 0x1 |
| #define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_OSR_64 0x0 |
| |
| #define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_S 1 |
| #define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_M 0x2 |
| #define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_BR_32 0x1 |
| #define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_BR_64 0x0 |
| |
| #define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_S 0 |
| #define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_M 0x1 |
| #define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_MASTER 0x1 |
| #define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_SLAVE 0x0 |
| |
| |
| /* -- For CDC_CH_CTL */ |
| #define TIMPANI_A_CDC_CH_CTL (0x83) |
| #define TIMPANI_CDC_CH_CTL_RWC "RW" |
| #define TIMPANI_CDC_CH_CTL_POR 0 |
| #define TIMPANI_CDC_CH_CTL_S 0 |
| #define TIMPANI_CDC_CH_CTL_M 0xFF |
| |
| |
| #define TIMPANI_CDC_CH_CTL_TX2_EN_R_S 7 |
| #define TIMPANI_CDC_CH_CTL_TX2_EN_R_M 0x80 |
| |
| #define TIMPANI_CDC_CH_CTL_TX2_EN_L_S 6 |
| #define TIMPANI_CDC_CH_CTL_TX2_EN_L_M 0x40 |
| |
| #define TIMPANI_CDC_CH_CTL_RX2_EN_R_S 5 |
| #define TIMPANI_CDC_CH_CTL_RX2_EN_R_M 0x20 |
| |
| #define TIMPANI_CDC_CH_CTL_RX2_EN_L_S 4 |
| #define TIMPANI_CDC_CH_CTL_RX2_EN_L_M 0x10 |
| |
| #define TIMPANI_CDC_CH_CTL_TX1_EN_R_S 3 |
| #define TIMPANI_CDC_CH_CTL_TX1_EN_R_M 0x8 |
| |
| #define TIMPANI_CDC_CH_CTL_TX1_EN_L_S 2 |
| #define TIMPANI_CDC_CH_CTL_TX1_EN_L_M 0x4 |
| |
| #define TIMPANI_CDC_CH_CTL_RX1_EN_R_S 1 |
| #define TIMPANI_CDC_CH_CTL_RX1_EN_R_M 0x2 |
| |
| #define TIMPANI_CDC_CH_CTL_RX1_EN_L_S 0 |
| #define TIMPANI_CDC_CH_CTL_RX1_EN_L_M 0x1 |
| |
| |
| /* -- For CDC_RX1LG */ |
| #define TIMPANI_A_CDC_RX1LG (0x84) |
| #define TIMPANI_CDC_RX1LG_RWC "RW" |
| #define TIMPANI_CDC_RX1LG_POR 0xac |
| #define TIMPANI_CDC_RX1LG_S 0 |
| #define TIMPANI_CDC_RX1LG_M 0xFF |
| |
| |
| #define TIMPANI_CDC_RX1LG_GAIN_S 0 |
| #define TIMPANI_CDC_RX1LG_GAIN_M 0xFF |
| |
| |
| /* -- For CDC_RX1RG */ |
| #define TIMPANI_A_CDC_RX1RG (0x85) |
| #define TIMPANI_CDC_RX1RG_RWC "RW" |
| #define TIMPANI_CDC_RX1RG_POR 0xac |
| #define TIMPANI_CDC_RX1RG_S 0 |
| #define TIMPANI_CDC_RX1RG_M 0xFF |
| |
| |
| #define TIMPANI_CDC_RX1RG_GAIN_S 0 |
| #define TIMPANI_CDC_RX1RG_GAIN_M 0xFF |
| |
| |
| /* -- For CDC_TX1LG */ |
| #define TIMPANI_A_CDC_TX1LG (0x86) |
| #define TIMPANI_CDC_TX1LG_RWC "RW" |
| #define TIMPANI_CDC_TX1LG_POR 0xac |
| #define TIMPANI_CDC_TX1LG_S 0 |
| #define TIMPANI_CDC_TX1LG_M 0xFF |
| |
| |
| #define TIMPANI_CDC_TX1LG_GAIN_S 0 |
| #define TIMPANI_CDC_TX1LG_GAIN_M 0xFF |
| |
| |
| /* -- For CDC_TX1RG */ |
| #define TIMPANI_A_CDC_TX1RG (0x87) |
| #define TIMPANI_CDC_TX1RG_RWC "RW" |
| #define TIMPANI_CDC_TX1RG_POR 0xac |
| #define TIMPANI_CDC_TX1RG_S 0 |
| #define TIMPANI_CDC_TX1RG_M 0xFF |
| |
| |
| #define TIMPANI_CDC_TX1RG_GAIN_S 0 |
| #define TIMPANI_CDC_TX1RG_GAIN_M 0xFF |
| |
| |
| /* -- For CDC_RX_PGA_TIMER */ |
| #define TIMPANI_A_CDC_RX_PGA_TIMER (0x88) |
| #define TIMPANI_CDC_RX_PGA_TIMER_RWC "RW" |
| #define TIMPANI_CDC_RX_PGA_TIMER_POR 0xff |
| #define TIMPANI_CDC_RX_PGA_TIMER_S 0 |
| #define TIMPANI_CDC_RX_PGA_TIMER_M 0xFF |
| |
| |
| #define TIMPANI_CDC_RX_PGA_TIMER_TIMER_VAL_S 0 |
| #define TIMPANI_CDC_RX_PGA_TIMER_TIMER_VAL_M 0xFF |
| |
| |
| /* -- For CDC_TX_PGA_TIMER */ |
| #define TIMPANI_A_CDC_TX_PGA_TIMER (0x89) |
| #define TIMPANI_CDC_TX_PGA_TIMER_RWC "RW" |
| #define TIMPANI_CDC_TX_PGA_TIMER_POR 0xff |
| #define TIMPANI_CDC_TX_PGA_TIMER_S 0 |
| #define TIMPANI_CDC_TX_PGA_TIMER_M 0xFF |
| |
| |
| #define TIMPANI_CDC_TX_PGA_TIMER_TIMER_VAL_S 0 |
| #define TIMPANI_CDC_TX_PGA_TIMER_TIMER_VAL_M 0xFF |
| |
| |
| /* -- For CDC_GCTL1 */ |
| #define TIMPANI_A_CDC_GCTL1 (0x8A) |
| #define TIMPANI_CDC_GCTL1_RWC "RW" |
| #define TIMPANI_CDC_GCTL1_POR 0x33 |
| #define TIMPANI_CDC_GCTL1_S 0 |
| #define TIMPANI_CDC_GCTL1_M 0xFF |
| |
| |
| #define TIMPANI_CDC_GCTL1_TX1_PGA_UPDATE_R_S 7 |
| #define TIMPANI_CDC_GCTL1_TX1_PGA_UPDATE_R_M 0x80 |
| |
| #define TIMPANI_CDC_GCTL1_TX1_PGA_UPDATE_L_S 6 |
| #define TIMPANI_CDC_GCTL1_TX1_PGA_UPDATE_L_M 0x40 |
| |
| #define TIMPANI_CDC_GCTL1_TX1_PGA_MUTE_EN_R_S 5 |
| #define TIMPANI_CDC_GCTL1_TX1_PGA_MUTE_EN_R_M 0x20 |
| |
| #define TIMPANI_CDC_GCTL1_TX1_PGA_MUTE_EN_L_S 4 |
| #define TIMPANI_CDC_GCTL1_TX1_PGA_MUTE_EN_L_M 0x10 |
| |
| #define TIMPANI_CDC_GCTL1_RX1_PGA_UPDATE_R_S 3 |
| #define TIMPANI_CDC_GCTL1_RX1_PGA_UPDATE_R_M 0x8 |
| |
| #define TIMPANI_CDC_GCTL1_RX1_PGA_UPDATE_L_S 2 |
| #define TIMPANI_CDC_GCTL1_RX1_PGA_UPDATE_L_M 0x4 |
| |
| #define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_R_S 1 |
| #define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_R_M 0x2 |
| |
| #define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_L_S 0 |
| #define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_L_M 0x1 |
| |
| |
| /* -- For CDC_TX1L_STG */ |
| #define TIMPANI_A_CDC_TX1L_STG (0x8B) |
| #define TIMPANI_CDC_TX1L_STG_RWC "RW" |
| #define TIMPANI_CDC_TX1L_STG_POR 0xac |
| #define TIMPANI_CDC_TX1L_STG_S 0 |
| #define TIMPANI_CDC_TX1L_STG_M 0xFF |
| |
| |
| #define TIMPANI_CDC_TX1L_STG_GAIN_S 0 |
| #define TIMPANI_CDC_TX1L_STG_GAIN_M 0xFF |
| |
| |
| /* -- For CDC_ST_CTL */ |
| #define TIMPANI_A_CDC_ST_CTL (0x8C) |
| #define TIMPANI_CDC_ST_CTL_RWC "RW" |
| #define TIMPANI_CDC_ST_CTL_POR 0x55 |
| #define TIMPANI_CDC_ST_CTL_S 0 |
| #define TIMPANI_CDC_ST_CTL_M 0xFF |
| |
| |
| #define TIMPANI_CDC_ST_CTL_TX2_R_SIDETONE_UPDATE_S 7 |
| #define TIMPANI_CDC_ST_CTL_TX2_R_SIDETONE_UPDATE_M 0x80 |
| |
| #define TIMPANI_CDC_ST_CTL_TX2_R_SIDETONE_MUTE_EN_S 6 |
| #define TIMPANI_CDC_ST_CTL_TX2_R_SIDETONE_MUTE_EN_M 0x40 |
| |
| #define TIMPANI_CDC_ST_CTL_TX2_L_SIDETONE_UPDATE_S 5 |
| #define TIMPANI_CDC_ST_CTL_TX2_L_SIDETONE_UPDATE_M 0x20 |
| |
| #define TIMPANI_CDC_ST_CTL_TX2_L_SIDETONE_MUTE_EN_S 4 |
| #define TIMPANI_CDC_ST_CTL_TX2_L_SIDETONE_MUTE_EN_M 0x10 |
| |
| #define TIMPANI_CDC_ST_CTL_TX1_R_SIDETONE_UPDATE_S 3 |
| #define TIMPANI_CDC_ST_CTL_TX1_R_SIDETONE_UPDATE_M 0x8 |
| |
| #define TIMPANI_CDC_ST_CTL_TX1_R_SIDETONE_MUTE_EN_S 2 |
| #define TIMPANI_CDC_ST_CTL_TX1_R_SIDETONE_MUTE_EN_M 0x4 |
| |
| #define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_UPDATE_S 1 |
| #define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_UPDATE_M 0x2 |
| |
| #define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_MUTE_EN_S 0 |
| #define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_MUTE_EN_M 0x1 |
| |
| |
| /* -- For CDC_RX1L_DCOFFSET */ |
| #define TIMPANI_A_CDC_RX1L_DCOFFSET (0x8D) |
| #define TIMPANI_CDC_RX1L_DCOFFSET_RWC "RW" |
| #define TIMPANI_CDC_RX1L_DCOFFSET_POR 0 |
| #define TIMPANI_CDC_RX1L_DCOFFSET_S 0 |
| #define TIMPANI_CDC_RX1L_DCOFFSET_M 0xFF |
| |
| |
| #define TIMPANI_CDC_RX1L_DCOFFSET_OFFSET_S 0 |
| #define TIMPANI_CDC_RX1L_DCOFFSET_OFFSET_M 0xFF |
| |
| |
| /* -- For CDC_RX1R_DCOFFSET */ |
| #define TIMPANI_A_CDC_RX1R_DCOFFSET (0x8E) |
| #define TIMPANI_CDC_RX1R_DCOFFSET_RWC "RW" |
| #define TIMPANI_CDC_RX1R_DCOFFSET_POR 0 |
| #define TIMPANI_CDC_RX1R_DCOFFSET_S 0 |
| #define TIMPANI_CDC_RX1R_DCOFFSET_M 0xFF |
| |
| |
| #define TIMPANI_CDC_RX1R_DCOFFSET_OFFSET_S 0 |
| #define TIMPANI_CDC_RX1R_DCOFFSET_OFFSET_M 0xFF |
| |
| |
| /* -- For CDC_BYPASS_CTL1 */ |
| #define TIMPANI_A_CDC_BYPASS_CTL1 (0x8F) |
| #define TIMPANI_CDC_BYPASS_CTL1_RWC "RW" |
| #define TIMPANI_CDC_BYPASS_CTL1_POR 0x2 |
| #define TIMPANI_CDC_BYPASS_CTL1_S 0 |
| #define TIMPANI_CDC_BYPASS_CTL1_M 0xF |
| |
| |
| #define TIMPANI_CDC_BYPASS_CTL1_DITHER_BP_S 3 |
| #define TIMPANI_CDC_BYPASS_CTL1_DITHER_BP_M 0x8 |
| |
| #define TIMPANI_CDC_BYPASS_CTL1_DITHER_SHAPE_SEL_S 2 |
| #define TIMPANI_CDC_BYPASS_CTL1_DITHER_SHAPE_SEL_M 0x4 |
| |
| #define TIMPANI_CDC_BYPASS_CTL1_DITHER_DLY_SEL_S 1 |
| #define TIMPANI_CDC_BYPASS_CTL1_DITHER_DLY_SEL_M 0x2 |
| |
| #define TIMPANI_CDC_BYPASS_CTL1_RX1_HPF_BP_S 0 |
| #define TIMPANI_CDC_BYPASS_CTL1_RX1_HPF_BP_M 0x1 |
| |
| |
| /* -- For CDC_PDM_CONFIG */ |
| #define TIMPANI_A_CDC_PDM_CONFIG (0x90) |
| #define TIMPANI_CDC_PDM_CONFIG_RWC "RW" |
| #define TIMPANI_CDC_PDM_CONFIG_POR 0 |
| #define TIMPANI_CDC_PDM_CONFIG_S 0 |
| #define TIMPANI_CDC_PDM_CONFIG_M 0xF |
| |
| |
| #define TIMPANI_CDC_PDM_CONFIG_PDM_SEL_S 0 |
| #define TIMPANI_CDC_PDM_CONFIG_PDM_SEL_M 0xF |
| |
| |
| /* -- For CDC_TESTMODE1 */ |
| #define TIMPANI_A_CDC_TESTMODE1 (0x91) |
| #define TIMPANI_CDC_TESTMODE1_RWC "RW" |
| #define TIMPANI_CDC_TESTMODE1_POR 0 |
| #define TIMPANI_CDC_TESTMODE1_S 0 |
| #define TIMPANI_CDC_TESTMODE1_M 0x3F |
| |
| |
| #define TIMPANI_CDC_TESTMODE1_COMP_I2C_TEST_EN_S 5 |
| #define TIMPANI_CDC_TESTMODE1_COMP_I2C_TEST_EN_M 0x20 |
| |
| #define TIMPANI_CDC_TESTMODE1_RX1_TEST_EN_R_S 4 |
| #define TIMPANI_CDC_TESTMODE1_RX1_TEST_EN_R_M 0x10 |
| |
| #define TIMPANI_CDC_TESTMODE1_RX1_TEST_EN_L_S 3 |
| #define TIMPANI_CDC_TESTMODE1_RX1_TEST_EN_L_M 0x8 |
| |
| #define TIMPANI_CDC_TESTMODE1_TX1_TEST_EN_R_S 2 |
| #define TIMPANI_CDC_TESTMODE1_TX1_TEST_EN_R_M 0x4 |
| |
| #define TIMPANI_CDC_TESTMODE1_TX1_TEST_EN_L_S 1 |
| #define TIMPANI_CDC_TESTMODE1_TX1_TEST_EN_L_M 0x2 |
| |
| #define TIMPANI_CDC_TESTMODE1_A_LOOPBACK_EN1_S 0 |
| #define TIMPANI_CDC_TESTMODE1_A_LOOPBACK_EN1_M 0x1 |
| |
| |
| /* -- For CDC_DMIC_CLK_CTL */ |
| #define TIMPANI_A_CDC_DMIC_CLK_CTL (0x92) |
| #define TIMPANI_CDC_DMIC_CLK_CTL_RWC "RW" |
| #define TIMPANI_CDC_DMIC_CLK_CTL_POR 0 |
| #define TIMPANI_CDC_DMIC_CLK_CTL_S 0 |
| #define TIMPANI_CDC_DMIC_CLK_CTL_M 0x3F |
| |
| |
| #define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_S 3 |
| #define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_M 0x38 |
| #define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_6 0x4 |
| #define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_4 0x3 |
| #define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_3 0x2 |
| #define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_2 0x1 |
| #define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_1 0x0 |
| |
| #define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_S 1 |
| #define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_M 0x6 |
| #define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_RX_MCLK2 0x2 |
| #define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_RX_MCLK1 0x1 |
| #define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_TX_MCLK 0x0 |
| |
| #define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_CLK_EN_S 0 |
| #define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_CLK_EN_M 0x1 |
| |
| |
| /* -- For CDC_ADC12_CLK_CTL */ |
| #define TIMPANI_A_CDC_ADC12_CLK_CTL (0x93) |
| #define TIMPANI_CDC_ADC12_CLK_CTL_RWC "RW" |
| #define TIMPANI_CDC_ADC12_CLK_CTL_POR 0 |
| #define TIMPANI_CDC_ADC12_CLK_CTL_S 0 |
| #define TIMPANI_CDC_ADC12_CLK_CTL_M 0xFF |
| |
| |
| #define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_S 6 |
| #define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_M 0xC0 |
| #define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_RX_MCLK2 0x2 |
| #define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_RX_MCLK1 0x1 |
| #define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_TX_MCLK 0x0 |
| |
| #define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_S 3 |
| #define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_M 0x38 |
| #define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_6 0x4 |
| #define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_4 0x3 |
| #define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_3 0x2 |
| #define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_2 0x1 |
| #define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_1 0x0 |
| |
| #define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_S 0 |
| #define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_M 0x7 |
| #define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_6 0x4 |
| #define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_4 0x3 |
| #define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_3 0x2 |
| #define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_2 0x1 |
| #define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_1 0x0 |
| |
| |
| /* -- For CDC_TX1_CTL */ |
| #define TIMPANI_A_CDC_TX1_CTL (0x94) |
| #define TIMPANI_CDC_TX1_CTL_RWC "RW" |
| #define TIMPANI_CDC_TX1_CTL_POR 0x1b |
| #define TIMPANI_CDC_TX1_CTL_S 0 |
| #define TIMPANI_CDC_TX1_CTL_M 0x3F |
| |
| |
| #define TIMPANI_CDC_TX1_CTL_TX1_DMIC_SEL_R_S 5 |
| #define TIMPANI_CDC_TX1_CTL_TX1_DMIC_SEL_R_M 0x20 |
| |
| #define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_S 3 |
| #define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_M 0x18 |
| #define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_OSR_256 0x3 |
| #define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_OSR_128 0x1 |
| #define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_OSR_64 0x0 |
| |
| #define TIMPANI_CDC_TX1_CTL_TX1_DMIC_SEL_L_S 2 |
| #define TIMPANI_CDC_TX1_CTL_TX1_DMIC_SEL_L_M 0x4 |
| |
| #define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_S 0 |
| #define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_M 0x3 |
| #define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_OSR_256 0x3 |
| #define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_OSR_128 0x1 |
| #define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_OSR_64 0x0 |
| |
| |
| /* -- For CDC_ADC34_CLK_CTL */ |
| #define TIMPANI_A_CDC_ADC34_CLK_CTL (0x95) |
| #define TIMPANI_CDC_ADC34_CLK_CTL_RWC "RW" |
| #define TIMPANI_CDC_ADC34_CLK_CTL_POR 0 |
| #define TIMPANI_CDC_ADC34_CLK_CTL_S 0 |
| #define TIMPANI_CDC_ADC34_CLK_CTL_M 0xFF |
| |
| |
| #define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_S 6 |
| #define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_M 0xC0 |
| #define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_RX_MCLK2 0x2 |
| #define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_RX_MCLK1 0x1 |
| #define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_TX_MCLK 0x0 |
| |
| #define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_S 3 |
| #define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_M 0x38 |
| #define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_6 0x4 |
| #define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_4 0x3 |
| #define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_3 0x2 |
| #define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_2 0x1 |
| #define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_1 0x0 |
| |
| #define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_S 0 |
| #define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_M 0x7 |
| #define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_6 0x4 |
| #define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_4 0x3 |
| #define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_3 0x2 |
| #define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_2 0x1 |
| #define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_1 0x0 |
| |
| |
| /* -- For CDC_TX2_CTL */ |
| #define TIMPANI_A_CDC_TX2_CTL (0x96) |
| #define TIMPANI_CDC_TX2_CTL_RWC "RW" |
| #define TIMPANI_CDC_TX2_CTL_POR 0x1b |
| #define TIMPANI_CDC_TX2_CTL_S 0 |
| #define TIMPANI_CDC_TX2_CTL_M 0x3F |
| |
| |
| #define TIMPANI_CDC_TX2_CTL_TX2_DMIC_SEL_R_S 5 |
| #define TIMPANI_CDC_TX2_CTL_TX2_DMIC_SEL_R_M 0x20 |
| |
| #define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_S 3 |
| #define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_M 0x18 |
| #define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_OSR_256 0x3 |
| #define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_OSR_128 0x1 |
| #define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_OSR_64 0x0 |
| |
| #define TIMPANI_CDC_TX2_CTL_TX2_DMIC_SEL_L_S 2 |
| #define TIMPANI_CDC_TX2_CTL_TX2_DMIC_SEL_L_M 0x4 |
| |
| #define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_S 0 |
| #define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_M 0x3 |
| #define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_OSR_256 0x3 |
| #define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_OSR_128 0x1 |
| #define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_OSR_64 0x0 |
| |
| |
| /* -- For CDC_RX1_CLK_CTL */ |
| #define TIMPANI_A_CDC_RX1_CLK_CTL (0x97) |
| #define TIMPANI_CDC_RX1_CLK_CTL_RWC "RW" |
| #define TIMPANI_CDC_RX1_CLK_CTL_POR 0x1 |
| #define TIMPANI_CDC_RX1_CLK_CTL_S 0 |
| #define TIMPANI_CDC_RX1_CLK_CTL_M 0x1F |
| |
| |
| #define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_S 2 |
| #define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_M 0x1C |
| #define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_6 0x4 |
| #define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_4 0x3 |
| #define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_3 0x2 |
| #define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_2 0x1 |
| #define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_1 0x0 |
| |
| #define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_S 0 |
| #define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_M 0x3 |
| #define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_RX_MCLK2 0x2 |
| #define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_RX_MCLK1 0x1 |
| #define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_TX_MCLK 0x0 |
| |
| |
| /* -- For CDC_RX2_CLK_CTL */ |
| #define TIMPANI_A_CDC_RX2_CLK_CTL (0x98) |
| #define TIMPANI_CDC_RX2_CLK_CTL_RWC "RW" |
| #define TIMPANI_CDC_RX2_CLK_CTL_POR 0x2 |
| #define TIMPANI_CDC_RX2_CLK_CTL_S 0 |
| #define TIMPANI_CDC_RX2_CLK_CTL_M 0x1F |
| |
| |
| #define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_S 2 |
| #define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_M 0x1C |
| #define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_6 0x4 |
| #define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_4 0x3 |
| #define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_3 0x2 |
| #define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_2 0x1 |
| #define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_1 0x0 |
| |
| #define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_S 0 |
| #define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_M 0x3 |
| #define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_RX_MCLK2 0x2 |
| #define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_RX_MCLK1 0x1 |
| #define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_TX_MCLK 0x0 |
| |
| |
| /* -- For CDC_DEC_ADC_SEL */ |
| #define TIMPANI_A_CDC_DEC_ADC_SEL (0x99) |
| #define TIMPANI_CDC_DEC_ADC_SEL_RWC "RW" |
| #define TIMPANI_CDC_DEC_ADC_SEL_POR 0 |
| #define TIMPANI_CDC_DEC_ADC_SEL_S 0 |
| #define TIMPANI_CDC_DEC_ADC_SEL_M 0xFF |
| |
| |
| #define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_S 6 |
| #define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_M 0xC0 |
| #define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC4 0x3 |
| #define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC3 0x2 |
| #define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC2 0x1 |
| #define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC1 0x0 |
| |
| #define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_S 4 |
| #define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_M 0x30 |
| #define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC4 0x3 |
| #define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC3 0x2 |
| #define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC2 0x1 |
| #define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC1 0x0 |
| |
| #define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_S 2 |
| #define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_M 0xC |
| #define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC4 0x3 |
| #define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC3 0x2 |
| #define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC2 0x1 |
| #define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC1 0x0 |
| |
| #define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_S 0 |
| #define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_M 0x3 |
| #define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC4 0x3 |
| #define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC3 0x2 |
| #define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC2 0x1 |
| #define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC1 0x0 |
| |
| |
| /* -- For CDC_ANC_INPUT_MUX */ |
| #define TIMPANI_A_CDC_ANC_INPUT_MUX (0x9A) |
| #define TIMPANI_CDC_ANC_INPUT_MUX_RWC "RW" |
| #define TIMPANI_CDC_ANC_INPUT_MUX_POR 0 |
| #define TIMPANI_CDC_ANC_INPUT_MUX_S 0 |
| #define TIMPANI_CDC_ANC_INPUT_MUX_M 0xFF |
| |
| |
| #define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_S 6 |
| #define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_M 0xC0 |
| #define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX2DOR 0x3 |
| #define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX2DOL 0x2 |
| #define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX1DOR 0x1 |
| #define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX1DOL 0x0 |
| |
| #define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_S 4 |
| #define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_M 0x30 |
| #define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC2_DIN_R 0x3 |
| #define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC2_DIN_L 0x2 |
| #define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC1_DIN_R 0x1 |
| #define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC1_DIN_L 0x0 |
| |
| #define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_S 2 |
| #define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_M 0xC |
| #define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX2DOR 0x3 |
| #define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX2DOL 0x2 |
| #define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX1DOR 0x1 |
| #define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX1DOL 0x0 |
| |
| #define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_S 0 |
| #define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_M 0x3 |
| #define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC2_DIN_R 0x3 |
| #define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC2_DIN_L 0x2 |
| #define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC1_DIN_R 0x1 |
| #define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC1_DIN_L 0x0 |
| |
| |
| /* -- For CDC_ANC_RX_CLK_NS_SEL */ |
| #define TIMPANI_A_CDC_ANC_RX_CLK_NS_SEL (0x9B) |
| #define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_RWC "RW" |
| #define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_POR 0 |
| #define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_S 0 |
| #define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_M 0x1 |
| |
| |
| #define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_ANC_RX_CLK_NS_SEL_S 0 |
| #define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_ANC_RX_CLK_NS_SEL_M 0x1 |
| |
| |
| /* -- For CDC_ANC_FB_TUNE_SEL */ |
| #define TIMPANI_A_CDC_ANC_FB_TUNE_SEL (0x9C) |
| #define TIMPANI_CDC_ANC_FB_TUNE_SEL_RWC "RW" |
| #define TIMPANI_CDC_ANC_FB_TUNE_SEL_POR 0 |
| #define TIMPANI_CDC_ANC_FB_TUNE_SEL_S 0 |
| #define TIMPANI_CDC_ANC_FB_TUNE_SEL_M 0x3 |
| |
| |
| #define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_S 1 |
| #define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_M 0x2 |
| #define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_FB_TUNE_EN 0x1 |
| #define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_FB_TUNE_DIS 0x0 |
| |
| #define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_S 0 |
| #define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_M 0x1 |
| #define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_FB_TUNE_EN 0x1 |
| #define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_FB_TUNE_DIS 0x0 |
| |
| |
| /* -- For CLK_DIV_SYNC_CTL */ |
| #define TIMPANI_A_CLK_DIV_SYNC_CTL (0x9E) |
| #define TIMPANI_CLK_DIV_SYNC_CTL_RWC "RW" |
| #define TIMPANI_CLK_DIV_SYNC_CTL_POR 0 |
| #define TIMPANI_CLK_DIV_SYNC_CTL_S 0 |
| #define TIMPANI_CLK_DIV_SYNC_CTL_M 0x3 |
| |
| |
| #define TIMPANI_CLK_DIV_SYNC_CTL_GLBL_DIV_SYNC_S 1 |
| #define TIMPANI_CLK_DIV_SYNC_CTL_GLBL_DIV_SYNC_M 0x2 |
| |
| #define TIMPANI_CLK_DIV_SYNC_CTL_TX_DIV_SYNC_S 0 |
| #define TIMPANI_CLK_DIV_SYNC_CTL_TX_DIV_SYNC_M 0x1 |
| |
| |
| /* -- For CDC_ADC_CLK_EN */ |
| #define TIMPANI_A_CDC_ADC_CLK_EN (0x9F) |
| #define TIMPANI_CDC_ADC_CLK_EN_RWC "RW" |
| #define TIMPANI_CDC_ADC_CLK_EN_POR 0 |
| #define TIMPANI_CDC_ADC_CLK_EN_S 0 |
| #define TIMPANI_CDC_ADC_CLK_EN_M 0xF |
| |
| |
| #define TIMPANI_CDC_ADC_CLK_EN_A_TX2_R_EN_S 3 |
| #define TIMPANI_CDC_ADC_CLK_EN_A_TX2_R_EN_M 0x8 |
| |
| #define TIMPANI_CDC_ADC_CLK_EN_A_TX2_L_EN_S 2 |
| #define TIMPANI_CDC_ADC_CLK_EN_A_TX2_L_EN_M 0x4 |
| |
| #define TIMPANI_CDC_ADC_CLK_EN_A_TX1_R_EN_S 1 |
| #define TIMPANI_CDC_ADC_CLK_EN_A_TX1_R_EN_M 0x2 |
| |
| #define TIMPANI_CDC_ADC_CLK_EN_A_TX1_L_EN_S 0 |
| #define TIMPANI_CDC_ADC_CLK_EN_A_TX1_L_EN_M 0x1 |
| |
| |
| /* -- For CDC_ST_MIXING */ |
| #define TIMPANI_A_CDC_ST_MIXING (0xA0) |
| #define TIMPANI_CDC_ST_MIXING_RWC "RW" |
| #define TIMPANI_CDC_ST_MIXING_POR 0 |
| #define TIMPANI_CDC_ST_MIXING_S 0 |
| #define TIMPANI_CDC_ST_MIXING_M 0xF |
| |
| |
| #define TIMPANI_CDC_ST_MIXING_TX2_R_S 3 |
| #define TIMPANI_CDC_ST_MIXING_TX2_R_M 0x8 |
| |
| #define TIMPANI_CDC_ST_MIXING_TX2_L_S 2 |
| #define TIMPANI_CDC_ST_MIXING_TX2_L_M 0x4 |
| |
| #define TIMPANI_CDC_ST_MIXING_TX1_R_S 1 |
| #define TIMPANI_CDC_ST_MIXING_TX1_R_M 0x2 |
| |
| #define TIMPANI_CDC_ST_MIXING_TX1_L_S 0 |
| #define TIMPANI_CDC_ST_MIXING_TX1_L_M 0x1 |
| |
| |
| /* -- For CDC_RX2_CTL */ |
| #define TIMPANI_A_CDC_RX2_CTL (0xA1) |
| #define TIMPANI_CDC_RX2_CTL_RWC "RW" |
| #define TIMPANI_CDC_RX2_CTL_POR 0xc |
| #define TIMPANI_CDC_RX2_CTL_S 0 |
| #define TIMPANI_CDC_RX2_CTL_M 0x3F |
| |
| |
| #define TIMPANI_CDC_RX2_CTL_SIDETONE_EN2_R_S 5 |
| #define TIMPANI_CDC_RX2_CTL_SIDETONE_EN2_R_M 0x20 |
| |
| #define TIMPANI_CDC_RX2_CTL_SIDETONE_EN2_L_S 4 |
| #define TIMPANI_CDC_RX2_CTL_SIDETONE_EN2_L_M 0x10 |
| |
| #define TIMPANI_CDC_RX2_CTL_RX2_RATE_S 2 |
| #define TIMPANI_CDC_RX2_CTL_RX2_RATE_M 0xC |
| #define TIMPANI_CDC_RX2_CTL_RX2_RATE_OSR_256 0x3 |
| #define TIMPANI_CDC_RX2_CTL_RX2_RATE_OSR_128 0x1 |
| #define TIMPANI_CDC_RX2_CTL_RX2_RATE_OSR_64 0x0 |
| |
| #define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_S 1 |
| #define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_M 0x2 |
| #define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_BR_32 0x1 |
| #define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_BR_64 0x0 |
| |
| #define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_S 0 |
| #define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_M 0x1 |
| #define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_MASTER 0x1 |
| #define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_SLAVE 0x0 |
| |
| |
| /* -- For CDC_ARB_CLK_EN */ |
| #define TIMPANI_A_CDC_ARB_CLK_EN (0xA2) |
| #define TIMPANI_CDC_ARB_CLK_EN_RWC "RW" |
| #define TIMPANI_CDC_ARB_CLK_EN_POR 0 |
| #define TIMPANI_CDC_ARB_CLK_EN_S 0 |
| #define TIMPANI_CDC_ARB_CLK_EN_M 0x1 |
| |
| |
| #define TIMPANI_CDC_ARB_CLK_EN_ARB_CLK_EN_S 0 |
| #define TIMPANI_CDC_ARB_CLK_EN_ARB_CLK_EN_M 0x1 |
| |
| |
| /* -- For CDC_I2S_CTL2 */ |
| #define TIMPANI_A_CDC_I2S_CTL2 (0xA3) |
| #define TIMPANI_CDC_I2S_CTL2_RWC "RW" |
| #define TIMPANI_CDC_I2S_CTL2_POR 0 |
| #define TIMPANI_CDC_I2S_CTL2_S 0 |
| #define TIMPANI_CDC_I2S_CTL2_M 0x3F |
| |
| |
| #define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_S 3 |
| #define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_M 0x38 |
| #define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_DMIC 0x4 |
| #define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX2_R 0x3 |
| #define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX2_L 0x2 |
| #define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX1_R 0x1 |
| #define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX1_L 0x0 |
| |
| #define TIMPANI_CDC_I2S_CTL2_RX2_I2SCLK_EN_S 2 |
| #define TIMPANI_CDC_I2S_CTL2_RX2_I2SCLK_EN_M 0x4 |
| |
| #define TIMPANI_CDC_I2S_CTL2_RX1_I2SCLK_EN_S 1 |
| #define TIMPANI_CDC_I2S_CTL2_RX1_I2SCLK_EN_M 0x2 |
| |
| #define TIMPANI_CDC_I2S_CTL2_TX_I2SCLK_EN_S 0 |
| #define TIMPANI_CDC_I2S_CTL2_TX_I2SCLK_EN_M 0x1 |
| |
| |
| /* -- For CDC_RX2LG */ |
| #define TIMPANI_A_CDC_RX2LG (0xA4) |
| #define TIMPANI_CDC_RX2LG_RWC "RW" |
| #define TIMPANI_CDC_RX2LG_POR 0xac |
| #define TIMPANI_CDC_RX2LG_S 0 |
| #define TIMPANI_CDC_RX2LG_M 0xFF |
| |
| |
| #define TIMPANI_CDC_RX2LG_GAIN_S 0 |
| #define TIMPANI_CDC_RX2LG_GAIN_M 0xFF |
| |
| |
| /* -- For CDC_RX2RG */ |
| #define TIMPANI_A_CDC_RX2RG (0xA5) |
| #define TIMPANI_CDC_RX2RG_RWC "RW" |
| #define TIMPANI_CDC_RX2RG_POR 0xac |
| #define TIMPANI_CDC_RX2RG_S 0 |
| #define TIMPANI_CDC_RX2RG_M 0xFF |
| |
| |
| #define TIMPANI_CDC_RX2RG_GAIN_S 0 |
| #define TIMPANI_CDC_RX2RG_GAIN_M 0xFF |
| |
| |
| /* -- For CDC_TX2LG */ |
| #define TIMPANI_A_CDC_TX2LG (0xA6) |
| #define TIMPANI_CDC_TX2LG_RWC "RW" |
| #define TIMPANI_CDC_TX2LG_POR 0xac |
| #define TIMPANI_CDC_TX2LG_S 0 |
| #define TIMPANI_CDC_TX2LG_M 0xFF |
| |
| |
| #define TIMPANI_CDC_TX2LG_GAIN_S 0 |
| #define TIMPANI_CDC_TX2LG_GAIN_M 0xFF |
| |
| |
| /* -- For CDC_TX2RG */ |
| #define TIMPANI_A_CDC_TX2RG (0xA7) |
| #define TIMPANI_CDC_TX2RG_RWC "RW" |
| #define TIMPANI_CDC_TX2RG_POR 0xac |
| #define TIMPANI_CDC_TX2RG_S 0 |
| #define TIMPANI_CDC_TX2RG_M 0xFF |
| |
| |
| #define TIMPANI_CDC_TX2RG_GAIN_S 0 |
| #define TIMPANI_CDC_TX2RG_GAIN_M 0xFF |
| |
| |
| /* -- For CDC_DMIC_MUX */ |
| #define TIMPANI_A_CDC_DMIC_MUX (0xA8) |
| #define TIMPANI_CDC_DMIC_MUX_RWC "RW" |
| #define TIMPANI_CDC_DMIC_MUX_POR 0 |
| #define TIMPANI_CDC_DMIC_MUX_S 0 |
| #define TIMPANI_CDC_DMIC_MUX_M 0xFF |
| |
| |
| #define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_S 6 |
| #define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_M 0xC0 |
| #define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC2_DIN_R 0x3 |
| #define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC2_DIN_L 0x2 |
| #define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC1_DIN_R 0x1 |
| #define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC1_DIN_L 0x0 |
| |
| #define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_S 4 |
| #define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_M 0x30 |
| #define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC2_DIN_R 0x3 |
| #define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC2_DIN_L 0x2 |
| #define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC1_DIN_R 0x1 |
| #define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC1_DIN_L 0x0 |
| |
| #define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_S 2 |
| #define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_M 0xC |
| #define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC2_DIN_R 0x3 |
| #define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC2_DIN_L 0x2 |
| #define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC1_DIN_R 0x1 |
| #define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC1_DIN_L 0x0 |
| |
| #define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_S 0 |
| #define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_M 0x3 |
| #define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC2_DIN_R 0x3 |
| #define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC2_DIN_L 0x2 |
| #define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC1_DIN_R 0x1 |
| #define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC1_DIN_L 0x0 |
| |
| |
| /* -- For CDC_ARB_CLK_CTL */ |
| #define TIMPANI_A_CDC_ARB_CLK_CTL (0xA9) |
| #define TIMPANI_CDC_ARB_CLK_CTL_RWC "RW" |
| #define TIMPANI_CDC_ARB_CLK_CTL_POR 0 |
| #define TIMPANI_CDC_ARB_CLK_CTL_S 0 |
| #define TIMPANI_CDC_ARB_CLK_CTL_M 0x3 |
| |
| |
| #define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_S 0 |
| #define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_M 0x3 |
| #define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_TX_MCLK 0x0 |
| #define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_RX_MCLK1 0x1 |
| #define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_RX_MCLK2 0x2 |
| #define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_TCXO 0x3 |
| |
| |
| /* -- For CDC_GCTL2 */ |
| #define TIMPANI_A_CDC_GCTL2 (0xAA) |
| #define TIMPANI_CDC_GCTL2_RWC "RW" |
| #define TIMPANI_CDC_GCTL2_POR 0x33 |
| #define TIMPANI_CDC_GCTL2_S 0 |
| #define TIMPANI_CDC_GCTL2_M 0xFF |
| |
| |
| #define TIMPANI_CDC_GCTL2_TX2_PGA_UPDATE_R_S 7 |
| #define TIMPANI_CDC_GCTL2_TX2_PGA_UPDATE_R_M 0x80 |
| |
| #define TIMPANI_CDC_GCTL2_TX2_PGA_UPDATE_L_S 6 |
| #define TIMPANI_CDC_GCTL2_TX2_PGA_UPDATE_L_M 0x40 |
| |
| #define TIMPANI_CDC_GCTL2_TX2_PGA_MUTE_EN_R_S 5 |
| #define TIMPANI_CDC_GCTL2_TX2_PGA_MUTE_EN_R_M 0x20 |
| |
| #define TIMPANI_CDC_GCTL2_TX2_PGA_MUTE_EN_L_S 4 |
| #define TIMPANI_CDC_GCTL2_TX2_PGA_MUTE_EN_L_M 0x10 |
| |
| #define TIMPANI_CDC_GCTL2_RX2_PGA_UPDATE_R_S 3 |
| #define TIMPANI_CDC_GCTL2_RX2_PGA_UPDATE_R_M 0x8 |
| |
| #define TIMPANI_CDC_GCTL2_RX2_PGA_UPDATE_L_S 2 |
| #define TIMPANI_CDC_GCTL2_RX2_PGA_UPDATE_L_M 0x4 |
| |
| #define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_R_S 1 |
| #define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_R_M 0x2 |
| |
| #define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_L_S 0 |
| #define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_L_M 0x1 |
| |
| |
| /* -- For CDC_BYPASS_CTL2 */ |
| #define TIMPANI_A_CDC_BYPASS_CTL2 (0xAB) |
| #define TIMPANI_CDC_BYPASS_CTL2_RWC "RW" |
| #define TIMPANI_CDC_BYPASS_CTL2_POR 0x2D |
| #define TIMPANI_CDC_BYPASS_CTL2_S 0 |
| #define TIMPANI_CDC_BYPASS_CTL2_M 0x3F |
| |
| |
| #define TIMPANI_CDC_BYPASS_CTL2_TX1_DMIC_GAIN_BP_R_S 5 |
| #define TIMPANI_CDC_BYPASS_CTL2_TX1_DMIC_GAIN_BP_R_M 0x20 |
| |
| #define TIMPANI_CDC_BYPASS_CTL2_TX1_ADC_GAIN_BP_R_S 4 |
| #define TIMPANI_CDC_BYPASS_CTL2_TX1_ADC_GAIN_BP_R_M 0x10 |
| |
| #define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_R_S 3 |
| #define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_R_M 0x8 |
| |
| #define TIMPANI_CDC_BYPASS_CTL2_TX1_DMIC_GAIN_BP_L_S 2 |
| #define TIMPANI_CDC_BYPASS_CTL2_TX1_DMIC_GAIN_BP_L_M 0x4 |
| |
| #define TIMPANI_CDC_BYPASS_CTL2_TX1_ADC_GAIN_BP_L_S 1 |
| #define TIMPANI_CDC_BYPASS_CTL2_TX1_ADC_GAIN_BP_L_M 0x2 |
| |
| #define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_L_S 0 |
| #define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_L_M 0x1 |
| |
| |
| /* -- For CDC_BYPASS_CTL3 */ |
| #define TIMPANI_A_CDC_BYPASS_CTL3 (0xAC) |
| #define TIMPANI_CDC_BYPASS_CTL3_RWC "RW" |
| #define TIMPANI_CDC_BYPASS_CTL3_POR 0x2D |
| #define TIMPANI_CDC_BYPASS_CTL3_S 0 |
| #define TIMPANI_CDC_BYPASS_CTL3_M 0x3F |
| |
| |
| #define TIMPANI_CDC_BYPASS_CTL3_TX2_DMIC_GAIN_BP_R_S 5 |
| #define TIMPANI_CDC_BYPASS_CTL3_TX2_DMIC_GAIN_BP_R_M 0x20 |
| |
| #define TIMPANI_CDC_BYPASS_CTL3_TX2_ADC_GAIN_BP_R_S 4 |
| #define TIMPANI_CDC_BYPASS_CTL3_TX2_ADC_GAIN_BP_R_M 0x10 |
| |
| #define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_R_S 3 |
| #define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_R_M 0x8 |
| |
| #define TIMPANI_CDC_BYPASS_CTL3_TX2_DMIC_GAIN_BP_L_S 2 |
| #define TIMPANI_CDC_BYPASS_CTL3_TX2_DMIC_GAIN_BP_L_M 0x4 |
| |
| #define TIMPANI_CDC_BYPASS_CTL3_TX2_ADC_GAIN_BP_L_S 1 |
| #define TIMPANI_CDC_BYPASS_CTL3_TX2_ADC_GAIN_BP_L_M 0x2 |
| |
| #define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_L_S 0 |
| #define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_L_M 0x1 |
| |
| |
| /* -- For CDC_BYPASS_CTL4 */ |
| #define TIMPANI_A_CDC_BYPASS_CTL4 (0xAD) |
| #define TIMPANI_CDC_BYPASS_CTL4_RWC "RW" |
| #define TIMPANI_CDC_BYPASS_CTL4_POR 0x2 |
| #define TIMPANI_CDC_BYPASS_CTL4_S 0 |
| #define TIMPANI_CDC_BYPASS_CTL4_M 0xF |
| |
| |
| #define TIMPANI_CDC_BYPASS_CTL4_DITHER_BP_S 3 |
| #define TIMPANI_CDC_BYPASS_CTL4_DITHER_BP_M 0x8 |
| |
| #define TIMPANI_CDC_BYPASS_CTL4_DITHER_SHAPE_SEL_S 2 |
| #define TIMPANI_CDC_BYPASS_CTL4_DITHER_SHAPE_SEL_M 0x4 |
| |
| #define TIMPANI_CDC_BYPASS_CTL4_DITHER_DLY_SEL_S 1 |
| #define TIMPANI_CDC_BYPASS_CTL4_DITHER_DLY_SEL_M 0x2 |
| |
| #define TIMPANI_CDC_BYPASS_CTL4_RX2_HPF_BP_S 0 |
| #define TIMPANI_CDC_BYPASS_CTL4_RX2_HPF_BP_M 0x1 |
| |
| |
| /* -- For CDC_RX2L_DCOFFSET */ |
| #define TIMPANI_A_CDC_RX2L_DCOFFSET (0xAE) |
| #define TIMPANI_CDC_RX2L_DCOFFSET_RWC "RW" |
| #define TIMPANI_CDC_RX2L_DCOFFSET_POR 0 |
| #define TIMPANI_CDC_RX2L_DCOFFSET_S 0 |
| #define TIMPANI_CDC_RX2L_DCOFFSET_M 0xFF |
| |
| |
| #define TIMPANI_CDC_RX2L_DCOFFSET_OFFSET_S 0 |
| #define TIMPANI_CDC_RX2L_DCOFFSET_OFFSET_M 0xFF |
| |
| |
| /* -- For CDC_RX2R_DCOFFSET */ |
| #define TIMPANI_A_CDC_RX2R_DCOFFSET (0xAF) |
| #define TIMPANI_CDC_RX2R_DCOFFSET_RWC "RW" |
| #define TIMPANI_CDC_RX2R_DCOFFSET_POR 0 |
| #define TIMPANI_CDC_RX2R_DCOFFSET_S 0 |
| #define TIMPANI_CDC_RX2R_DCOFFSET_M 0xFF |
| |
| |
| #define TIMPANI_CDC_RX2R_DCOFFSET_OFFSET_S 0 |
| #define TIMPANI_CDC_RX2R_DCOFFSET_OFFSET_M 0xFF |
| |
| |
| /* -- For CDC_RX_MIX_CTL */ |
| #define TIMPANI_A_CDC_RX_MIX_CTL (0xB0) |
| #define TIMPANI_CDC_RX_MIX_CTL_RWC "RW" |
| #define TIMPANI_CDC_RX_MIX_CTL_POR 0 |
| #define TIMPANI_CDC_RX_MIX_CTL_S 0 |
| #define TIMPANI_CDC_RX_MIX_CTL_M 0x3 |
| |
| |
| #define TIMPANI_CDC_RX_MIX_CTL_RX2TO1_EN_S 1 |
| #define TIMPANI_CDC_RX_MIX_CTL_RX2TO1_EN_M 0x2 |
| |
| #define TIMPANI_CDC_RX_MIX_CTL_RX1TO2_EN_S 0 |
| #define TIMPANI_CDC_RX_MIX_CTL_RX1TO2_EN_M 0x1 |
| |
| |
| /* -- For CDC_SPARE_CTL */ |
| #define TIMPANI_A_CDC_SPARE_CTL (0xB1) |
| #define TIMPANI_CDC_SPARE_CTL_RWC "RW" |
| #define TIMPANI_CDC_SPARE_CTL_POR 0 |
| #define TIMPANI_CDC_SPARE_CTL_S 0 |
| #define TIMPANI_CDC_SPARE_CTL_M 0xFF |
| |
| |
| #define TIMPANI_CDC_SPARE_CTL_CDC_SPARE_S 0 |
| #define TIMPANI_CDC_SPARE_CTL_CDC_SPARE_M 0xFF |
| |
| |
| /* -- For CDC_TESTMODE2 */ |
| #define TIMPANI_A_CDC_TESTMODE2 (0xB2) |
| #define TIMPANI_CDC_TESTMODE2_RWC "RW" |
| #define TIMPANI_CDC_TESTMODE2_POR 0 |
| #define TIMPANI_CDC_TESTMODE2_S 0 |
| #define TIMPANI_CDC_TESTMODE2_M 0x1F |
| |
| |
| #define TIMPANI_CDC_TESTMODE2_RX2_TEST_EN_R_S 4 |
| #define TIMPANI_CDC_TESTMODE2_RX2_TEST_EN_R_M 0x10 |
| |
| #define TIMPANI_CDC_TESTMODE2_RX2_TEST_EN_L_S 3 |
| #define TIMPANI_CDC_TESTMODE2_RX2_TEST_EN_L_M 0x8 |
| |
| #define TIMPANI_CDC_TESTMODE2_TX2_TEST_EN_R_S 2 |
| #define TIMPANI_CDC_TESTMODE2_TX2_TEST_EN_R_M 0x4 |
| |
| #define TIMPANI_CDC_TESTMODE2_TX2_TEST_EN_L_S 1 |
| #define TIMPANI_CDC_TESTMODE2_TX2_TEST_EN_L_M 0x2 |
| |
| #define TIMPANI_CDC_TESTMODE2_A_LOOPBACK_EN2_S 0 |
| #define TIMPANI_CDC_TESTMODE2_A_LOOPBACK_EN2_M 0x1 |
| |
| |
| /* -- For CDC_PDM_OE */ |
| #define TIMPANI_A_CDC_PDM_OE (0xB3) |
| #define TIMPANI_CDC_PDM_OE_RWC "RW" |
| #define TIMPANI_CDC_PDM_OE_POR 0 |
| #define TIMPANI_CDC_PDM_OE_S 0 |
| #define TIMPANI_CDC_PDM_OE_M 0x3F |
| |
| |
| #define TIMPANI_CDC_PDM_OE_PDM_23_20_OE_S 5 |
| #define TIMPANI_CDC_PDM_OE_PDM_23_20_OE_M 0x20 |
| |
| #define TIMPANI_CDC_PDM_OE_PDM_19_16_OE_S 4 |
| #define TIMPANI_CDC_PDM_OE_PDM_19_16_OE_M 0x10 |
| |
| #define TIMPANI_CDC_PDM_OE_PDM_15_12_OE_S 3 |
| #define TIMPANI_CDC_PDM_OE_PDM_15_12_OE_M 0x8 |
| |
| #define TIMPANI_CDC_PDM_OE_PDM_11_8_OE_S 2 |
| #define TIMPANI_CDC_PDM_OE_PDM_11_8_OE_M 0x4 |
| |
| #define TIMPANI_CDC_PDM_OE_PDM_7_4_OE_S 1 |
| #define TIMPANI_CDC_PDM_OE_PDM_7_4_OE_M 0x2 |
| |
| #define TIMPANI_CDC_PDM_OE_PDM_3_0_OE_S 0 |
| #define TIMPANI_CDC_PDM_OE_PDM_3_0_OE_M 0x1 |
| |
| |
| /* -- For CDC_TX1R_STG */ |
| #define TIMPANI_A_CDC_TX1R_STG (0xB4) |
| #define TIMPANI_CDC_TX1R_STG_RWC "RW" |
| #define TIMPANI_CDC_TX1R_STG_POR 0xac |
| #define TIMPANI_CDC_TX1R_STG_S 0 |
| #define TIMPANI_CDC_TX1R_STG_M 0xFF |
| |
| |
| #define TIMPANI_CDC_TX1R_STG_GAIN_S 0 |
| #define TIMPANI_CDC_TX1R_STG_GAIN_M 0xFF |
| |
| |
| /* -- For CDC_TX2L_STG */ |
| #define TIMPANI_A_CDC_TX2L_STG (0xB5) |
| #define TIMPANI_CDC_TX2L_STG_RWC "RW" |
| #define TIMPANI_CDC_TX2L_STG_POR 0xac |
| #define TIMPANI_CDC_TX2L_STG_S 0 |
| #define TIMPANI_CDC_TX2L_STG_M 0xFF |
| |
| |
| #define TIMPANI_CDC_TX2L_STG_GAIN_S 0 |
| #define TIMPANI_CDC_TX2L_STG_GAIN_M 0xFF |
| |
| |
| /* -- For CDC_TX2R_STG */ |
| #define TIMPANI_A_CDC_TX2R_STG (0xB6) |
| #define TIMPANI_CDC_TX2R_STG_RWC "RW" |
| #define TIMPANI_CDC_TX2R_STG_POR 0xac |
| #define TIMPANI_CDC_TX2R_STG_S 0 |
| #define TIMPANI_CDC_TX2R_STG_M 0xFF |
| |
| |
| #define TIMPANI_CDC_TX2R_STG_GAIN_S 0 |
| #define TIMPANI_CDC_TX2R_STG_GAIN_M 0xFF |
| |
| |
| /* -- For CDC_ARB_BYPASS_CTL */ |
| #define TIMPANI_A_CDC_ARB_BYPASS_CTL (0xB7) |
| #define TIMPANI_CDC_ARB_BYPASS_CTL_RWC "RW" |
| #define TIMPANI_CDC_ARB_BYPASS_CTL_POR 0 |
| #define TIMPANI_CDC_ARB_BYPASS_CTL_S 0 |
| #define TIMPANI_CDC_ARB_BYPASS_CTL_M 0x1 |
| |
| |
| #define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_S 0 |
| #define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_M 0x1 |
| #define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_BYPASS 0x1 |
| #define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_NO_BYPASS 0x0 |
| |
| |
| /* -- For CDC_ANC1_CTL1 */ |
| #define TIMPANI_A_CDC_ANC1_CTL1 (0xC0) |
| #define TIMPANI_CDC_ANC1_CTL1_RWC "RW" |
| #define TIMPANI_CDC_ANC1_CTL1_POR 0 |
| #define TIMPANI_CDC_ANC1_CTL1_S 0 |
| #define TIMPANI_CDC_ANC1_CTL1_M 0x3F |
| |
| |
| #define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_S 5 |
| #define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_M 0x20 |
| #define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_FF_OUT_DIS 0x1 |
| #define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_FF_OUT_EN 0x0 |
| |
| #define TIMPANI_CDC_ANC1_CTL1_ANC1_ADC_DMIC_SEL_S 4 |
| #define TIMPANI_CDC_ANC1_CTL1_ANC1_ADC_DMIC_SEL_M 0x10 |
| #define TIMPANI_CDC_ANC1_CTL1_ANC1_ADC_DMIC_SEL_DMIC 0x1 |
| #define TIMPANI_CDC_ANC1_CTL1_ANC1_ADC_DMIC_SEL_ADC 0x0 |
| |
| #define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_S 3 |
| #define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_M 0x8 |
| #define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_LR_MIX_EN 0x1 |
| #define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_LR_MIX_DIS 0x0 |
| |
| #define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_S 2 |
| #define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_M 0x4 |
| #define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_FB_MIX_EN 0x1 |
| #define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_FB_MIX_DIS 0x0 |
| |
| #define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_S 1 |
| #define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_M 0x2 |
| #define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_ANC_EN 0x1 |
| #define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_ANC_DIS 0x0 |
| |
| #define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_S 0 |
| #define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_M 0x1 |
| #define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_ANC_RESET 0x1 |
| #define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_ANC_ACTIVE 0x0 |
| |
| |
| /* -- For CDC_ANC1_CTL2 */ |
| #define TIMPANI_A_CDC_ANC1_CTL2 (0xC1) |
| #define TIMPANI_CDC_ANC1_CTL2_RWC "RW" |
| #define TIMPANI_CDC_ANC1_CTL2_POR 0 |
| #define TIMPANI_CDC_ANC1_CTL2_S 0 |
| #define TIMPANI_CDC_ANC1_CTL2_M 0x1F |
| |
| |
| #define TIMPANI_CDC_ANC1_CTL2_ANC1_FREQ_SEL_S 0 |
| #define TIMPANI_CDC_ANC1_CTL2_ANC1_FREQ_SEL_M 0x1F |
| |
| |
| /* -- For CDC_ANC1_FF_FB_SHIFT */ |
| #define TIMPANI_A_CDC_ANC1_FF_FB_SHIFT (0xC2) |
| #define TIMPANI_CDC_ANC1_FF_FB_SHIFT_RWC "RW" |
| #define TIMPANI_CDC_ANC1_FF_FB_SHIFT_POR 0 |
| #define TIMPANI_CDC_ANC1_FF_FB_SHIFT_S 0 |
| #define TIMPANI_CDC_ANC1_FF_FB_SHIFT_M 0xFF |
| |
| |
| #define TIMPANI_CDC_ANC1_FF_FB_SHIFT_ANC1_FB_LPF_SHIFT_S 4 |
| #define TIMPANI_CDC_ANC1_FF_FB_SHIFT_ANC1_FB_LPF_SHIFT_M 0xF0 |
| |
| #define TIMPANI_CDC_ANC1_FF_FB_SHIFT_ANC1_FF_LPF_SHIFT_S 0 |
| #define TIMPANI_CDC_ANC1_FF_FB_SHIFT_ANC1_FF_LPF_SHIFT_M 0xF |
| |
| |
| /* -- For CDC_ANC1_RX_NS */ |
| #define TIMPANI_A_CDC_ANC1_RX_NS (0xC3) |
| #define TIMPANI_CDC_ANC1_RX_NS_RWC "RW" |
| #define TIMPANI_CDC_ANC1_RX_NS_POR 0x1 |
| #define TIMPANI_CDC_ANC1_RX_NS_S 0 |
| #define TIMPANI_CDC_ANC1_RX_NS_M 0x7 |
| |
| |
| #define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_BP_S 2 |
| #define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_BP_M 0x4 |
| |
| #define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_SHAPE_SEL_S 1 |
| #define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_SHAPE_SEL_M 0x2 |
| |
| #define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_DLY_SEL_S 0 |
| #define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_DLY_SEL_M 0x1 |
| |
| |
| /* -- For CDC_ANC1_SPARE */ |
| #define TIMPANI_A_CDC_ANC1_SPARE (0xC4) |
| #define TIMPANI_CDC_ANC1_SPARE_RWC "RW" |
| #define TIMPANI_CDC_ANC1_SPARE_POR 0 |
| #define TIMPANI_CDC_ANC1_SPARE_S 0 |
| #define TIMPANI_CDC_ANC1_SPARE_M 0xFF |
| |
| |
| #define TIMPANI_CDC_ANC1_SPARE_ANC1_SPARE_S 0 |
| #define TIMPANI_CDC_ANC1_SPARE_ANC1_SPARE_M 0xFF |
| |
| |
| /* -- For CDC_ANC1_IIR_COEFF_PTR */ |
| #define TIMPANI_A_CDC_ANC1_IIR_COEFF_PTR (0xC5) |
| #define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_RWC "RW" |
| #define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_POR 0 |
| #define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_S 0 |
| #define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_M 0x1F |
| |
| |
| #define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_ANC1_IIR_COEFF_PTR_S 0 |
| #define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_ANC1_IIR_COEFF_PTR_M 0x1F |
| |
| |
| /* -- For CDC_ANC1_IIR_COEFF_MSB */ |
| #define TIMPANI_A_CDC_ANC1_IIR_COEFF_MSB (0xC6) |
| #define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_RWC "RW" |
| #define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_POR 0 |
| #define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_S 0 |
| #define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_M 0x1 |
| |
| |
| #define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_ANC1_IIR_COEFF_MSB_S 0 |
| #define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_ANC1_IIR_COEFF_MSB_M 0x1 |
| |
| |
| /* -- For CDC_ANC1_IIR_COEFF_LSB */ |
| #define TIMPANI_A_CDC_ANC1_IIR_COEFF_LSB (0xC7) |
| #define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_RWC "RW" |
| #define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_POR 0 |
| #define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_S 0 |
| #define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_M 0xFF |
| |
| |
| #define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_ANC1_IIR_COEFF_LSB_S 0 |
| #define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_ANC1_IIR_COEFF_LSB_M 0xFF |
| |
| |
| /* -- For CDC_ANC1_IIR_COEFF_CTL */ |
| #define TIMPANI_A_CDC_ANC1_IIR_COEFF_CTL (0xC8) |
| #define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_RWC "RW" |
| #define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_POR 0 |
| #define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_S 0 |
| #define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_M 0x3 |
| |
| |
| #define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_S 1 |
| #define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_M 0x2 |
| #define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_ADAPTIVE 0x1 |
| #define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_NON_ADAPTIVE 0x0 |
| |
| #define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_S 0 |
| #define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_M 0x1 |
| #define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_UPDATE 0x1 |
| #define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_NO_UPDATE 0x0 |
| |
| |
| /* -- For CDC_ANC1_LPF_COEFF_PTR */ |
| #define TIMPANI_A_CDC_ANC1_LPF_COEFF_PTR (0xC9) |
| #define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_RWC "RW" |
| #define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_POR 0 |
| #define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_S 0 |
| #define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_M 0xF |
| |
| |
| #define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_ANC1_LPF_COEFF_PTR_S 0 |
| #define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_ANC1_LPF_COEFF_PTR_M 0xF |
| |
| |
| /* -- For CDC_ANC1_LPF_COEFF_MSB */ |
| #define TIMPANI_A_CDC_ANC1_LPF_COEFF_MSB (0xCA) |
| #define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_RWC "RW" |
| #define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_POR 0 |
| #define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_S 0 |
| #define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_M 0xF |
| |
| |
| #define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_ANC1_LPF_COEFF_MSB_S 0 |
| #define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_ANC1_LPF_COEFF_MSB_M 0xF |
| |
| |
| /* -- For CDC_ANC1_LPF_COEFF_LSB */ |
| #define TIMPANI_A_CDC_ANC1_LPF_COEFF_LSB (0xCB) |
| #define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_RWC "RW" |
| #define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_POR 0 |
| #define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_S 0 |
| #define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_M 0xFF |
| |
| |
| #define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_ANC1_LPF_COEFF_LSB_S 0 |
| #define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_ANC1_LPF_COEFF_LSB_M 0xFF |
| |
| |
| /* -- For CDC_ANC1_SCALE_PTR */ |
| #define TIMPANI_A_CDC_ANC1_SCALE_PTR (0xCC) |
| #define TIMPANI_CDC_ANC1_SCALE_PTR_RWC "RW" |
| #define TIMPANI_CDC_ANC1_SCALE_PTR_POR 0 |
| #define TIMPANI_CDC_ANC1_SCALE_PTR_S 0 |
| #define TIMPANI_CDC_ANC1_SCALE_PTR_M 0x7 |
| |
| |
| #define TIMPANI_CDC_ANC1_SCALE_PTR_ANC1_SCALE_PTR_S 0 |
| #define TIMPANI_CDC_ANC1_SCALE_PTR_ANC1_SCALE_PTR_M 0x7 |
| |
| |
| /* -- For CDC_ANC1_SCALE */ |
| #define TIMPANI_A_CDC_ANC1_SCALE (0xCD) |
| #define TIMPANI_CDC_ANC1_SCALE_RWC "RW" |
| #define TIMPANI_CDC_ANC1_SCALE_POR 0 |
| #define TIMPANI_CDC_ANC1_SCALE_S 0 |
| #define TIMPANI_CDC_ANC1_SCALE_M 0xFF |
| |
| |
| #define TIMPANI_CDC_ANC1_SCALE_ANC1_SCALE_S 0 |
| #define TIMPANI_CDC_ANC1_SCALE_ANC1_SCALE_M 0xFF |
| |
| |
| /* -- For CDC_ANC1_DEBUG */ |
| #define TIMPANI_A_CDC_ANC1_DEBUG (0xCE) |
| #define TIMPANI_CDC_ANC1_DEBUG_RWC "RW" |
| #define TIMPANI_CDC_ANC1_DEBUG_POR 0 |
| #define TIMPANI_CDC_ANC1_DEBUG_S 0 |
| #define TIMPANI_CDC_ANC1_DEBUG_M 0xF |
| |
| |
| #define TIMPANI_CDC_ANC1_DEBUG_ANC1_DEBUG_SEL_S 0 |
| #define TIMPANI_CDC_ANC1_DEBUG_ANC1_DEBUG_SEL_M 0xF |
| |
| |
| /* -- For CDC_ANC2_CTL1 */ |
| #define TIMPANI_A_CDC_ANC2_CTL1 (0xD0) |
| #define TIMPANI_CDC_ANC2_CTL1_RWC "RW" |
| #define TIMPANI_CDC_ANC2_CTL1_POR 0 |
| #define TIMPANI_CDC_ANC2_CTL1_S 0 |
| #define TIMPANI_CDC_ANC2_CTL1_M 0x3F |
| |
| |
| #define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_S 5 |
| #define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_M 0x20 |
| #define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_FF_OUT_DIS 0x1 |
| #define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_FF_OUT_EN 0x0 |
| |
| #define TIMPANI_CDC_ANC2_CTL1_ANC2_ADC_DMIC_SEL_S 4 |
| #define TIMPANI_CDC_ANC2_CTL1_ANC2_ADC_DMIC_SEL_M 0x10 |
| #define TIMPANI_CDC_ANC2_CTL1_ANC2_ADC_DMIC_SEL_DMIC 0x1 |
| #define TIMPANI_CDC_ANC2_CTL1_ANC2_ADC_DMIC_SEL_ADC 0x0 |
| |
| #define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_S 3 |
| #define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_M 0x8 |
| #define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_LR_MIX_EN 0x1 |
| #define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_LR_MIX_DIS 0x0 |
| |
| #define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_S 2 |
| #define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_M 0x4 |
| #define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_FB_MIX_EN 0x1 |
| #define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_FB_MIX_DIS 0x0 |
| |
| #define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_S 1 |
| #define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_M 0x2 |
| #define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_ANC_EN 0x1 |
| #define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_ANC_DIS 0x0 |
| |
| #define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_S 0 |
| #define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_M 0x1 |
| #define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_ANC_RESET 0x1 |
| #define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_ANC_ACTIVE 0x0 |
| |
| |
| /* -- For CDC_ANC2_CTL2 */ |
| #define TIMPANI_A_CDC_ANC2_CTL2 (0xD1) |
| #define TIMPANI_CDC_ANC2_CTL2_RWC "RW" |
| #define TIMPANI_CDC_ANC2_CTL2_POR 0 |
| #define TIMPANI_CDC_ANC2_CTL2_S 0 |
| #define TIMPANI_CDC_ANC2_CTL2_M 0x1F |
| |
| |
| #define TIMPANI_CDC_ANC2_CTL2_ANC2_FREQ_SEL_S 0 |
| #define TIMPANI_CDC_ANC2_CTL2_ANC2_FREQ_SEL_M 0x1F |
| |
| |
| /* -- For CDC_ANC2_FF_FB_SHIFT */ |
| #define TIMPANI_A_CDC_ANC2_FF_FB_SHIFT (0xD2) |
| #define TIMPANI_CDC_ANC2_FF_FB_SHIFT_RWC "RW" |
| #define TIMPANI_CDC_ANC2_FF_FB_SHIFT_POR 0 |
| #define TIMPANI_CDC_ANC2_FF_FB_SHIFT_S 0 |
| #define TIMPANI_CDC_ANC2_FF_FB_SHIFT_M 0xFF |
| |
| |
| #define TIMPANI_CDC_ANC2_FF_FB_SHIFT_ANC2_FB_LPF_SHIFT_S 4 |
| #define TIMPANI_CDC_ANC2_FF_FB_SHIFT_ANC2_FB_LPF_SHIFT_M 0xF0 |
| |
| #define TIMPANI_CDC_ANC2_FF_FB_SHIFT_ANC2_FF_LPF_SHIFT_S 0 |
| #define TIMPANI_CDC_ANC2_FF_FB_SHIFT_ANC2_FF_LPF_SHIFT_M 0xF |
| |
| |
| /* -- For CDC_ANC2_RX_NS */ |
| #define TIMPANI_A_CDC_ANC2_RX_NS (0xD3) |
| #define TIMPANI_CDC_ANC2_RX_NS_RWC "RW" |
| #define TIMPANI_CDC_ANC2_RX_NS_POR 0x1 |
| #define TIMPANI_CDC_ANC2_RX_NS_S 0 |
| #define TIMPANI_CDC_ANC2_RX_NS_M 0x7 |
| |
| |
| #define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_BP_S 2 |
| #define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_BP_M 0x4 |
| |
| #define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_SHAPE_SEL_S 1 |
| #define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_SHAPE_SEL_M 0x2 |
| |
| #define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_DLY_SEL_S 0 |
| #define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_DLY_SEL_M 0x1 |
| |
| |
| /* -- For CDC_ANC2_SPARE */ |
| #define TIMPANI_A_CDC_ANC2_SPARE (0xD4) |
| #define TIMPANI_CDC_ANC2_SPARE_RWC "RW" |
| #define TIMPANI_CDC_ANC2_SPARE_POR 0 |
| #define TIMPANI_CDC_ANC2_SPARE_S 0 |
| #define TIMPANI_CDC_ANC2_SPARE_M 0xFF |
| |
| |
| #define TIMPANI_CDC_ANC2_SPARE_ANC2_SPARE_S 0 |
| #define TIMPANI_CDC_ANC2_SPARE_ANC2_SPARE_M 0xFF |
| |
| |
| /* -- For CDC_ANC2_IIR_COEFF_PTR */ |
| #define TIMPANI_A_CDC_ANC2_IIR_COEFF_PTR (0xD5) |
| #define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_RWC "RW" |
| #define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_POR 0 |
| #define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_S 0 |
| #define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_M 0x1F |
| |
| |
| #define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_ANC2_IIR_COEFF_PTR_S 0 |
| #define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_ANC2_IIR_COEFF_PTR_M 0x1F |
| |
| |
| /* -- For CDC_ANC2_IIR_COEFF_MSB */ |
| #define TIMPANI_A_CDC_ANC2_IIR_COEFF_MSB (0xD6) |
| #define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_RWC "RW" |
| #define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_POR 0 |
| #define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_S 0 |
| #define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_M 0x1 |
| |
| |
| #define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_ANC2_IIR_COEFF_MSB_S 0 |
| #define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_ANC2_IIR_COEFF_MSB_M 0x1 |
| |
| |
| /* -- For CDC_ANC2_IIR_COEFF_LSB */ |
| #define TIMPANI_A_CDC_ANC2_IIR_COEFF_LSB (0xD7) |
| #define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_RWC "RW" |
| #define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_POR 0 |
| #define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_S 0 |
| #define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_M 0xFF |
| |
| |
| #define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_ANC2_IIR_COEFF_LSB_S 0 |
| #define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_ANC2_IIR_COEFF_LSB_M 0xFF |
| |
| |
| /* -- For CDC_ANC2_IIR_COEFF_CTL */ |
| #define TIMPANI_A_CDC_ANC2_IIR_COEFF_CTL (0xD8) |
| #define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_RWC "RW" |
| #define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_POR 0 |
| #define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_S 0 |
| #define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_M 0x3 |
| |
| |
| #define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_S 1 |
| #define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_M 0x2 |
| #define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_ADAPTIVE 0x1 |
| #define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_NON_ADAPTIVE 0x0 |
| |
| #define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_S 0 |
| #define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_M 0x1 |
| #define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_UPDATE 0x1 |
| #define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_NO_UPDATE 0x0 |
| |
| |
| /* -- For CDC_ANC2_LPF_COEFF_PTR */ |
| #define TIMPANI_A_CDC_ANC2_LPF_COEFF_PTR (0xD9) |
| #define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_RWC "RW" |
| #define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_POR 0 |
| #define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_S 0 |
| #define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_M 0xF |
| |
| |
| #define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_ANC2_LPF_COEFF_PTR_S 0 |
| #define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_ANC2_LPF_COEFF_PTR_M 0xF |
| |
| |
| /* -- For CDC_ANC2_LPF_COEFF_MSB */ |
| #define TIMPANI_A_CDC_ANC2_LPF_COEFF_MSB (0xDA) |
| #define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_RWC "RW" |
| #define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_POR 0 |
| #define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_S 0 |
| #define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_M 0xF |
| |
| |
| #define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_ANC2_LPF_COEFF_MSB_S 0 |
| #define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_ANC2_LPF_COEFF_MSB_M 0xF |
| |
| |
| /* -- For CDC_ANC2_LPF_COEFF_LSB */ |
| #define TIMPANI_A_CDC_ANC2_LPF_COEFF_LSB (0xDB) |
| #define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_RWC "RW" |
| #define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_POR 0 |
| #define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_S 0 |
| #define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_M 0xFF |
| |
| |
| #define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_ANC2_LPF_COEFF_LSB_S 0 |
| #define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_ANC2_LPF_COEFF_LSB_M 0xFF |
| |
| |
| /* -- For CDC_ANC2_SCALE_PTR */ |
| #define TIMPANI_A_CDC_ANC2_SCALE_PTR (0xDC) |
| #define TIMPANI_CDC_ANC2_SCALE_PTR_RWC "RW" |
| #define TIMPANI_CDC_ANC2_SCALE_PTR_POR 0 |
| #define TIMPANI_CDC_ANC2_SCALE_PTR_S 0 |
| #define TIMPANI_CDC_ANC2_SCALE_PTR_M 0x7 |
| |
| |
| #define TIMPANI_CDC_ANC2_SCALE_PTR_ANC2_SCALE_PTR_S 0 |
| #define TIMPANI_CDC_ANC2_SCALE_PTR_ANC2_SCALE_PTR_M 0x7 |
| |
| |
| /* -- For CDC_ANC2_SCALE */ |
| #define TIMPANI_A_CDC_ANC2_SCALE (0xDD) |
| #define TIMPANI_CDC_ANC2_SCALE_RWC "RW" |
| #define TIMPANI_CDC_ANC2_SCALE_POR 0 |
| #define TIMPANI_CDC_ANC2_SCALE_S 0 |
| #define TIMPANI_CDC_ANC2_SCALE_M 0xFF |
| |
| |
| #define TIMPANI_CDC_ANC2_SCALE_ANC2_SCALE_S 0 |
| #define TIMPANI_CDC_ANC2_SCALE_ANC2_SCALE_M 0xFF |
| |
| |
| /* -- For CDC_ANC2_DEBUG */ |
| #define TIMPANI_A_CDC_ANC2_DEBUG (0xDE) |
| #define TIMPANI_CDC_ANC2_DEBUG_RWC "RW" |
| #define TIMPANI_CDC_ANC2_DEBUG_POR 0 |
| #define TIMPANI_CDC_ANC2_DEBUG_S 0 |
| #define TIMPANI_CDC_ANC2_DEBUG_M 0xF |
| |
| |
| #define TIMPANI_CDC_ANC2_DEBUG_ANC2_DEBUG_SEL_S 0 |
| #define TIMPANI_CDC_ANC2_DEBUG_ANC2_DEBUG_SEL_M 0xF |
| |
| |
| /* -- For CDC_LINE_L_AVOL */ |
| #define TIMPANI_A_CDC_LINE_L_AVOL (0xE0) |
| #define TIMPANI_CDC_LINE_L_AVOL_RWC "RW" |
| #define TIMPANI_CDC_LINE_L_AVOL_POR 0xac |
| #define TIMPANI_CDC_LINE_L_AVOL_S 0 |
| #define TIMPANI_CDC_LINE_L_AVOL_M 0xFF |
| |
| |
| #define TIMPANI_CDC_LINE_L_AVOL_USER_GAIN_S 2 |
| #define TIMPANI_CDC_LINE_L_AVOL_USER_GAIN_M 0xFC |
| |
| #define TIMPANI_CDC_LINE_L_AVOL_DUMMY_S 0 |
| #define TIMPANI_CDC_LINE_L_AVOL_DUMMY_M 0x3 |
| |
| |
| /* -- For CDC_LINE_R_AVOL */ |
| #define TIMPANI_A_CDC_LINE_R_AVOL (0xE1) |
| #define TIMPANI_CDC_LINE_R_AVOL_RWC "RW" |
| #define TIMPANI_CDC_LINE_R_AVOL_POR 0xac |
| #define TIMPANI_CDC_LINE_R_AVOL_S 0 |
| #define TIMPANI_CDC_LINE_R_AVOL_M 0xFF |
| |
| |
| #define TIMPANI_CDC_LINE_R_AVOL_USER_GAIN_S 2 |
| #define TIMPANI_CDC_LINE_R_AVOL_USER_GAIN_M 0xFC |
| |
| #define TIMPANI_CDC_LINE_R_AVOL_DUMMY_S 0 |
| #define TIMPANI_CDC_LINE_R_AVOL_DUMMY_M 0x3 |
| |
| |
| /* -- For CDC_HPH_L_AVOL */ |
| #define TIMPANI_A_CDC_HPH_L_AVOL (0xE2) |
| #define TIMPANI_CDC_HPH_L_AVOL_RWC "RW" |
| #define TIMPANI_CDC_HPH_L_AVOL_POR 0xae |
| #define TIMPANI_CDC_HPH_L_AVOL_S 0 |
| #define TIMPANI_CDC_HPH_L_AVOL_M 0xFF |
| |
| |
| #define TIMPANI_CDC_HPH_L_AVOL_USER_GAIN_S 2 |
| #define TIMPANI_CDC_HPH_L_AVOL_USER_GAIN_M 0xFC |
| |
| #define TIMPANI_CDC_HPH_L_AVOL_MUTE_S 1 |
| #define TIMPANI_CDC_HPH_L_AVOL_MUTE_M 0x2 |
| #define TIMPANI_CDC_HPH_L_AVOL_MUTE_MUTE 0x1 |
| #define TIMPANI_CDC_HPH_L_AVOL_MUTE_UNMUTE 0x0 |
| |
| #define TIMPANI_CDC_HPH_L_AVOL_DUMMY_S 0 |
| #define TIMPANI_CDC_HPH_L_AVOL_DUMMY_M 0x1 |
| |
| |
| /* -- For CDC_HPH_R_AVOL */ |
| #define TIMPANI_A_CDC_HPH_R_AVOL (0xE3) |
| #define TIMPANI_CDC_HPH_R_AVOL_RWC "RW" |
| #define TIMPANI_CDC_HPH_R_AVOL_POR 0xae |
| #define TIMPANI_CDC_HPH_R_AVOL_S 0 |
| #define TIMPANI_CDC_HPH_R_AVOL_M 0xFF |
| |
| |
| #define TIMPANI_CDC_HPH_R_AVOL_USER_GAIN_S 2 |
| #define TIMPANI_CDC_HPH_R_AVOL_USER_GAIN_M 0xFC |
| |
| #define TIMPANI_CDC_HPH_R_AVOL_MUTE_S 1 |
| #define TIMPANI_CDC_HPH_R_AVOL_MUTE_M 0x2 |
| #define TIMPANI_CDC_HPH_R_AVOL_MUTE_MUTE 0x1 |
| #define TIMPANI_CDC_HPH_R_AVOL_MUTE_UNMUTE 0x0 |
| |
| #define TIMPANI_CDC_HPH_R_AVOL_DUMMY_S 0 |
| #define TIMPANI_CDC_HPH_R_AVOL_DUMMY_M 0x1 |
| |
| |
| /* -- For CDC_COMP_CTL1 */ |
| #define TIMPANI_A_CDC_COMP_CTL1 (0xE4) |
| #define TIMPANI_CDC_COMP_CTL1_RWC "RW" |
| #define TIMPANI_CDC_COMP_CTL1_POR 0 |
| #define TIMPANI_CDC_COMP_CTL1_S 0 |
| #define TIMPANI_CDC_COMP_CTL1_M 0xFF |
| |
| |
| #define TIMPANI_CDC_COMP_CTL1_LO_CLK_EN_S 7 |
| #define TIMPANI_CDC_COMP_CTL1_LO_CLK_EN_M 0x80 |
| |
| #define TIMPANI_CDC_COMP_CTL1_HPH_CLK_EN_S 6 |
| #define TIMPANI_CDC_COMP_CTL1_HPH_CLK_EN_M 0x40 |
| |
| #define TIMPANI_CDC_COMP_CTL1_LO_SOFT_RESET_S 5 |
| #define TIMPANI_CDC_COMP_CTL1_LO_SOFT_RESET_M 0x20 |
| |
| #define TIMPANI_CDC_COMP_CTL1_HPH_SOFT_RESET_S 4 |
| #define TIMPANI_CDC_COMP_CTL1_HPH_SOFT_RESET_M 0x10 |
| |
| #define TIMPANI_CDC_COMP_CTL1_LO_R_EN_S 3 |
| #define TIMPANI_CDC_COMP_CTL1_LO_R_EN_M 0x8 |
| |
| #define TIMPANI_CDC_COMP_CTL1_LO_L_EN_S 2 |
| #define TIMPANI_CDC_COMP_CTL1_LO_L_EN_M 0x4 |
| |
| #define TIMPANI_CDC_COMP_CTL1_HPH_R_EN_S 1 |
| #define TIMPANI_CDC_COMP_CTL1_HPH_R_EN_M 0x2 |
| |
| #define TIMPANI_CDC_COMP_CTL1_HPH_L_EN_S 0 |
| #define TIMPANI_CDC_COMP_CTL1_HPH_L_EN_M 0x1 |
| |
| |
| /* -- For CDC_COMP_CTL2 */ |
| #define TIMPANI_A_CDC_COMP_CTL2 (0xE5) |
| #define TIMPANI_CDC_COMP_CTL2_RWC "RW" |
| #define TIMPANI_CDC_COMP_CTL2_POR 0xe |
| #define TIMPANI_CDC_COMP_CTL2_S 0 |
| #define TIMPANI_CDC_COMP_CTL2_M 0xF |
| |
| |
| #define TIMPANI_CDC_COMP_CTL2_LINEOUT_IN_MUX_S 2 |
| #define TIMPANI_CDC_COMP_CTL2_LINEOUT_IN_MUX_M 0xC |
| |
| #define TIMPANI_CDC_COMP_CTL2_HPH_IN_MUX_S 0 |
| #define TIMPANI_CDC_COMP_CTL2_HPH_IN_MUX_M 0x3 |
| |
| |
| /* -- For CDC_COMP_PEAK_METER */ |
| #define TIMPANI_A_CDC_COMP_PEAK_METER (0xE6) |
| #define TIMPANI_CDC_COMP_PEAK_METER_RWC "RW" |
| #define TIMPANI_CDC_COMP_PEAK_METER_POR 0x9 |
| #define TIMPANI_CDC_COMP_PEAK_METER_S 0 |
| #define TIMPANI_CDC_COMP_PEAK_METER_M 0xF |
| |
| |
| #define TIMPANI_CDC_COMP_PEAK_METER_TIME_OUT_S 0 |
| #define TIMPANI_CDC_COMP_PEAK_METER_TIME_OUT_M 0xF |
| |
| |
| /* -- For CDC_COMP_LEVEL_METER_CTL1 */ |
| #define TIMPANI_A_CDC_COMP_LEVEL_METER_CTL1 (0xE7) |
| #define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_RWC "RW" |
| #define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_POR 0x7 |
| #define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_S 0 |
| #define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_M 0xF |
| |
| |
| #define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_DIV_FACTOR_S 0 |
| #define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_DIV_FACTOR_M 0xF |
| |
| |
| /* -- For CDC_COMP_LEVEL_METER_CTL2 */ |
| #define TIMPANI_A_CDC_COMP_LEVEL_METER_CTL2 (0xE8) |
| #define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_RWC "RW" |
| #define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_POR 0x28 |
| #define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_S 0 |
| #define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_M 0xFF |
| |
| |
| #define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_RESAMPLE_RATE_S 0 |
| #define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_RESAMPLE_RATE_M 0xFF |
| |
| |
| /* -- For CDC_COMP_ZONE_SELECT */ |
| #define TIMPANI_A_CDC_COMP_ZONE_SELECT (0xE9) |
| #define TIMPANI_CDC_COMP_ZONE_SELECT_RWC "RW" |
| #define TIMPANI_CDC_COMP_ZONE_SELECT_POR 0x3b |
| #define TIMPANI_CDC_COMP_ZONE_SELECT_S 0 |
| #define TIMPANI_CDC_COMP_ZONE_SELECT_M 0x7F |
| |
| |
| #define TIMPANI_CDC_COMP_ZONE_SELECT_ENTRY_S 3 |
| #define TIMPANI_CDC_COMP_ZONE_SELECT_ENTRY_M 0x78 |
| |
| #define TIMPANI_CDC_COMP_ZONE_SELECT_SHIFT_S 0 |
| #define TIMPANI_CDC_COMP_ZONE_SELECT_SHIFT_M 0x7 |
| |
| |
| /* -- For CDC_COMP_ZC_MSB */ |
| #define TIMPANI_A_CDC_COMP_ZC_MSB (0xEA) |
| #define TIMPANI_CDC_COMP_ZC_MSB_RWC "RW" |
| #define TIMPANI_CDC_COMP_ZC_MSB_POR 0 |
| #define TIMPANI_CDC_COMP_ZC_MSB_S 0 |
| #define TIMPANI_CDC_COMP_ZC_MSB_M 0x7 |
| |
| |
| #define TIMPANI_CDC_COMP_ZC_MSB_DET_WINDOW_S 0 |
| #define TIMPANI_CDC_COMP_ZC_MSB_DET_WINDOW_M 0x7 |
| |
| |
| /* -- For CDC_COMP_ZC_LSB */ |
| #define TIMPANI_A_CDC_COMP_ZC_LSB (0xEB) |
| #define TIMPANI_CDC_COMP_ZC_LSB_RWC "RW" |
| #define TIMPANI_CDC_COMP_ZC_LSB_POR 0x1f |
| #define TIMPANI_CDC_COMP_ZC_LSB_S 0 |
| #define TIMPANI_CDC_COMP_ZC_LSB_M 0xFF |
| |
| |
| #define TIMPANI_CDC_COMP_ZC_LSB_DET_WINDOW_S 0 |
| #define TIMPANI_CDC_COMP_ZC_LSB_DET_WINDOW_M 0xFF |
| |
| |
| /* -- For CDC_COMP_SHUT_DOWN */ |
| #define TIMPANI_A_CDC_COMP_SHUT_DOWN (0xEC) |
| #define TIMPANI_CDC_COMP_SHUT_DOWN_RWC "RW" |
| #define TIMPANI_CDC_COMP_SHUT_DOWN_POR 0x1b |
| #define TIMPANI_CDC_COMP_SHUT_DOWN_S 0 |
| #define TIMPANI_CDC_COMP_SHUT_DOWN_M 0x3F |
| |
| |
| #define TIMPANI_CDC_COMP_SHUT_DOWN_HPH_TIMEOUT_S 3 |
| #define TIMPANI_CDC_COMP_SHUT_DOWN_HPH_TIMEOUT_M 0x38 |
| |
| #define TIMPANI_CDC_COMP_SHUT_DOWN_LO_TIMEOUT_S 0 |
| #define TIMPANI_CDC_COMP_SHUT_DOWN_LO_TIMEOUT_M 0x7 |
| |
| |
| /* -- For CDC_COMP_SHUT_DOWN_STATUS */ |
| #define TIMPANI_A_CDC_COMP_SHUT_DOWN_STATUS (0xED) |
| #define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_RWC "RW" |
| #define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_POR 0 |
| #define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_S 0 |
| #define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_M 0xF |
| |
| |
| #define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_LO_R_S 3 |
| #define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_LO_R_M 0x8 |
| |
| #define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_LO_L_S 2 |
| #define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_LO_L_M 0x4 |
| |
| #define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_R_S 1 |
| #define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_R_M 0x2 |
| |
| #define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_L_S 0 |
| #define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_L_M 0x1 |
| |
| |
| /* -- For CDC_COMP_HALT */ |
| #define TIMPANI_A_CDC_COMP_HALT (0xEE) |
| #define TIMPANI_CDC_COMP_HALT_RWC "RW" |
| #define TIMPANI_CDC_COMP_HALT_POR 0 |
| #define TIMPANI_CDC_COMP_HALT_S 0 |
| #define TIMPANI_CDC_COMP_HALT_M 0x1 |
| |
| |
| #define TIMPANI_CDC_COMP_HALT_COMPANDER_HALT_S 0 |
| #define TIMPANI_CDC_COMP_HALT_COMPANDER_HALT_M 0x1 |
| |
| |
| #endif |
