commit 4f1a0c315367150292da970280636d0fab54e848
author Ben Cheng <bccheng@google.com> Mon Mar 11 15:24:29 2013 -0700
committer Android Git Automerger <android-git-automerger@android.com> Mon Mar 11 15:24:29 2013 -0700
tree bf52442362c262e8a254c22c608879a3dff9080e
parent 1eaa1d6006bf9aa6ecb16deab052224c817a5669
parent 7434760b13067cf93f8efc2ead8c54a32b6b42e9

am 7434760b: Merge "Add support for ARM SMMLA instruction."

* commit '7434760b13067cf93f8efc2ead8c54a32b6b42e9':
  Add support for ARM SMMLA instruction.

main/VEX/priv/guest_arm_toIR.c

diff --git a/main/VEX/priv/guest_arm_toIR.c b/main/VEX/priv/guest_arm_toIR.c
index 4c5cb96..372c927 100644
--- a/main/VEX/priv/guest_arm_toIR.c
+++ b/main/VEX/priv/guest_arm_toIR.c
@@ -18826,6 +18826,30 @@
       }
    }
 
+   /* ------------------- (T1) SMMLA{R} ------------------ */
+   if (INSN0(15,7) == BITS9(1,1,1,1,1,0,1,1,0)
+       && INSN0(6,4) == BITS3(1,0,1)
+       && INSN1(7,5) == BITS3(0,0,0)) {
+      UInt bitR = INSN1(4,4);
+      UInt rA = INSN1(15,12);
+      UInt rD = INSN1(11,8);
+      UInt rM = INSN1(3,0);
+      UInt rN = INSN0(3,0);
+      if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM) && (rA != 13)) {
+         IRExpr* res
+         = unop(Iop_64HIto32,
+                binop(Iop_Add64,
+                      binop(Iop_Add64,
+                            binop(Iop_32HLto64, getIRegT(rA), mkU32(0)),
+                            binop(Iop_MullS32, getIRegT(rN), getIRegT(rM))),
+                      mkU64(bitR ? 0x80000000ULL : 0ULL)));
+         putIRegT(rD, res, condT);
+         DIP("smmla%s r%u, r%u, r%u, r%u\n",
+             bitR ? "r" : "", rD, rN, rM, rA);
+         goto decode_success;
+      }
+   }
+
    /* ----------------------------------------------------------- */
    /* -- VFP (CP 10, CP 11) instructions (in Thumb mode)       -- */
    /* ----------------------------------------------------------- */