| #define OFFSET_x86_EAX 8 |
| #define OFFSET_x86_EBX 20 |
| #define OFFSET_x86_ECX 12 |
| #define OFFSET_x86_EDX 16 |
| #define OFFSET_x86_ESI 32 |
| #define OFFSET_x86_EDI 36 |
| #define OFFSET_x86_EBP 28 |
| #define OFFSET_x86_ESP 24 |
| #define OFFSET_x86_EIP 68 |
| #define OFFSET_x86_CS 288 |
| #define OFFSET_x86_DS 290 |
| #define OFFSET_x86_ES 292 |
| #define OFFSET_x86_FS 294 |
| #define OFFSET_x86_GS 296 |
| #define OFFSET_x86_SS 298 |
| #define OFFSET_amd64_RAX 16 |
| #define OFFSET_amd64_RBX 40 |
| #define OFFSET_amd64_RCX 24 |
| #define OFFSET_amd64_RDX 32 |
| #define OFFSET_amd64_RSI 64 |
| #define OFFSET_amd64_RDI 72 |
| #define OFFSET_amd64_RSP 48 |
| #define OFFSET_amd64_RBP 56 |
| #define OFFSET_amd64_R8 80 |
| #define OFFSET_amd64_R9 88 |
| #define OFFSET_amd64_R10 96 |
| #define OFFSET_amd64_R11 104 |
| #define OFFSET_amd64_R12 112 |
| #define OFFSET_amd64_R13 120 |
| #define OFFSET_amd64_R14 128 |
| #define OFFSET_amd64_R15 136 |
| #define OFFSET_amd64_RIP 184 |
| #define OFFSET_ppc32_GPR0 16 |
| #define OFFSET_ppc32_GPR1 20 |
| #define OFFSET_ppc32_GPR2 24 |
| #define OFFSET_ppc32_GPR3 28 |
| #define OFFSET_ppc32_GPR4 32 |
| #define OFFSET_ppc32_GPR5 36 |
| #define OFFSET_ppc32_GPR6 40 |
| #define OFFSET_ppc32_GPR7 44 |
| #define OFFSET_ppc32_GPR8 48 |
| #define OFFSET_ppc32_GPR9 52 |
| #define OFFSET_ppc32_GPR10 56 |
| #define OFFSET_ppc32_CIA 1168 |
| #define OFFSET_ppc32_CR0_0 1185 |
| #define OFFSET_ppc64_GPR0 16 |
| #define OFFSET_ppc64_GPR1 24 |
| #define OFFSET_ppc64_GPR2 32 |
| #define OFFSET_ppc64_GPR3 40 |
| #define OFFSET_ppc64_GPR4 48 |
| #define OFFSET_ppc64_GPR5 56 |
| #define OFFSET_ppc64_GPR6 64 |
| #define OFFSET_ppc64_GPR7 72 |
| #define OFFSET_ppc64_GPR8 80 |
| #define OFFSET_ppc64_GPR9 88 |
| #define OFFSET_ppc64_GPR10 96 |
| #define OFFSET_ppc64_CIA 1296 |
| #define OFFSET_ppc64_CR0_0 1325 |
| #define OFFSET_arm_R0 8 |
| #define OFFSET_arm_R1 12 |
| #define OFFSET_arm_R2 16 |
| #define OFFSET_arm_R3 20 |
| #define OFFSET_arm_R4 24 |
| #define OFFSET_arm_R5 28 |
| #define OFFSET_arm_R7 36 |
| #define OFFSET_arm_R13 60 |
| #define OFFSET_arm_R14 64 |
| #define OFFSET_arm_R15T 68 |
| #define OFFSET_s390x_r2 208 |
| #define OFFSET_s390x_r3 216 |
| #define OFFSET_s390x_r4 224 |
| #define OFFSET_s390x_r5 232 |
| #define OFFSET_s390x_r6 240 |
| #define OFFSET_s390x_r7 248 |
| #define OFFSET_s390x_r15 312 |
| #define OFFSET_s390x_IA 336 |
| #define OFFSET_s390x_SYSNO 344 |
| #define OFFSET_s390x_IP_AT_SYSCALL 408 |
| #define OFFSET_s390x_fpc 328 |
| #define OFFSET_s390x_CC_OP 352 |
| #define OFFSET_s390x_CC_DEP1 360 |
| #define OFFSET_s390x_CC_DEP2 368 |
| #define OFFSET_s390x_CC_NDEP 376 |
| #define OFFSET_mips32_r0 0 |
| #define OFFSET_mips32_r1 4 |
| #define OFFSET_mips32_r2 8 |
| #define OFFSET_mips32_r3 12 |
| #define OFFSET_mips32_r4 16 |
| #define OFFSET_mips32_r5 20 |
| #define OFFSET_mips32_r6 24 |
| #define OFFSET_mips32_r7 28 |
| #define OFFSET_mips32_r8 32 |
| #define OFFSET_mips32_r9 36 |
| #define OFFSET_mips32_r10 40 |
| #define OFFSET_mips32_r11 44 |
| #define OFFSET_mips32_r12 48 |
| #define OFFSET_mips32_r13 52 |
| #define OFFSET_mips32_r14 56 |
| #define OFFSET_mips32_r15 60 |
| #define OFFSET_mips32_r15 60 |
| #define OFFSET_mips32_r17 68 |
| #define OFFSET_mips32_r18 72 |
| #define OFFSET_mips32_r19 76 |
| #define OFFSET_mips32_r20 80 |
| #define OFFSET_mips32_r21 84 |
| #define OFFSET_mips32_r22 88 |
| #define OFFSET_mips32_r23 92 |
| #define OFFSET_mips32_r24 96 |
| #define OFFSET_mips32_r25 100 |
| #define OFFSET_mips32_r26 104 |
| #define OFFSET_mips32_r27 108 |
| #define OFFSET_mips32_r28 112 |
| #define OFFSET_mips32_r29 116 |
| #define OFFSET_mips32_r30 120 |
| #define OFFSET_mips32_r31 124 |
| #define OFFSET_mips32_PC 128 |
| #define OFFSET_mips32_HI 132 |
| #define OFFSET_mips32_LO 136 |
